JPH03273786A - Image pickup device - Google Patents

Abstract

PURPOSE:To stably output a sub carrier and a burst signal without affecting the frequency of the second reference frequency signal with the frequency change of the first reference frequency by canceling the PLL control of the first and second reference frequency signals at the time of an external synchronizing mode. CONSTITUTION:In the case of the external synchronizing mode, an external synchronizing signal input discriminating circuit 11 detects that an external synchronizing signal is inputted from an input terminal 20, the voltage value of a signal line 15 is turned to a constant value and the frequency to be outputted from an Nfsc oscillator 10 is forcibly fixed. When the control voltage of the signal line 15 reaches a certain constant value, the Nfsc oscillator 10 to output an Nfsc clock signal is stably oscillated with the frequency Nfsc at the frequency of the voltage value. Thus, when the frequency Nfsc is stablized, the frequencies of the sub carrier and the burst signal to be outputted from a sub carrier burst generating circuit and a PLL circuit 8 are made stable as well.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application The present invention is directed to, for example, PAL (Pha...
The present invention relates to an imaging device such as an Alternative by Line color video camera.

[Prior Art] Conventionally, a PAL video camera system using a solid-state image sensor is configured as shown in FIG. Here, 201 is a lens optical system, and the lens 201
a and a crystal low-pass filter 201b, which focuses an image on a CCD 202, which is a solid-state image sensor. Each of the RGB signals output from this CCD 202 is transmitted to a pre-processing circuit 203 and a process processing circuit 20.
4, the signal is converted into a color difference signal and a luminance signal, and the encoder 2205 outputs the signal as a video output signal.

206 is an Mf oscillation circuit that generates a signal of frequency Mf;
07 is N f which outputs a frequency signal of frequency Nf, c
It is a sc oscillator. 208 is a clock pulse generator;
Input the Mf frequency signal from the Mf oscillator 206, and
It outputs pulse signals for D drive and various timing signals used for video processing. A driver 209 drives the CCD 202. 211 subcarrier bast oscillator and PLL circuit, input Mf multiplied signal Nf, c signal,
When these are out of synchronization, the Nfsc control voltage signal 212 is outputted to adjust the frequency of the Nfsc signal. Further, the phase comparator 210 inputs an external synchronization signal, and connects the external synchronization signal and the clock signal output from the clock pulse generator 208 to a PLL circuit 2.
11, and when they are out of synchronization, a control voltage signal 213 is output to adjust the frequency of the signal of frequency Mf output from the Mf oscillation circuit 206.

In this way, the frequency Mf for driving the solid-state image sensor 202
Frequency Nf that constitutes the signal, burst, and subcarrier
SC is normally operated by applying PLL. In this system, in the external synchronization mode, especially in the V-H synchronization system (vertical synchronization and horizontal synchronization), when the external synchronization signal is input to the phase comparator 210, it is inputted from the outside with the horizontal synchronization signal of the camera body. Control voltage signal 2 based on the phase difference by comparing the phase with the horizontal synchronization signal
13 is output to the Mf oscillation circuit 206. When this Mf oscillation circuit 206 receives the control voltage signal 213 from the phase comparator 21O, it changes the oscillation frequency of the clock signal to be output according to the voltage, thereby achieving synchronization with an external synchronizing signal.

[Problems to be Solved by the Invention] As described above, in the above conventional example, in the external synchronization mode, phase comparison is performed for the external synchronization signals ■ and H, and the control voltage signal 213 is generated based on the phase error. By changing the oscillation frequency of the fundamental frequency Mf of the clock pulse generator 208, the timings of ■ and H are matched with the ■ and H synchronization signals of the camera body. but,
In PAL color video camera systems, the fundamental frequency M
f and burst, Nf for subcarrier configuration, and PLL
Therefore, if the frequency of Mf is directly controlled by the phase in external synchronization mode, it will also affect NfsC, which applies PLL.

Therefore, if the amount of change in V and H is larger than the lock range of the PLL with the Nfsc oscillation circuit 207 for subcarrier and burst configuration, the PLL between Mf and Nfsc loses lock and the burst and subcarrier Frequency was disturbed, which sometimes caused problems with color video output.

The present invention has been made in view of the above-mentioned conventional example, and in the external synchronization mode, by canceling the PLL control of Mf and Nfsc, the phase (frequency) of the external synchronization signal and V, H synchronization is changed between Mf and Nfsc. To provide an imaging device that can stably output a subcarrier and a burst signal without affecting the frequency of Nf3c due to a change in the frequency of Mf, even if the change is larger than the lock range of a PLL.

[Means for Solving the Problems] In order to achieve the above object, an imaging device of the present invention has the following configuration. That is, an image capturing means, an image signal processing means for processing an image signal from the image capturing means, a video output means for converting the image signal into a video signal and outputting the same, and a first reference frequency signal inputted to the video signal. a timing signal generating means for outputting a timing signal to be outputted to the imaging means and the image signal processing means; and a frequency generating means for generating a second reference frequency signal serving as a reference for a subcarrier signal and a burst signal in the video output means. A PAL type imaging device comprising: an adjusting means for adjusting the frequencies of the first and second reference frequency signals by performing PLL control on the first and second reference frequency signals; and an external synchronization signal. frequency changing means for changing the frequency of the first reference frequency signal based on the phase difference between the first reference frequency signal and the internal synchronizing signal; a determining means for determining that the external synchronizing signal is input; and inhibiting means for inhibiting PLL control in the adjusting means when it is determined that a synchronization signal has been input.

[Operation] In the above configuration, by the determination means for determining that an external synchronization signal has been input. When it is determined that the external synchronization signal has been input, the first and second reference frequency signals are controlled by PLL to prohibit adjustment of the frequencies of the first and second reference frequency signals. ing. This results in
Only the frequency of the first reference frequency signal is adjusted by the external synchronization signal, and the frequency of the second reference frequency signal becomes a stable constant frequency, making the subcarrier and burst signal stable.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[Description of configuration of color video camera (FIG. 1)] FIG. 1 is a block diagram showing the schematic configuration of a PAL color video camera using a solid-state image sensor according to an embodiment of the present invention.

In the figure, 1 indicates a lens optical system, 1a is a lens,
1b indicates a crystal low-pass filter. 2 is a CCD which is a solid-state image sensor. 3 converts the R, G, and B signals output from the solid-state image sensor 2 into AGC, clamp, and knee
e) A Buri process circuit that processes characteristic luminance signals. 4 is a process processing circuit, R (red), B (blue), G (green), Y (
Input the brightness), process the blanking gamma, W, C (white clip), etc., and input the B-Y, R-
It is converted into a Y color difference signal and a luminance (Y) signal and output. 6 is an encoder circuit that outputs P from the color difference signal and the luminance signal.
An AL composite video signal is created and output as a video signal.

7 is an Mf oscillation circuit which outputs a clock signal of frequency Mf (H2). 5 is a clock synchronization signal generator;
A clock signal having a frequency of MfH2 from the Mf oscillation circuit 7 is input as a basic frequency signal, and pulses for COD driving and various timing pulse signals used for video signal processing are output.

12 is a driver circuit that drives C0D2.

10 is an oscillation circuit of Nfsc, and 8 is a subcarrier, burst generator, and PLL circuit, which applies PLL to signals of frequencies N f sc and Mf to generate subcarrier and burst signals.

20 is an external synchronization signal input terminal, and 9 is a phase comparator and a control voltage generation circuit, which input external synchronization signals (V, H synchronization signals) and the synchronization signal of the camera body output from the clock synchronization signal generator 5. The Mf oscillation circuit 7 operates to change the frequency of the reference frequency signal outputted from the Mf oscillation circuit 7 by comparing the phases of the Mf oscillation circuit 7. 11 is an external synchronization signal input determination circuit.

The operation of the circuit with the above configuration will be explained. Now, when the camera body is operating in internal synchronization mode (when no external synchronization signal is input), the value of the control voltage signal 13 output from the phase comparator 9 is a constant value, and M
The frequency Mf of the signal output from the f oscillation circuit 7 is a stable and constant frequency of 1.

When the constant frequency Mf (H2) signal is input to the subcarrier, burst generator, and PLL circuit 8 via the signal line 14, it is phase-compared with the frequency Nfg from the Nf,c oscillator 10, and then sent to the signal line 15. Nfsc oscillator 10 via
A subcarrier frequency control voltage signal is output. As a result, the signal with the frequency Nfsc output from the Nfsc oscillator 10 and the signal with the frequency Mf are connected to the PLL.
Controlled subcarrier burst generator and PLL circuit 8
More stable subcarrier and burst signals are output.

On the other hand, in the case of external synchronization mode, an external synchronization signal is input from the input terminal 20, and the phase is compared with the internal (camera) synchronization signal 16 by the phase comparator 9.
The MfH2 oscillation control type pressure signal 13 is output. As a result, the oscillation frequency output from the Mf oscillation circuit 7 is controlled.

Now, △Mf(H2) by the control voltage signal 13
When a clock signal whose frequency is (Mf+ΔMf) whose frequency is controlled is input to the subcarrier generator and the PLL circuit 8 via the signal line 14, PLL control is executed between the frequency Nfllc and the clock signal whose frequency is (Mf+ΔMf). As a result, the Nfsc oscillation frequency output from the NfIlc oscillation 10 through the signal line 15 is controlled to ΔN f sc, and the subcarrier and burst frequencies output from the subcarrier generator and PLL circuit 8 also change. become.

However, in this embodiment, the external synchronization signal input determination circuit 1
1 detects that an external synchronizing signal is input from the input terminal 20, sets the voltage value of the signal line 15 to a constant value, and adjusts the frequency (Nf
go) is forcibly fixed. Note that when the control voltage of the signal line 15 reaches a certain constant value, the Nf,0 oscillator 10 that outputs the Nfsc clock signal stably oscillates at the frequency of that voltage value Nf,c. In this way, when the frequency Nfsc becomes stable, the subcarrier
The subcarrier and burst frequencies output from the burst generation circuit and PLL circuit 8 are also stabilized.

As explained above, according to this embodiment, in a PAL video camera using a solid-state image sensor, the fundamental frequency Mf (H2) for creating a reference frequency signal for driving the solid-state image sensor and the pulse for video signal processing, and the sub-frequency In a system that performs PLL control of frequencies Nf and c for creating carriers and burst signals, in the case of internal synchronization mode, Mf and Nfll
c means camera operation while performing PLL operation, and when an external synchronization signal is input, stabilizes Nfg by canceling PLL control of subcarrier oscillation frequency N f sc and frequency Mf. It is possible to output subcarriers and burst signals.

Thereby, the camera can be operated without causing problems in the image even in the external synchronization mode.

[Effects of the Invention] As explained above, according to the present invention, in the external synchronization mode, by canceling the PLL control of the first and second reference frequency signals, the phase ( Even if the frequency of the first reference frequency varies greatly, the subcarrier and burst signal can be stably output without the frequency change of the first reference frequency affecting the frequency of the second reference frequency signal. be.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a PAL color video camera according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional PAL color video camera. In the figure, 1... Lens optical system, 2... CCD, 3...
・Bri process circuit, 4... Process processing circuit, 5・
... Clock synchronization signal generator, 6... Encoder circuit, 7... Mf oscillation circuit, 8... Subcarrier, burst generator, and PLL circuit, 9... Phase comparator and control voltage generation circuit, 10...Nf8c oscillator, 11
. . . External synchronous signal input determination circuit, 12 . . . Driver, 20 . . . External synchronous input terminal. 6

Claims (1)

[Scope of Claims] An imaging means, an image signal processing means for processing an image signal from the imaging means, a video output means for converting the image signal into a video signal and outputting it, and a first reference frequency signal. timing signal generating means for outputting a timing signal inputted and output to the imaging means and the image signal processing means; and a second reference frequency signal generating a second reference frequency signal serving as a reference for a subcarrier signal and a burst signal in the video output means. A PAL type imaging device having a frequency generating means, the first and second reference frequency signals being subjected to PLL control,
an adjusting means for adjusting the frequency of the first and second reference frequency signals; a frequency changing means for changing the frequency of the first reference frequency signal based on a phase difference between an external synchronization signal and an internal synchronization signal; A determining means for determining that the external synchronizing signal has been input; and a prohibiting means for prohibiting PLL control in the adjusting means when the determining means determines that the external synchronizing signal has been input. An imaging device characterized by: