JPH03273709A - Phase control circuit - Google Patents

Abstract

PURPOSE:To secure the coincidence of frequency stability between a phase control circuit and a source oscillator by selecting a signal of the corresponding phase out of a delay circuit equivalent to one cycle of an input signal to be controlled by means of a selector and an up-down counter of an (n) modulo. CONSTITUTION:The waveform of an input signal SIG to be controlled is sampled by a delay circuit 11 and delayed by an extent equivalent to one cycle. Then each tap of the circuit 11 is set opposite to the value held by an up-down counter 13. A sample of the phase value shown by the counter 13 is taken out of the corresponding tap of the circuit 11 by a selector 12. As the counter 13 serves an n-notation counter, the total (n) pieces of signals, i.e., (n) phases of signals which are delayed every 1/n cyles of the signal SIG are obtained and selected by the selector 12. Thus a signal having the corresponding phase is selected out of the circuit 11 equivalent to one cycle of the signal SIG. As a result, the coincidence of frequency coincidence is secured between a phase control circuit and a source oscillator.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a synchronization circuit, a phase modulation circuit, or a phase control circuit used for demodulation, modulation, etc. in communication equipment.

BACKGROUND ART Conventionally, as a technique of this kind, there is a technique shown in "High Frequency Circuit Design Know-how" (by Takeshi Yoshida, pp. 120-123, published by CQ Publishing Co., Ltd., 1985) (Reference 1). This is a voltage controlled crystal oscillator (vcxo) using a varicap.
oscillator). The Q of a crystal oscillator is approximately 10"~10"', which is much higher than that of a normal LC resonant circuit (voltage controlled oscillator using LC), making it a highly stable oscillator with little frequency change due to aging or temperature changes. is obtained.

Also, "Frequency processing circuits and filter circuits" (Takashi Koga, Bessatsu Electronics Life, (Introduction) AV electronic circuits, pp. 95-98, published by Japan Broadcasting Publishing Association, 198
March 1, 1998) (Reference 2) discloses a voltage controlled oscillation circuit using a -90° phase circuit.

Problems to be Solved by the Invention Crystal oscillators have a high Q, so when used as a VCXO as in Reference 1, it is difficult to widen the variable range of the oscillation frequency, and it is difficult to use a normal crystal oscillator without voltage control. Frequency stability is worse than . This also applies to the one described in Document 2.

In other words, VCXO and VCO are essentially for controlling frequency, not for controlling phase. Therefore, it is not suitable for Application 4, where the phase needs to be delicately controlled.

Therefore, an object of the present invention is to obtain a circuit that can freely control the phase of a highly stable source oscillator, such as a crystal oscillator or an atomic oscillator, without impairing the oscillation stability at all.

Furthermore, the frequency can be changed by continuously changing the phase over time, but this also does not impair the stability of the source oscillator. Here, it is also an object of the present invention to obtain a highly stable frequency with a certain offset from the frequency of a highly stable source oscillator.

Means for Solving the Problems In the invention as set forth in claim 1, a periodic controlled input signal is input and a signal of n phases every 1/n (n is an integer) of the period of the controlled input signal is outputted. , a modulo n up/down counter, and a selector that uses the output signal of the up/down counter as a selection control signal and the n-phase output signal from the delay circuit as a selected signal.

In the invention according to claim 2 or 3, a periodic controlled input signal is input and the period of the controlled input signal is 17n(
shifted by a clock with a period of (n is an integer) (n-1)
A stage or n-stage shift register and a modulo n up-down counter are provided, and the output signal of the up-down counter is used as a selection control signal, and the input signal to the shift register and the (n-1) stage shift register are provided. A selector is provided that uses the output signal of each stage of the n-stage shift register as the selected signal, or the output signal of each stage of the n-stage shift register as the selected signal.

The waveform of the active controlled input signal is sampled by a delay circuit;
A delay of one cycle is performed. Each tap of this delay circuit is made to correspond to a value held by an up/down counter, and a sample of the phase value indicated by this counter is taken out from the corresponding tap of the delay circuit by a selector. Here, since the up/down counter is modulo n1, that is, it is an n-ary counter, a total of n signals, that is, n-phase signals are created by delaying the controlled input signal every 1/n periods, and the n-phase signals are delayed every 1/n periods of the controlled input signal. A signal is selected by a selector. This selected phase number corresponds to the value of the counter. In this way, since the signal of the corresponding phase is selected from the delay circuit for one period of the controlled input signal, the frequency stability completely matches that of the source oscillator. Furthermore, it is easy to lock to an arbitrary phase without changing the frequency.

Therefore, it is also possible to handle a controlled input signal that is an analog signal by using an analog configuration of the delay circuit and selector. In addition, as in the invention according to claim 2 or 3, (n-1)
A simple configuration using a stage or n-stage shift register as a delay circuit may be used, and the configuration may be configured exclusively for the rectangular wave representing the logic 110.

Applications of the present invention that exhibit such effects will be described.

First, considering communication, especially the synchronization of code transmission,
The symbol transmission rate on the transmitting side is generally determined by a sufficiently stable crystal oscillator.

On the other hand, on the receiving side, the symbol transmission rate is known in advance with sufficiently high accuracy, but the arrival phase of the symbol cannot be predicted in advance. Therefore, it is necessary to sample the symbol that has arrived (ie, received) at the receiving end in accordance with the phase of the symbol.

This is the well-known symbol synchronization problem.

Various methods are known for this symbol synchronization, but in the field of high-speed transmission, the V
It is common practice to perform symbol synchronization by finely adjusting the frequency of the oscillator of the CO or VCXO. Information for this fine adjustment of the frequency is usually obtained by comparing the phase of the received symbol with the phase of the oscillator. This phase comparison is not related to the gist of the present invention, so the details will be omitted, but if the sample phase of the received symbol does not match the phase of the oscillator, it is necessary to adjust the oscillation phase of the oscillator. Now, if it is necessary to advance (or delay) the oscillation phase, the oscillation frequency of the oscillator will be raised (or lowered) until the phases match, and the target phase and frequency will be asymptotically approached. The problem here is that when the oscillation frequency is raised, for example, if disturbances such as noise or instantaneous interruptions occur, a phenomenon occurs in which the sample phase becomes progressively faster. Normally, in such a case, you should temporarily stop changing the oscillation frequency, but the VCO or VCXO
In this case, the oscillation accuracy is not sufficient, so temporarily stopping the frequency change has no effect. This phenomenon originally originates from the fact that the properties of the oscillator (which can oscillate with sufficient precision) are not accurately utilized. In this regard, by applying the present invention which exhibits the above-described effects, it is possible to maintain sufficiently high frequencies of the oscillators not only on the transmitting side but also on the receiving side, and only the sampling phase can be controlled on the receiving side. Therefore, if the sample phase correction is stopped in the event of the above-mentioned disturbance, the previous sample phase can be maintained for a long period of time.
It becomes an extremely high performance receiver.

Another application is in atomic clocks and atomic oscillators. In recent years, many rubidium atomic oscillators using semiconductor lasers as excitation light sources have begun to be used. However, ““R
"Laser spectroscopy and frequency control of semiconductor lasers for b-atomic oscillators" (written by Minoru Hashimoto et al., Journal of the Institute of Electrical Engineers of Japan C0Vo
Q, l O8-CON.

9, I) I), 706-712.1988) (Reference 3)
In particular, as stated in Nos. 710 to 711, the reference frequency of the atomic oscillator is the microtransition frequency (approximately 6°8 GHz) between the hyperfine levels of the ground state of the Rb atom.
It shifts slightly depending on the frequency and power of the pumping light. This effect, called optical shift, limits the frequency accuracy of rubidium atomic oscillators. However, this optical shift characteristic can be determined quantitatively, and even if it cannot be calculated in advance, it can be measured as a stable value.

In other words, it can be said that although frequency accuracy decreases, frequency stability does not decrease significantly.

By applying the present invention, it is possible to correct the decrease in frequency accuracy due to this optical shift characteristic. For example, by using the well-known frequency synthesis method from atomic frequencies, 5 MH
Suppose that the signals of z are combined. This synthesized 5MH
z signal has a frequency stability of 10-” or 10
-" can be maintained, but the frequency accuracy is 10-"L. Now, assuming the frequency is 10-" lower than the true value, 5 MH
It is only necessary to advance the phase of the z signal continuously. According to the present invention, a method for controlling this phase is provided. That is, in the embodiment described later, one cycle is sampled 16 times, and the phase can be adjusted with a resolution of 1/16 cycle. Specifically, the deviation of a 5 MHz signal with a frequency error of 10-" from its true value by 1/8 period is (1/16) / (10-"x5x
lo@)=1250 seconds later. That is, the synthesized 5
It is sufficient to advance the phase of the MHz signal by 1/16 period after 1250 seconds. In this case, the phase of 1/16 period jumps, so this phase adjustment (frequency adjustment)
The resulting 5 MHz signal includes a phase error (resolution) of a maximum of 1/8 period. In this example, (1
/16) 15XIO"' = 12,5X10-' seconds, that is, the resolution is 12゜5 n5ec. The combined signal is 10MHz, one period is 8 samples, and the phase is adjusted with a resolution of 1/8 period. The same applies if the resolution is the resolution of the phase adjuster, and can be designed freely.Specifically, the value of the integer n referred to in the present invention can be changed as necessary. Just make it bigger.

Embodiment A first embodiment of the present invention will be explained based on FIG. This embodiment shows an example in which n=8. First, a highly stable crystal oscillator 1 is provided as an oscillator (O20). A counter (CNT) 2 is connected to the crystal oscillator 1 .

This counter 2 is a modulo 8 counter, specifically a 5N7 IC manufactured by Texas Instruments.
A synchronous 4-bit counter called 4LS163 is used. Here, in this embodiment, only the lower three bits of the four bits are used. A shift register (SR7) 3 is connected to this counter 2. Furthermore, in the subsequent stage, there is a (n-1)=7 stage shift register (SR
6-5RO) 4-10 are connected to form a delay circuit 11. Each of the shift registers 3 to 10 has a D-type flip-flop configuration, and by using eight of them, an 8-bit shift register configuration is obtained. These shift registers (SR7 to 5RO) 3 to 1o use the output signal SIG from the counter 2 as a controlled input signal, and the output signals P1 to P0 of each stage are input to the selector 1 as selected signals.
2 is entered. On the other hand, this selector 12 receives a selection control signal Q. -Up/down counter 1 that inputs QA
3 is connected.

This up/down counter 13 includes a shift register (SRADV) 14 having a D-type flip-flop configuration, (S
RRET) 15 is connected. Further, a shift register (SROUT) 16 having a D-type flip-flop configuration is connected to the output side of the selector 12.

Here, the controlled input signal whose phase is to be controlled is the signal SIG output from the counter 2. This signal S
IG has periodicity, and if its period is Ts,
The period of the clock CLK is Ts/8 (= Ts
/n). Therefore, the shift register (SR7
~5RO) 3 to 10 function as delay lines that store and delay the controlled input signal SIG over one period, and a delay circuit 11 is formed here. That is, the shift register (SR
7-5RO) The delay time between each tap of 3-10 is Ts
/ 8.

Each output P of shift register (SR7-5RO) 3-10
7-P. are shifted in phase by a time of Ts/8, and these outputs P, ~P0 are the selected signal terminals of the selector 12, ~D. is input. This selector 12 is, for example, an IC 5 manufactured by Texas Instruments.
A N74LS251 data selector/three-state output multiplexer is used. Here, A of selector 12,
For B and C terminals, A is LSB (least significant bit),
If C is MSB (most significant bit), the binary input values i indicated by C, B, and A are selected signal terminals D1 to D. Di is selected and output to Y. This binary input value l indicates the phase number of the controlled input signal SIG. As the up/down counter 13 for controlling the selector 12, a synchronous 4-bit up/down counter such as 5N74LS192, which is an IC manufactured by Texas Instruments, is used, for example. Here, since it is used as a modulo 8 counter, only the lower three bits of the four bits are used. Each time a rising pulse is input to the up-count terminal or down-count terminal of the up-down counter 13, a count-up or count-down operation is performed, respectively. Since the count value 1 held by this up/down counter 13 corresponds to the phase number i of the controlled input signal SIG mentioned above, each time this counter 13 counts up or down, the output Y of the selector 12 becomes T s / A signal whose phase is advanced or delayed by a time of 8 is output. Here, ADVANC
E or RERARD indirectly causes the up/down counter 13 to operate up or down through the shift registers 14 and 15. That is, although these shift registers 14 and 15 are not necessarily essential, they are used to synchronize the operation timing of the up/down counter 13 with the clock CLK. In addition, the output shift register 16 is connected to the control input of the selector 12 (
This is to eliminate glitches that tend to occur when the parameters A, B, and C) change. Here, since the occurrence of glitches can be prevented by making the circuit configuration stricter, this shift register 16 may be omitted.

5 Furthermore, since a synchronous counter is used as the counter 2 in this embodiment, it is clear that the first shift register 3 can also be omitted. That is, it may be a (nl) stage shift register.

However, asynchronous counters, such as 5N
When using a dependent counter with ripple carry such as 74LS93, the output signal of the counter, that is, the controlled input signal SIG, has a slight delay, so shift register (SR7) 3 is omitted and this is directly transferred to the shift register. If (SR6) is input as 4 (P and P are the same), the shift operation may become abnormal.

Therefore, in this case, in order to avoid malfunctions, the shift register (SR7) may be made indispensable, and an eight-stage (n-stage) shift register configuration may be used.

In this embodiment, the output CLK of the oscillator 1 is divided by 1/n to generate the controlled input signal SIG, but as shown in FIG. 2, the controlled input value No. 16 SIG is directly output. An oscillator 17 is provided, and an n multiplier 1
The clock CLK may be generated by multiplying this by n by 8. The n-multiplying method may be a general method of distorting the input signal and extracting its harmonics using a resonant circuit, or a frequency synthesis method using a PLL.

When the clock CLK is generated using such a multiplication method, the phase relationship between the controlled input signal SIG and the clock CLK becomes complicated, so it is preferable that the number of shift register stages constituting the delay circuit 11 be n stages. .

Next, a second embodiment of the present invention will be described with reference to FIG. This embodiment shows an example in which n=16. First, the highly stable crystal oscillator 21 has n
=16 delay circuits (DL15 to DLO) 22, 23 .
, 35, 36, and 37 are connected in order. Therefore,
These delay circuits 22 to 37 are constructed by dividing one period of the controlled input signal SIG whose phase is to be controlled into n=16 equal parts.
It outputs 16 phase signals. That is, if the period of the controlled input signal SIG is Ts, each delay circuit 22 to
The delay time of 37 is Ts/16 (=Ts/n). Therefore, the delay circuits 22 to 37 are connected to the controlled input signal S
It functions as a delay line that stores and delays IG over one cycle. Each output P15 to P0 of the delay circuits 22 to 37 is Ts
/16 times, and these outputs P1. ~P0 is the selected signal terminal S1.
~Input to S0. This selector 38 is an analog selector, and for example, AD7506 (16 channel analog multiplexer), which is an IC manufactured by Analog Devices, is used. Here, A 6 H of selector 38
A @ gA,, A, per terminal, Ao is LSB (
MSB (most significant bit), A,
Then, the binary input value i indicated by A,, A,, A,, A is S of the selected signal terminals S I B to S0.
Select i and output to OUT. This binary input value l
indicates the phase number of the controlled input signal SIG.

Up/down counter 3 for controlling selector 38
Similarly to the previous embodiment, reference numeral 9 uses a synchronous 4-bit up-down counter such as 5N74LS192, which is an IC manufactured by Texas Instruments. Each time a rising pulse is input to the up-count terminal or down-count terminal of the up-down counter 39, a count-up or count-down operation is performed, respectively. Since the count value i held by this up/down counter 39 corresponds to the phase number l of the controlled input signal SIG mentioned above, the output OUT of the selector 38 is T s / every time this counter 39 counts up or counts down. A signal whose phase is advanced or delayed by 16 times is output. Here, ADVANCE or RERARD causes the up/down counter 39 to operate up or down.

By the way, as the delay circuits 22 to 37 in this embodiment, typical propagation delays such as coaxial cables and strip lines may be used, and in the low frequency range, LC circuits having equal polarization may be used. So-called delay lines may also be used. Furthermore, a delay circuit using surface acoustic waves may be used like a SAW filter. Furthermore, analog delay circuits such as COD can also be used; in this case, COD
The transfer lock speed allows you to precisely control the delay time. In this method, the transfer lock speed is set to 08C21
By multiplying by n, it is possible to easily create n phases. In addition,
A well-known method for generating a locked frequency by multiplying the output signal of O20 by n is to distort the signal and generate its harmonics using a resonant circuit. Also, P
A frequency synthesis method using LL is also well known.

In any case, according to this embodiment, by configuring the delay circuits 202 to 37 and the selector 38 in an analog manner, an analog signal can be used as the controlled input signal SIG, and it is possible to use not only a rectangular wave or a sine wave but also a periodic signal. The phase of a signal with any waveform can be freely controlled as long as it is suitable.

Effects of the Invention As described above, the present invention is configured to select a signal of a corresponding phase from a delay circuit for one period of a controlled input signal using a selector and an n modulo up/down counter, so that frequency stability can be achieved. It is possible to completely match the frequency stability of the source oscillator, and it is also possible to easily lock to any phase without changing the frequency, and by configuring the delay circuit and selector in analog, the controlled input signal By using an analog signal as a signal, it is possible to freely control the phase of not only rectangular waves but also other periodic arbitrary waveform signals, and if the target is a rectangular wave etc., the claim Like the invention described in 2 or 3, (n
-1) It can be realized with a simple configuration using a stage or zero stage shift register as a delay circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention, and FIG.
The figure is a block diagram showing a modification, and FIG. 3 is a block diagram showing a second embodiment of the invention.

Claims (1)

[Claims] 1. A delay circuit that receives a periodic controlled input signal and outputs a signal of n phases every 1/n (n is an integer) of the period of the controlled input signal, modulo n 1. A phase control circuit comprising: an up/down counter; and a selector using an output signal of the up/down counter as a selection control signal and an n-phase output signal from the delay circuit as a selection signal. 2. An (n-1) stage shift register to which a periodic controlled input signal is input and which is shifted by a clock having a period of 1/n (n is an integer) of the period of the controlled input signal, modulo n and a selector that uses an output signal of the up-down counter as a selection control signal and an input signal to the shift register and an output signal of each stage of the shift register as selected signals. phase control circuit. 3. An n-stage shift register into which a periodic controlled input signal is input and which is shifted with a clock having a period of 1/n (n is an integer) of the period of the controlled input signal, and an up/down counter modulo n. and a selector which uses the output signal of the up-down counter as a selection control signal and the output signal of each stage of the shift register as a selection signal.