JPH03270492A - Load/function dividing type exchange control system - Google Patents

Abstract

PURPOSE:To easily present additional service by dividing the function of a main processor to present exchange processing service. CONSTITUTION:For first processor groups (local processor groups) 90-97 and second processor groups (main processor groups) 160-165, the loads or functions of plural terminal interfaces such as line/trunk circuits or the like to be housed in time division switches (TSW0-TSW7) 70-77 are divided to the prescribed amount In respect to the second processor groups 160-165, the loads or the functions are further divided into N groups (N: arbitrary natural number) composed of plural processors and the functions are shared so as to execute the specified exchange service for each processor in the N groups. Thus, the function of the main processor to execute the exchange processing service is divided and the additional service can be easily presented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to switching control systems (fP, #), particularly to load and function distributed switching control systems.

[Conventional technology]

An example of a conventional distributed switching control system is shown in FIG. 7 and will be described.

In the figure, 61o and 61n are subscriber telephones (SUB)
, 62o, 62n are line circuits (LC), 63o, 63
n is the central office trunk (COT), 64o and 64n are the originating register trunks (ORT), and 65 is the relay stand (AT).
TCON), 66 is relay console controller (PO3C)
, 67o, 67n are time division switches (T S Wo
p T S W n ), 68o, 68n are speech path control units (SPC), and 69o, 69n are call processors (
CPRO, cpan), 70o, 70n are processor path interfaces (FBI), T1 is a path control unit (B2O), and 72 is a common processor path (PBUs).
), 73 is a data memory interface (DMI),
74 is a common memory (MEM).

Conventionally, in this type of control system, as shown in FIG. 7, a constant line (LC)/) rank (COT)
A call processor (CPRa, CP
Rn) 69o, 69n are distributed on a common processor path (PBUS) 72 for multiple units via processor path interfaces (PBI) 70o, 70n, and a common memory (MEM) 74 for storing system data/office data. Exchange processing services were provided by sharing them via a data memory interface (DMI) 73.

[Problem to be solved by the invention]

In the conventional distributed exchange control method described above, in order to add special service functions, data exchange functions, 15DN functions, and other functions, it is required to incorporate software into individual software programs, so it is difficult to develop the software. There is a problem in that not only does the evaluation require a large amount of man-hours, but it also reduces the processing capacity of the exchange service.

[Means to solve the problem]

The load/function distributed switching system of the present invention requires multiple terminal interface circuits such as line/trunk circuits accommodated in a time division switch, based on the control system of an electronic exchange that adopts a distributed control system. A first group of processors that distributes the load or functions in quantity and controls it; a second group of processors that performs exchange processing services based on various activation requests from the load-balanced processors; Commonly read to this second processor group,
The first and second processor groups are connected to a common processor path through a processor path interface means included in each processor, and the first and second processor groups are connected to a common processor path by a path control unit. It has a means that can transfer information between arbitrary processors in response to a request from a processor group, and for the second processor group, there is a means for transferring information between arbitrary processors. ), and the functions are divided so that each of the N groups of processors executes a specific exchange processing service, and when the exchange processing service is activated for the first processor from the subscriber cabinet or trunk circuit. , arbitrarily select one of the N groups of processors as the first processor according to its content;
It has a means of transmitting information and is designed to perform exchange processing services.

[Effect]

In the present invention, the functions of the main processor that provides exchange processing services are divided.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing an embodiment of the load/function distributed switching control system according to the present invention.

In the diagram, 1G, 1? is subscriber telephone CSUB), 2
0, 27 are line circuits (LC), 3o, 37 are central office line trunks (COT), 47 are outgoing register trunks (ORT), 5 are relay consoles (ATTCON), 6 are relay console controllers (PO8C), 7o, γn is a time division switch (TSWO, TSW?), go, 11yFi channel control unit (spC), 9o, 9te are local processors (LP, , LP, ), 100, 107 are local processor units (LPU), 11a , 1
17 is the processor path interface (FBI)
, 12 is a path control unit (BSC), 13 is a common processor path (PBUS), 14o 14s, 14
4, 14s is the main processor (MP66, MP
O-3, MPI-0, MPI-815o...153
, 154, 15s is the processor path interface (FBI), 16o = 16s, 164.

165 is the main processor unit) (MPU), 1
7o-173, 174, 175 are data memory ink-7 ace (DMI), 18 is data memory path (DM
BU8), 19 is a data memory (DM), 20 is a data memory interface (DMI), 21 is a common memory (MEM'), and 22 is a highway switch (H8W).

Then, line circuit (LC) 2°, 27, office line trunk (COT) 3°, 37, outgoing register trunk (OR
T) 40.47, the relay console (ATTCON) 5 and the relay console controller (posC) 6 are distributed with a certain amount of load, and the time division switches (T 8 Wo, T SW 7
) 7o, 77, and its control is carried out via the communication path control unit (SPc) go, 87. Call detection and response 1 call reception from the local processors So to 97 and the local processor group (LPO-LP?) Two main processor groups (MPo-o #MP) provide exchange processing services based on exchange processing requests such as detection.
o-a, upl-o; $ and MP 1-1) 14o
The main processor is divided into two groups in terms of processing functions: a general-purpose group and an additional service group.

For multiple main processors, a common memory (, MEM) 21 is connected.

t*, each 11” processor is connected to a common processor path (PBUS) 13 via a processor path interface (PBI) 15o to 154, and a path controller (
BSC) 12 enables information transfer between processors. Time division switch (TSWo = T
SW7) 70 to 77 have a three-stage configuration of T-S-T.

In this way, the present invention provides a time division switch (TS%~T8
W? ) A first processor group (local processor group) that distributes the loads or functions of a plurality of terminal interface circuits such as line/trunk circuits accommodated in the terminals 70 to 77 to a predetermined number and controls them; a second processor group (main processor group) that performs exchange processing services based on various activation requests from the processors; and a common memory 21 that can be shared and written to the second processor group. The first and second processor groups are connected to a common processor path (PBUS) 13 through a processor path interface means included in each processor, and the path control unit CB2O) 12 connects the The second processor has means capable of transferring information between arbitrary processors in response to requests from the first processor and the second
The processor group is further divided into N groups (N: any natural number) consisting of a plurality of processors, and the functions are divided so that each processor in the N groups executes a specific exchange processing service. When the switching processing service is activated from the subscriber or the trunk circuit to the first processor, the first processor (depending on the content) arbitrarily selects one of the above N groups of processors and transmits information. and is configured to perform exchange processing services.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIGS. 2 to 5, which are diagrams for explaining the operation of FIG. 1. In FIGS. 2 to 5, the same reference numerals as in FIG. 1 indicate corresponding parts.

The exchange processing operation will now be described with reference to FIG. 2, taking a local connection call as an example.

Figure 2 (at, local processor (LPo)
9o subscriber phone A (5UBA) 10 goes off hook, local processor unit (LPU) Io
o detects a call via the communication path control unit (SPC) 8o, and issues a dial tone connection processing request to the main processor (MP) based on the call detection. Then, based on this request, the main processor (MP) performs the processing based on FIG. , select an empty register, and select the time division switch (TSWo) T.

By controlling the (primary switch, secondary switch, tertiary switch), the line circuit (LC) 2° of subscriber telephone A (SUB A) 1o and the originating register trunk (OR
T) By connecting 4o, subscriber telephone A (8U
B A) Give 1o a dial tone.

Similarly, when subscriber telephone A (SUB k) 1° dials the extension number (xxxx) in the state shown in Fig. 2 <b>, the local processor (LPo) 9° changes to the main processor (MP). The main processor (MP) configures the calling state as shown in FIG. 2(C), and then calls the called party telephone B (
When SUB B) 1r responds to the paging signal f (RG), it performs extension interconnection processing as shown in FIG.

Next, inter-processor transfer for the above processing will be explained using FIGS. 3, 4, and 5.

As shown in FIG. 3, when each processor makes an inter-processor information transfer request, a request signal (RQT) 23 is transmitted from the processor path interface (PBI) 11o, 11+-117 to the path control unit (BSC) 12. . Then, in this path control unit (BSC) 12, an arbiter (ARBT:) 24 sequentially receives path activation requests, returns an authorization signal (ACK) 25 as a request enable signal 5, and as a result, the right to use the path is granted to the requesting party. is configured to give the processor

As mentioned above, the local processor (LPG) So
When there is a call request from the p-cal processor unit (LPU) 10od, an activation request is made to the processor path interface (FBI) 11o.

Then, as shown in FIG.
The number of the called processor is stored in the register A (REG A) 27 in the memory, and the information to be sent is stored in the sending memory
Y) 28, and set the condition of group selection or individual selection as the activation condition to register B (REG B) 29.

Here, group selection and single selection will be explained.

In the system configuration shown in this example, the local processor! FP (LPo = LP?) The system is such that a vacant main processor (MP) sequentially processes various randomly generated requests from 90 to 9y.
Local processor group (LPO-LP7) 90-9-
cannot determine which main processors (MPs) are free, and as a result, a group selection function is required to select a group of free main processors (MPs) from among a group of main processors (MPs).

In the case of the present invention, the main processor (MP) is a general-purpose main processor group (MP QQ -Mp(, -
3) 14o to 143 and main processor group for additional services (MPl-r), MPI-1) 144t
At this time, the local processor is divided into 14s (divided into 14s), and at this time, the local processor is
000). When the above conditions are set, a path activation request flip-flop (RQ) is sent as a path transfer request signal.
Set T F/F)30.

Processor path interface (FBI) 11
.

In the transmission circuit (SND CKT) 2G, the path control section (B
SC) 12 sends a request signal (RQT) and a permission signal (
Wait for the return of ACK. Then, this permission signal (AC
K) reception control circuit (SND CTL) 31
WJ often executes a series of sending sequences, but WJ
As shown in figure s, first, as a sequence of search mode clock 1, the mode signal (2 bits MD 0 and 1) is set to the search mode of rOJ and rlj, and Do=D7.
Adds pits and their parity signals and sends the called processor number on the data path.

10,000, processor path interface (FBI) of main processor 〇 (JiPo) in Fig. 4, reception circuit (RCV CKT) of 15゜, reception control circuit (RCV of 32)
-CTL)sa performs a series of reception sequences, but in the main processor (MpH), when the search mode clock is 1, the incoming call is detected because the number of its own processor matches the number of the called processor that has been sent. I do.

Then, the main processor (MPo) determines whether it is idle or busy based on whether or not it is executing another job (Job) using the equipment busy flip-flop (BSYF/F) 34, and sets the search mode clock 2. The condition is sent back to the calling processor. The transmission control circuit (:SND CTL) 35 of the calling processor receives this signal,
If the main processor (MPl) is empty, transmission is possible and the mode is set to data mode (10), and the sending memory (SN
D MRY) Read information from 28 1-2 Receiving side b.'J
The information is transferred to the reception memory (RCVMRY) 36 of the processor path interface (FBI). However, when the main processor 〇 (MPo) is busy, the transmission control circuit t'-8ND C of the calling side boother
TL) 31 is the main processor (MP)! 1,000, it is determined that transmission is not possible, and the mode is reset to search mode/clock 1, and the main processor number is +1 at the same time.
(00110001) specifies the main processor 1 (MP+) and repeats the path transfer sequence tn again. That is, from the local processor (LP), a group of main processors (MP) such as empty processors are selected by group selection, and an activation jIb request is made.

When the transmission is completed, the transmission control circuit (SND C
TL) 35, the transmission is an end flip-flop (S-END
F/F) 37 is set, and as a result, an interrupt signal is sent to local processor unit 0 (LPU>10o) to notify the end of the transfer.

In the case, reception control circuit CRCV cTL) 33, reception end flip-flop c R-END F, /F) 3g
is set, and an interrupt signal is sent to the main processor (MP) to notify the end of reception.

Among them, as shown in Figure 4, 3g is the path activation permission flip 7.
0 (ACK F/F), 40 is a receiving circuit.

Also, in Figure 5), B11po-,: oooltoooo.

MPO-3: 00110011 MP1-o: ottiooo.

MPl-1: 0111001 As explained above, the exchange processing service is performed, but the basic connection is put on hold in the case of PBX K>.

In addition to basic services such as forwarding and three-way calls, various additional services are being added and will continue to increase in the future. However, adding all services uniformly increases the complexity of the software and the development process.
Increasing numbers! Cigarettes cause a decrease in processing power.

The present invention provides that normal service is performed by the main processor (MP).
o-0-MP O-3) 14o-I As is processed, and when various additional services as shown below are requested, the main processor'-MP 1-o 9MP
1-1) 14<.

145 for processing.

In addition, the load//' function distributed switching control method of the present invention is as follows:
Needless to say, this can be done by dividing the functions into a voice service and a data connection service for the standard service center, rather than corresponding to the additional service.

Additional service 1: Figure 6 (PI) f: As shown, central line relay board (ATT C0N) attached to the hotel system
Waiting display information collection button and display control that displays guest information on the central office line relay stand when connecting an incoming central office line call to 43 with an extension! ! ! Function 'f' is assigned to the main service processor (, MP,) of the additional service group.

Additional service 2: PBX as shown in Figure 86 (b+)
When a fire breaks out in the office where the system is installed, the main processor (MP) of the supplementary service group is assigned a series of functions for simultaneously calling a certain group of subscribers by remote access from subscribers.

In Fig. 6 (aJ, (b), which is a diagram used to explain this additional service, the same reference numerals as in Fig. 1 indicate phase parts, 41 is a time division switch (TSW), 4
2 is a central office trunk (COT), 44 is a relay stand controller (posC), 45 is a subscriber telephone (SUB), 46 is a line circuit, 4T is a time division switch (TSW>), 48 is a subscriber telephone (sUB), 49 is a line circuit (LC), S
O/fi Announcement Drunk (^NT), 51-
1~51-Fl! ri subscriber telephone, 52-1=52-
n is a line circuit (LC).

〔Effect of the invention〕

As explained above, the present invention achieves
This has the effect of making it easier to provide additional services.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the load/function distributed exchange control system according to the present invention, FIGS. 2, 3, 1X4, and 5 are operation explanatory diagrams of FIG. 1, and FIG. 7 is a diagram for explaining additional services, and FIG. 7 is a block diagram showing an example of a conventional distributed switching control system. 1 o~171111 @ 11 subscriber phone (SUB
), 2o~27... line circuit (LC), 30
~37...Central line trunk (COT), 40~47
...Outgoing register trunk (ORT), 5...
・Relay stand (ATTCON), 6... Attendant controller (posC), Tor;i... Time division switch (TSW), @o~fJ7* 11 @ @Communication path control unit (spC ), 9° to 97... Local processor (LP), 10o to 107... Local processor unit (LPU), 11o to 117... Processor bus interface (PBI), 12...
...Path control unit (BSC), 14o to 14s...
・Main processor path interface (FBI)
, 16o~16s...Main processor unit (MPU), 17o~175...Data memory interface (DMI), 19...Data yt
Sled (DM), 20...Data memory interface (DMI), 21...Common memory (MEM)
22...Highway switch f- (HSW).

Claims (1)

[Claims] In a control system for an electronic exchange that adopts a distributed control system, a first system that distributes the load or functions of multiple terminal interface circuits such as line/trunk circuits accommodated in a time division switch into a predetermined number and controls them. a group of processors, a second group of processors that perform exchange processing services based on various activation requests from the load-balanced processors, and a common memory that can be commonly read and written to the second group of processors. The first and second processor groups are connected to a common processor path through a processor path interface means included in each processor, and the path control section handles requests from the first and second processor groups. The second processor group is further divided into N groups (N: any natural number) each consisting of a plurality of processors. , the functions are divided so that each of the N groups of processors executes a specific exchange processing service, and when the exchange processing service is activated for the first processor from the subscriber or the trunk circuit, the first processor A load/function distributed exchange control system, characterized in that it has a means for arbitrarily selecting one of the N groups of processors and transmitting information, and performs an exchange processing service.