JPH03270224A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable the multilayer wiring in high selectivity and low contact resistance further subjected to no junction breakdown to be formed by a method wherein the cleaning process of a substrate or a wiring layer using halogenated metallic gas is included in the title manufacture. CONSTITUTION:The cleaning process of a substrate or a wiring layer using halogenated metallic gas is included in the title manufacture. Besides, after finishing this cleaning process, a metallic film may be deposited on the substrate or a wiring layer continuously using the halogenated metallic gas. Through these procedures, without especially performing the cleaning process using gases such as CF4, CCl4, SF6, BCl3, etc., the substrate and the wiring layer can be cleaning-processed so that multilayer wiring subjected to no junction breakdown may be formed thereby enabling the yield of semiconductor device to be augmented.

Description

[Detailed Description of the Invention] [Summary] A method for manufacturing a semiconductor device, which can improve the yield of semiconductor devices by forming a multilayer interconnection that has high selectivity, low contact resistance, and does not cause junction breakdown. The purpose of the present invention is to provide a method for manufacturing a highly reliable semiconductor device in which disconnection of wiring layers due to voids etc. does not occur, and the method for manufacturing a semiconductor device includes a step of cleaning the substrate or the wiring layer by dry etching. The method is configured to include a step of cleaning the substrate or the wiring layer with a metal halide gas.

As a result, the processing dimensions of contact holes are becoming smaller and finer, and cleaning processing using wet etching, which causes side etching, can no longer be used, and cleaning processing using dry etching is now being used instead. ing.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which cleaning processing by etching of a substrate inside a contact hole or a wiring layer inside a contact hole can be performed satisfactorily.

Generally, in multilayer wiring technology in the manufacturing process of semiconductor devices, before forming a metal layer such as tungsten on the substrate inside the contact hole or the wiring layer inside the contact hole by CVD (chemical vapor deposition), The inside of the contact hole is cleaned by wet etching. However, in recent years, due to the miniaturization of semiconductor elements [conventional technology], conventional methods for manufacturing this type of semiconductor device include, for example,
After forming a first insulating film by depositing SiO2 on the Si-based substrate and selectively etching the first insulating film by, for example, RIE method to form a first contact hole, for example, ion implantation is performed. Using the first insulating film as a mask, impurities are introduced into the substrate within the first contact hole by a method to form a substrate diffusion layer. At this time, a thin SiO2 film (natural oxide film) is generated on the substrate in the first contact hole, or impurities from the substrate are precipitated, and a high resistance layer is formed. Since the presence of this high resistance layer increases the contact resistance, a dry etching cleaning process is performed to remove the high resistance layer generated on the substrate within the first contact hole in order to reduce the contact resistance.

For this reason, the substrate in the first contact hole is cleaned using a gas such as CF4, CCl4, SF5, BCl3, etc.

Next, /l is deposited by, for example, sputtering to make contact with the substrate diffusion layer in the first contact hole to form a first wiring layer, and then, by, for example, CVD, /l is deposited on the first wiring layer by CVD. A second insulating film is formed by depositing SiO2. Next, the second insulating film is selectively etched using, for example, RIE to form a second contact hole.

Here, similarly to the above, a thin Af,03 film (natural oxide film) is formed on the first wiring layer in the second contact hole, or a high resistance layer is formed due to the precipitation of impurities. The presence of this high-resistance layer increases the contact resistance, so cleaning is performed to remove the high-resistance layer that has formed on the first wiring in the second contact hole in order to reduce the contact resistance. Processing.For this reason,
CF4, CC1! , 4. The first wiring layer in the second contact hole is cleaned using a gas such as SF6 or BCll. Further, as another cleaning process, sputter etching using Ar ions was performed instead of the above-mentioned gas.

[Problem to be solved by the invention]

However, in such a conventional method for manufacturing a semiconductor device, the cleaning process of the substrate in the first contact hole performed before forming the first wiring layer is performed using CF4,
Since dry etching was performed using gases such as CCL, SF, BCl3, etc., the following problems occurred.

(1) CF, , CCjl! , ,SF, ,BCl,
Since these gases contain impurities such as C, S, and B, impurities are formed on the SiO□ film during etching. For this reason, for example, when a metal such as tungsten is selectively grown in the first contact hole, although it is originally desired to form tungsten only on the substrate, Si
Sin and tungsten were also formed on the film using the impurities formed on the O□ as nuclei, resulting in poor growth performance.

(2) Particularly in the case of a shallow substrate diffusion layer, impurities were diffused into the diffusion layer, causing junction breakdown.

(3) Even if the natural oxide film could be cleaned, the above-mentioned impurities were deposited on the substrate, increasing the contact resistance.

Further, the cleaning process of the first wiring layer in the second contact hole performed before forming the second wiring layer is performed using CF, , CCL , SF, , BCff as described above.
Since dry etching was carried out using a gas such as i, etc., problems similar to those in (1) and (3) described above occurred, as well as the following problems.

(4) Even if the natural oxide film can be cleaned, the above-mentioned impurities will accumulate on the substrate, reducing electromigration and stress migration, and voids and hillocks will occur in the first interconnect layer. There is a problem in that the wiring layer becomes easily disconnected.

On the other hand, when cleaning the first wiring layer by sputter etching using Ar ion irradiation, the Ar ions implanted during etching or knock-on impurities reduce electromigration and stress migration, and the first
There is a problem in that voids and hillocks occur in the first wiring layer, making the first wiring layer more likely to be disconnected.

Therefore, the present invention makes it possible to improve the yield of semiconductor devices by forming multilayer interconnections that have high selectivity, low contact resistance, and do not cause junction breakdown. The purpose of the present invention is to provide a method for manufacturing a semiconductor device with high performance.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device which includes a step of cleaning a substrate or a wiring layer by dry etching, which includes a step of cleaning a previous substrate or a wiring layer with a metal halide gas. After the cleaning process is completed, a metal film may be continuously deposited on the substrate and the wiring layer using a metal halide gas, and the substrate or the wiring layer may be halogenated. a step of cleaning the substrate or the wiring layer with a mixed gas of a metal halide gas and an inert gas; a step of cleaning the substrate or the wiring layer with a mixed gas of a metal halide gas and N2; It may be constructed by including a step of performing a cleaning treatment with a mixed gas of metal halide gas and N2.

[Effect]

In the present invention, the substrate or wiring layer is cleaned using a metal halide gas.

Therefore, only the high resistance layer is removed when cleaning the substrate and wiring layer. For example, when etching is performed using a metal halide gas such as WF, the gas is separated into an etching (cleaning) region and a metal deposition region at a predetermined temperature, RF power, and predetermined gas pressure. For example, as shown in FIG. 4(a), l a+T
At a gas pressure of
The higher the power, the more metal is deposited. That is, W
In the case of F, the W-F bond is not broken in the etching region and no W deposition (selective growth) occurs.
Etching is performed under conditions of temperature and RF power gas pressure corresponding to an etching region in which this W--F bond is not broken. At this time, cleaning processing is performed using F ions and radicals. Selective growth of W is then performed under conditions of temperature, RF power, and gas pressure where the WF and gas correspond to the metal deposition region. On the other hand, as the pressure of WF and gas is increased, the etching area becomes narrower and the fourth
As shown in figure (b), the WF gas pressure is 50 mTor.
The area r is entirely a deposition area. That is, during the cleaning process, the gas pressure is set to 50 mTorr or less.

Therefore, unlike conventional methods, CF, CCl2. , SF, ,
Not only can the substrate and wiring layer be cleaned without cleaning using a gas such as BCf, but also metal can be continuously deposited. As a result, multilayer wiring with high selectivity, low contact resistance, and no junction breakdown is formed, which improves the yield of semiconductor devices.It also prevents disconnection of wiring layers due to voids and the like, making semiconductor devices reliable. Improves sex.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

1 to 4 are diagrams showing an embodiment of the semiconductor device manufacturing method according to the present invention, and FIG. 1 shows a semiconductor device manufacturing apparatus to which the semiconductor device manufacturing method of the present invention is applied. 2 shows a state in which a natural oxide film is formed on the substrate in the first contact hole, and FIG. 3 shows a state in which a natural oxide film is formed on A1 in the second contact hole. FIG. 4 is a diagram showing the relationship between RF power, etching (cleaning) rate, and W deposition rate when the gas pressure is 1 mTorr and 50 mTorr.

First, the configuration will be explained. In the construction drawing, ■ is a vacuum container, and the container 1 includes a nozzle 2, 31, a substrate 3, an electrode 4.
5. An inert gas introduction hole 6 is provided. The nozzle 2 introduces a predetermined metal halide gas into the container 1, and the introduced gas passes through an exhaust hole 7 formed in the container 1.
．． It is discharged from 8. An RF (high frequency) power source 9 is connected to the electrode 4.
When a high frequency voltage of a predetermined frequency is supplied from the electrode 4.5 and RF power is applied to the electrode 4.5, the metal halide gas is turned into plasma between the nozzle 2 and the SiM plate 3.

As shown in FIG. 2, this Si substrate 3 has a first insulating film 11 in which a first contact hole 0 is formed on the substrate 3. A natural oxide film 12 is formed on the surface. This Si substrate 3 is formed by depositing SiO□ on the substrate 3 by, for example, a CVD method to form a first insulating film 11, and then selectively etching the first insulating film H by, for example, an RIE method to form a first contact. After forming the hole 10, impurities are introduced into the substrate 3 within the first insulating film 11 by, for example, ion implantation to form the substrate diffusion layer 13. At this time, several tens to hundreds of SiO□ (natural oxide films) 12 may be formed on the substrate 3 in the first contact hole 10, or, for example, impurities may be precipitated from the substrate 3 and a high resistance layer may be formed. It is formed. Note that 14 in FIG. 1 is an ultraviolet lamp for heating the substrate 3.

Etching (cleaning treatment) was performed in the vacuum container 1 having such a configuration under the following conditions.

Metal halide gas: W F b (2cc),
Gas pressure crab l mTorr % Substrate heating temperature: 180°C 1 RF power = 80 W, RF power application time: 2 minutes The reason why the cleaning process is performed under the above conditions is as follows.

That is, at this time, WF, is plasma-treated and decomposed into WF, , +F. Then, as shown in Figure 3, RF
Since the W--F bond is not completely broken when the power is 100 W or less, the natural oxide film 12 is etched by F ions and radicals. Therefore, since impurities are not generated as in the conventional case, the interval I(1)
~(3) never occurs.

Next, at the same time as the RF power is turned off, the temperature of the Si substrate 3 is raised to 330° C. using the ultraviolet lamp 14, and W is selectively grown on the SiM plate 3 in the first contact hole 10.

WF6 is increased to 5 cc, and preferably H2 (500 cc), Si
By introducing H4 (5 cc), selective growth of W can be performed favorably.

During this selective growth, the W--F bond becomes completely broken in the metal deposition region, and the etching region becomes narrow. At this time, W may be deposited by increasing the RF power to 100 W or more, as shown in FIG. 3, without turning off the RF lightning voltage and raising the temperature of the Si substrate 3.

FIG. 3 shows a first wiring layer 1 formed by depositing AN on a Si substrate 3.
Although not shown in detail, the Si substrate 3 shown in FIG. 1 is present under the first wiring 115. That is, for example, the first
11 is deposited by digging a contact with the substrate diffusion layer 13 in the contact hole 10 to form, for example, a first wiring layer 15 as shown in FIG. After depositing Sin on the layer 15 to form the second insulating film 16, the second insulating film 1116 is etched by, for example, RIE to form the second contact hole 1.
form 7. At this time, the second contact hole 17
A high-resistance layer 18 of A formation t03 having a film thickness of about several tens to 100 layers is generated on the first wiring layer 15 in the first wiring layer 15.

Next, in the container 1 shown in FIG. 1, a cleaning process is performed to remove the high resistance layer 18 on the first wiring unit in the second contact hole 17 under the following conditions.

Metal halide gas: WFi (2cc), gas pressure 1 mTorr.

Substrate heating temperature: 180°C or less, RF power = 80 W, RF power application time = 2 minutes At this time, the aluminum on the first wiring layer 15 is different from the above-mentioned naturally oxidized WA13, in that it contains F ions and radicals. If only the etching speed is increased, the etching speed will be slow, so in order to speed up the etching speed, an inert gas such as Ar may be introduced from the inert gas introduction hole 6. At this time, the partial pressure of Ar may be lower than the total pressure. and introduce into the container 1 so that the amount becomes 20%.

Therefore, the high resistance layer 18 is removed by plasma-treated F ions, radicals, and Ar.

Next, at the same time as the RF power is turned off, the temperature of the Si substrate 3 is raised to 330° C. using the ultraviolet lamp 14, and W is selectively grown on the first wiring 115 of the second contact hole 17.

During this selective growth, the W--F bond is completely broken and a metal deposition region is formed, resulting in a narrow etching rate. Incidentally, at this time, instead of turning off the RF lightning voltage and raising the temperature of the Si substrate 3, W may be deposited by increasing the RF lightning voltage to 100 W or more as shown in FIG. In addition, etching can be promoted by introducing Hz (50cc) instead of Ar and utilizing a reduction reaction.
Alternatively, the etching rate may be increased by introducing Nz (10 cc) and mixing it with WF for plasma treatment, and introducing a reactive gas called N F s to remove excess F.

When introducing these N2 and N2 from the introduction hole 6, the total gas pressure should not exceed 10 s+Torr.

Regarding the metal deposition following the above-mentioned cleaning process, not only W but also other selective growth such as Ai may be used, or metal sputtering may be used.

Further, the gas used for cleaning the Si-based vi3 and the first wiring layer 15 is the above-mentioned WF.

M o CIt s , M
Metal halide gases such as oFb may also be used.When these gases are subjected to plasma treatment, they cause the following reaction.

M o Cj! 5 →Mo CIla + CI
MoFh-+MoC, +F Therefore, cleaning treatment is performed with F radicals or ions and Cl radicals or ions, respectively, and Mo is deposited in the subsequent selective growth of metal.

As described above, in this embodiment, since the Si substrate 3 or the first wiring layer 15 is cleaned with a metal halide gas, the multilayer wiring has high selectivity, low contact resistance, and does not cause bond breakdown. It is possible to form a semiconductor device, improve the yield of the semiconductor device, and provide a highly reliable method for manufacturing a semiconductor device that does not cause disconnection of the wiring layer due to voids or the like.

〔Effect of the invention〕

According to the present invention, since the substrate or the wiring layer is cleaned with a metal halide gas, it is possible to form a multilayer wiring that has high selective growth properties, low contact resistance, and does not cause junction breakdown. It is possible to improve the yield of the device, and
It is possible to provide a method for manufacturing a highly reliable semiconductor device that does not cause disconnection of wiring layers due to voids or the like.

3...Si substrate (substrate), 15...First wiring layer (wiring layer).

[Brief explanation of drawings]

1 to 4 are diagrams showing an embodiment of the semiconductor device manufacturing method according to the present invention, and FIG. 1 shows a semiconductor device manufacturing apparatus to which the semiconductor device manufacturing method of the present invention is applied. 2 shows a state in which a natural oxide film is formed on the substrate in the first contact hole, and FIG. 3 shows a state in which a natural oxide film is formed on A2 in the second contact hole. Figure 4 shows R when the gas pressure is 1) Torr and 50 mTorr.
FIG. 3 is a diagram illustrating the relationship between F power, etching (cleaning) rate, and W deposition rate. Fig. 2 shows a state in which a natural oxide film is formed on the substrate of one embodiment. Fig. 3 shows a state in which a natural oxide film is formed on An in the first embodiment.

Claims (5)

[Claims] (1) A method for manufacturing a semiconductor device comprising a step of cleaning a substrate or wiring layer by dry etching, the method comprising the step of cleaning the substrate or wiring layer with a metal halide gas. Method. (2) After the cleaning process is completed, a metal film is continuously deposited on the substrate and the wiring layer using a metal halide gas. . 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of: (3) cleaning the substrate or the wiring layer with a mixed gas of a metal halide gas and an inert gas. (4) The substrate or wiring layer is heated with a metal halide gas and H
3. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of performing a cleaning treatment using a mixed gas with _2. (5) The substrate or wiring layer is coated with a metal halide gas and N.
3. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of performing a cleaning treatment using a mixed gas with _2.