JPH03269624A - Sequencer control system - Google Patents

Abstract

PURPOSE:To easily control the timing by attaining a constitution where a specific instruction processing part works based on a signal having a fixed frequency ratio to a specific instruction clock signal set externally or internally or to the corresponding signal. CONSTITUTION:A bus control part 113 serving as an instruction generating part selects one of those requests received from the input/output devices 111 and 112 and a memory 110 and outputs a microinstruction necessary for execution of the selected request to hold the microinstruction in an instruction register 114. Then the microinstruction is decoded by an instruction decoder 12 according to a fact whether the microinstruction is equal to a normal or specific instruction. When a normal instruction is confirmed, a normal instruction processing part 13 processes the instruction in the timing obtained from a basic clock via a timing control part 14. On the the other hand, when a specific instruction is confirmed, a specific instruction processing part 15 processes the instruction in the timing of the frequency generated by a set frequency generator 151. Thus it is possible to secure the absolute time with no change of a control program even to the change of the basic clock.

Description

[Detailed Description of the Invention] (Summary) An instruction generation unit that generates a microprogram, a timing control unit that generates instruction clocks with various timings based on a basic clock, and an instruction generation unit that generates an instruction clock that is decoded based on the instruction clock. Regarding the sequencer control method that accommodates the normal instruction processing unit that processes the instructions, the sequencer control method can be changed easily and inexpensively without changing the program as the processing capacity of an external device improves. The purpose of the present invention is to provide a sequencer control system, comprising: an instruction decoding section that decodes an instruction depending on whether the instruction generated from the instruction generation section is a normal instruction or a specific instruction; This configuration accommodates a specific instruction processing section that performs processing with timing determined by a specific instruction clock signal generated from a signal source separate from the specific instruction processing section.

[Industrial application field]

The present invention relates to a sequencer control system that operates using a microprogram, and particularly relates to an instruction generation section that generates a microprogram, a timing control section that generates instruction clocks at various timings based on a basic clock, and a sequencer control system that operates on a microprogram. The present invention relates to a sequencer control method having a normal instruction processing unit that processes the instructions decoded based on the sequencer.

The present invention relates to a control system for a sequencer such as a CPU that interfaces with an external device.

(Prior Art) Conventionally, there has been a sequencer control method as shown in FIG.

As shown in the figure, the hydraulic type includes an instruction generation section 41 that generates a microprogram, a timing control section 44 that generates clocks for various timing instructions based on a basic clock, and a timing control section 44 that generates clocks for instructions for various timings based on a basic clock. It has a normal instruction processing section 43 that processes the instructions decoded based on a clock, and an instruction decoding section 42 that decodes the instructions generated from the instruction generation section 41.

As external devices become faster, there is a demand for CPUs to perform timing adjustments on the order of microseconds or nanoseconds.

For this reason, conventionally, when replacing the CPU for an interface connected to an external device by upgrading,
This has been done either by changing the program for the part that adjusts the timing of the timing control section 44, or by adding an external control section that has absolute time regardless of the processing capacity of the CPU.

[Problem to be solved by the invention]

By the way, as explained above, conventionally, as the processing capacity of external devices increases, it is necessary to adjust the timing of processing. In that case, even if a timing control unit with absolute time is used, the minimum unit is several thousand Ls, and timing adjustment on the order of microseconds or nanoseconds must be done by a program. It was necessary to change the program of the portion of the timing control section 44 in which the tie cutting is desired to be adjusted. That is, the problem of timing adjustment having to be made by changing the No Operating (idling) time or the loop command within the program has been solved, which makes it difficult to adjust the timing.

On the other hand, when timing adjustment is performed on each 110 side, there is a problem in that it cannot be done inexpensively.

Therefore, the present invention has been made with the object of providing a sequencer control method that can easily and inexpensively change the sequencer control method without changing the program as the processing capacity of an external device improves. be.

(Means for Solving the Problems) In order to solve the above technical problems, the present invention, as shown in FIG. In a sequencer control system having a timing control section 4 that generates an instruction clock and a normal instruction processing section 3 that processes the decoded instruction based on the instruction clock, the instruction generated from the instruction generation section 1 an instruction decoder 2 that decodes an instruction based on whether it is a normal instruction or a specific instruction; Specific command processing unit 5 that performs processing
It has the following.

[Effect]

The operation of the sequencer control method according to the present invention will be explained.

When the instruction generation unit 1 generates a microinstruction based on a request from an external device or host, the instruction decoding unit 2 decodes the instruction and decodes it depending on whether the instruction is a normal instruction or a specific instruction. conduct.

Here, what is meant by "sequencer J"? In the execution of instructions in electronic computers, instructions are further executed by skillfully connecting several elements made up of certain logic circuits, but these It is a device that controls logic circuit elements to operate step by step and is mainly made of flip-flop circuits, gate circuits, etc.
This also includes U.

Further, the "normal command" is an command that is processed based on the command clock signal from the timing control unit 4, and is a command that has been provided with the timing control unit 4, and the "specific command" is a command that is processed based on the command clock signal from the timing control unit 4. This command operates on a specific command clock signal that is different from the command clock signal outputted from the unit 4, and is different from the normal command.

That is, when the instruction decoding section 2 determines that the instruction is a normal instruction and decoding it, the normal instruction processing section 3 processes the instruction according to the instruction clock output from the timing control section 4.

On the other hand, if the instruction decoding unit 2 determines that the instruction is a specific instruction, the specific instruction processing unit 5 determines the specific instruction clock signal, the frequency of the signal, the frequency division ratio, the frequency doubling ratio, or Processing will be performed at a timing determined by the combination.

〔Example〕

Next, a sequencer control method according to an embodiment of the present invention will be explained based on FIGS. 2 and 3.

Broadly speaking, FIG. 2 consists of a 110 interface 30, input/output devices 111 and 112, and a memory 110.

As shown in the figure, this system includes an instruction generation unit 11 that generates a microprogram, a timing control unit 14 that generates instruction clocks with various timings based on a basic clock, and a timing control unit 14 that generates instruction clocks with various timings based on the basic clock. a normal instruction processing section 13 that processes the instruction decoded based on the instruction, and an instruction decoder as an instruction decoder 2 that decodes the instruction depending on whether the instruction generated from the instruction generation section 11 is a normal instruction or a specific instruction. 12, and a specific instruction processing unit 15 that processes the decoded specific instruction at a timing determined by the frequency ratio of the specific instruction clock signal or the specific instruction clock signal set from the outside. .

Here, the "frequency ratio with respect to a clock signal for a specific instruction set externally" is, for example, a frequency ratio set from an externally set frequency dividing ratio, frequency doubling ratio, or a combination thereof. "Frequency ratio" is 1 of f/n (n is an integer of 2 or more) synchronized with the frequency f of the clock signal for a specific instruction.
/n, and the "multiplying ratio" refers to the ratio of the frequency nf (n is an integer of 2 or more) synchronized with the frequency f.

As shown in the figure, the microinstruction generation unit 11 also has a memory 110 that stores microinstructions, input/output devices 111 and 112 as external devices, and responds to requests from input/output devices and the host. A bus control unit 113 that performs arbitration, an instruction register 114 that holds instructions being executed, and registers 115 and 116 that exchange data with the input/output devices 111 and 112.

Further, the specific instruction processing section 15 includes a set frequency generator 151 for determining timing based on the specific instruction clock signal or a frequency ratio set from the outside.

An example of the frequency generator 151 is shown in FIG.

When using the frequency divider 151a as the frequency generator, as shown in FIG. As shown in FIG. 3(b), an up counter 151bl and a comparator 151bl are used as an n-ary counter to generate a pulse of an n-ary frequency, or as shown in FIG. 3(c), a down counter 151 is used.
cl and the comparator 151c2 may be used to generate pulses of n-adic frequencies.

Note that the bus control section 113, the instruction register 114,
The instruction decoder 12, the normal instruction processing section 13, and the specific instruction processing section 15 constitute a part of the sequencer section 10, and the sequencer section 10 and 110 registers 115 and 116 are connected to the CPU.
The CPU 20 and the timing control section 14 constitute a part of the 110 interface 30.

Next, the operation of the sequencer control method according to this embodiment will be explained.

In advance, the operator selects the set frequency generator 151 of the specific command processing section 15 of the 110 interface 30 shown in FIG.
A frequency division ratio of 1/n is set for the frequency divider 151a. After that, the bus control unit 1 as the instruction generation unit 1
13 selects one of the requests from the input/output device 111, 112 or the memory 110 (host), outputs the microinstruction necessary to execute the request, and outputs the microinstruction necessary for executing the request.
to hold. The microinstruction is decoded by the instruction decoder 12 based on whether the instruction is a normal instruction or a specific instruction.

If the instruction is a normal instruction, the normal instruction processing section 13 performs processing according to the timing obtained from the basic clock by the timing control section 14.

On the other hand, if the microinstruction held by the instruction decoder 12 is a specific instruction,
The specific command processing unit 15 includes the set frequency generator 151
The specific instruction is processed at the timing of the frequency that occurs.

In this way, according to the present embodiment, it is possible to operate based on a specific instruction clock generated from a signal source separate from the basic clock, so that the program of the control unit can be changed even when the basic clock is changed. It is possible to secure absolute time without any hassle.

(Effects of the Invention) As explained above, in the present invention, the specific instruction processing section operates based on a specific instruction clock signal set from the outside or inside or a signal having a certain frequency ratio with the clock signal for the specific instruction. I try to do that.

Therefore, even if it becomes necessary to operate with timing other than the timing controlled by the timing control unit due to improved performance of an external device, the operation can be easily and inexpensively performed without changing the control contents of the timing control unit. This makes it possible to provide a versatile sequencer control system that can adjust timing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment, FIG. 3 is a diagram showing an example of an n-ary counter according to the embodiment, and FIG. 4 is a block diagram of a conventional example. It is. 1.11...Instruction generation section 2 (12)...Instruction decoding section (instruction decoder) 3.13
...Normal instruction processing section 4.14...Timing control section 5.15...Specific instruction processing section 151m (Tb) 51c1 51c2 Section 07 ■ Flash

Claims (1)

[Claims] An instruction generation unit (1) that generates a microprogram;
A sequencer having a timing control unit (4) that generates instruction clocks with various timings based on a basic clock, and a normal instruction processing unit (3) that processes the decoded instructions based on the instruction clock. In the control method, an instruction decoding section (2) decodes the instruction depending on whether the instruction generated from the instruction generation section (1) is a normal instruction or a specific instruction; is a specific instruction processing unit (5) that performs processing at a timing determined by a specific instruction clock signal generated from a separate signal source.
) A sequencer control method characterized by having the following.