JPH03268117A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a voltage which has a nearly specific level with simple constitution and to save the electric power to reduce the power consumption by providing an energizing control means which turns on or off a 1st and a 2nd transistors(TRs) at a specific frequency, and at the same time, supplying a potential from an output terminal which is connected between bleeder resistances. CONSTITUTION:An oscillator 4 turns on the P channel and N channel MOS TRs 2 and 3 at the same time in a period wherein a control signal phi1 has a high level (while a control signal phi2 has a low level), but turns off the P and N channel MOS TRs 2 and 3 at the same time in a period wherein the control signal phi1 has the low level (while the control signal phi2 has the high level). A rise or fall in the reference voltage VREF at an output terminal 1 is within a range of permissible voltage variation width, so the reference voltage VREF which has the nearly specific level can be outputted from the output terminal 1.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor integrated circuit device.

In recent years, as semiconductor integrated circuit devices have become more highly integrated and more compact, the optimum operating voltage for each circuit formed on the device has also been reduced. However, it is difficult to lower the operating voltage of the semiconductor integrated circuit device itself due to problems such as increased operating speed and external interfaces.

Therefore, it is necessary to provide a power supply circuit in the semiconductor integrated circuit device itself to obtain an appropriate voltage.

[Prior Art] In conventional semiconductor integrated circuit devices, in order to obtain the optimum power supply voltage for each circuit, power supplies of various voltage values were supplied externally in the required amount. The power supply required by the circuit has been generated internally.

Figure 5 shows a conventional power supply circuit, showing the power supply ■CC and ground l.
”GND, voltage dividing resistors R], R2 are connected in series, and output terminal 1 is connected between both voltage dividing resistors R1 and R2. A procedure capacitor CI is connected between the voltage dividing resistors R, 1, and R2 to divide the voltage of the power supply VCC, and output a predetermined level reference signal to the output terminal 1 via the smoothing capacitor C1. It is designed to generate a voltage VREF.The reference voltage VREP is VREF-IR2/ (R], +R2) l ・V
Represented by CC.

[Problem to be solved by the invention] However, in the conventional power supply circuit described above, the current I 1 (-VREF /R2) always flows from the power supply CC to the ground GND via the voltage dividing resistors R1 and R2, so there is no waste. This causes a problem in reducing the power consumption of semiconductor integrated circuit devices.

The present invention has been made to solve the above problems, and its purpose is to be able to obtain a voltage of approximately a predetermined level with a simple configuration, and to reduce power consumption by reducing power consumption. The purpose of the present invention is to provide a semiconductor integrated circuit device that can be used.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a first transistor connected to a first potential supply line, and a second transistor connected to a second potential supply line. , first and second voltage dividing resistors connected in series between the first and second transistors, an output terminal connected between both the voltage dividing resistors, and the first and second transistors. A conduction control means for simultaneously turning on or turning off at a predetermined frequency is provided, and a potential is supplied from the output terminal.

[Operation] When the first and second transistors are turned on by the conduction control means, a current flows from the first potential supply line to the second potential supply line via the first and second voltage dividing resistors. , the voltage between the first and second potential supply lines is divided by the first and second voltage dividing resistors, and the divided voltage is output from the output terminal. Further, since current flows from the first potential supply line to the second potential supply line only when the first and second transistors are turned on, power consumption is reduced.

[Example] An example embodying the present invention will be described below with reference to FIGS. 1 and 2.

For convenience of explanation, the same reference numerals are used to indicate the same components as in ``2'' and FIG. 5, and a portion of the explanation will be omitted.

FIG. 1 shows a power supply circuit formed on a chip, in which a P-channel MOS transistor 2 is connected to a power supply vCC as a first potential supply line, and an N-channel MOS transistor 2 is connected to a ground GND as a second potential supply line. MOS transistor 3 is connected. The voltage dividing resistors R1, R, 2 are connected in series between the P-channel and N-channel MOS transistors 2, 3, and the connection point between the resistors R1, R2 is determined based on the ON operation of both MOS transistors 2, 3. A voltage obtained by dividing the power supply VCC, that is, a shared voltage VR of the voltage dividing resistor R2 is generated at a, and the smoothing capacitor C1 is charged to the divided voltage VR. The smoothing capacitor CI outputs its charging voltage to the output terminal 1 as a reference voltage V REF as shown in FIG.
It is designed to be outputted from the MO8+- transistor and supplied to the load resistor R such as the gate terminal of the transistor.

An oscillator 4 serving as conduction control means is connected to the gate terminal of the P-channel MOS transistor 2 via an inverter 5 also serving as conduction control means, and is also connected to the gate terminal of the N-channel MO transistor 3. As shown in FIG. 2, the oscillator 4 outputs a control signal φ1 in which a low level signal and a high level signal are alternately switched at a predetermined frequency, and supplies it to the gate terminal of the transistor 3 of the N-channel MO8). signal φ
1 is inverted by an inverter 5 and supplied to the gate terminal of the P-channel MOS transistor 2 as a control signal φ2.

The period Tl of the low level signal of this control signal φ1 is set based on the discharging time constant CI-R and the allowable voltage fluctuation range dV of the reference voltage VREF shown in FIG. 2, and the period Th of the high level signal is set during charging. Constant CI・R1・ln2/ (R1
+R2) and the allowable voltage fluctuation width dV. Then, the frequency f of control signal φ1 = 1/(T
β+Th h, ). In this embodiment, the period T1 and the period Th of the control signal φI are each set to 25 μs, that is, the duty ratio is set to 50%, and the frequency is set to 20 kilohertz.

Then, the oscillator 4 simultaneously turns on the P-channel and N-channel MoS transistors 2.3 during the period Th when the control signal φ1 is at a high level (the control signal φ2 is at a low level), and the control signal φ1 is at a low level (the control signal φ2 is at a low level). During the period Tl (high level), the P-channel and N-channel MOS transistors 2 and 3 are simultaneously turned off.

Therefore, as shown in FIG. 2, the control signal φ1 output from the oscillator 4 turns on and off the P-channel and N-channel MOS transistors 2 and 3 at a predetermined frequency. The voltage VRBF is
During the period Th of the high level signal of the control signal φ1, the steady voltage rises to VR based on the charging time constant c1・R1・R2/(R]+R2), and during the period Tβ of the low level signal of the control signal φ1, the steady voltage increases. It descends from VR based on the discharge time constant 01·R. Since the voltage increase and voltage decrease stay within the permissible voltage fluctuation range dV, it is possible to output the reference voltage V REF from the output J terminal 1 at approximately a predetermined level.

In addition, in this embodiment, P channel and N channel MO3I-
The transistors 2 and 3 are connected to the control signal φ1 of the oscillator 4. Since φ2 is turned on with a duty ratio of 50%, current flows through the voltage dividing resistors R1 and R2 only when both MOS transistors 2°3 are turned on, so compared to the conventional power supply circuit shown in Figure 5. As a result, power consumption can be halved, resulting in power savings.

FIG. 3 shows another example in which the present invention is implemented in a DRA, M (dynamic ram). Each memory cell 6 includes an N-channel MOS transistor 9 whose source terminal is connected to the bit line 7 and whose gate terminal is connected to the word line 8;
A capacitor C2 is connected to the drain terminal of the transistor 9, and the output terminal 1 is connected to one electrode of each capacitor C2. In this example, each memory cell 6
Since the capacitor C2 is used as a smoothing capacitor, a dedicated smoothing capacitor C2 is used as in the above embodiment.
1 is not required. In this example, it is necessary to increase the load resistance connected to the output terminal 1 so that the data in each memory cell 6 is not destroyed.

In the above embodiment, the P-channel MOS transistor 2 was connected to the power supply ■CC, but as shown in FIG.
An N-channel MO8+- transistor 10 may be connected to the N-channel MOS transistor 10, and the control signal φ1 of the oscillator 4 may be directly input to the gate terminal of the N-channel MOS transistor 10.

Further, in the above embodiment, the duty ratio of the oscillator 4 was set to 50%, but the duty ratio of the oscillator 4 may be varied in consideration of the time constant due to the load resistance R and the smoothing capacitor CI. .

[Effects of the Invention] As detailed above, according to the present invention, a voltage of a predetermined level can be obtained with a simple configuration, and there is an excellent effect of reducing power consumption and saving power. .

[Brief explanation of drawings]

FIG. 1 is an electric circuit diagram showing an embodiment embodying the present invention, FIG. 2 is a waveform diagram showing the operation of the power supply circuit in one embodiment, and FIG. 3 is an electrical circuit diagram showing another embodiment. FIG. 4 is an electric circuit diagram showing another embodiment, and FIG. 5 is an electric circuit diagram showing a conventional power supply circuit. 2 is a P-channel MOS transistor as a first transistor; 3 is an N-channel MOS transistor as a second transistor; 4 is an oscillator that constitutes conduction control means; 5 is an inverter that also constitutes conduction control means; and GND
is the low power supply as the second potential supply line, R1 and R2 are the first
and the second voltage dividing resistor, VCC, is a high power source serving as a first potential supply line. In the figures, ■ indicates the output J terminal, 1 2 (input 0) Figure 3: Electrical circuit diagrams shown in different examples 19 Figure 4: Electrical circuit diagrams shown in different examples Figure 5: Conventional power supply circuit electrical circuit diagram

Claims (1)

[Claims] A first transistor (2) connected to a first potential supply line (VCC), a second transistor (3) connected to a second potential supply line (GND), first and second voltage dividing resistors (R1, R2) connected in series between the first and second transistors (2, 3); and connected between both voltage dividing resistors (R1, R2). an output terminal (1); and conduction control means (4, 5) for simultaneously turning on or turning off the first and second transistors (2, 3) at a predetermined frequency; 1. A semiconductor integrated circuit device characterized in that a potential is supplied from ).