JPH03266525A - Run length coding circuit - Google Patents

Abstract

PURPOSE:To attain high speed processing with simple constitution by employing the hardware for the run length coding processing. CONSTITUTION:The circuit is provided with a run length counter section 1 and an overflow code erasure section 2, a counter 11 of the run length counter section 1 counts consecutive zeros (ineffective coefficients) of an AC component data and outputs the result as a run length data and outputs once an overflow code when the count exceeds a prescribed value. when the overflow code is adjacent with a block end code EOB by the data count section 13, the code is erased by the overflow code erasure section 2. Thus, number of bits of the counter counting consecutive zeros is enough to be 4, and the simple circuit constitution not requiring complicated discrimination processing and enabling high speed processing is realized.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a run-length encoding circuit that counts the number of consecutive zero data and encodes that number and non-zero data to compress data, and particularly relates to a run-length encoding circuit that counts the number of consecutive zero data and encodes the number and non-zero data to compress data. This is suitable for application to data compression when still image data is compressed and transmitted or recorded.

[Conventional technology]

Figure 4 shows "Ba5eline", one of the international standardization methods proposed to standardize natural image coding methods.
FIG. 2 is a schematic diagram showing a data compression procedure of "System".

This system divides one input image into multiple blocks of 8×8 pixels, and performs discrete cosine transformation (DCT) on each block.
neTransform (processing P1), and divides the 8 x 8 DCT coefficients obtained by the conversion by the value obtained by multiplying each threshold value of a quantization matrix consisting of 8 x 8 dark values by a scale factor. (processing P2).

The direct current (DC) component of the quantized DCT coefficients is subtracted from the DC component quantized in the previous block (processing P3).
, the number of bits of the difference is Huffman encoded (processing P4
). The alternating current (AC) component performs a zigzag scan within the block and is converted into a one-dimensional sequence Ap (p=i+2+...,6
3) and processing P5), the consecutive zeros in the sequence Ap (
Run-length encoding and compressing the number of invalid coefficients (
Processing P6). Then, two-dimensional Huffman encoding is performed using the compressed number of consecutive zeros and the number of bits of the effective coefficient (processing P4).

FIG. 5 is a flowchart showing the processing operation for one block in run-length encoding processing (processing P6).

This process begins with the number of AC components in one block (6'
Initialize the variable p that counts the number of consecutive zeros (invalid coefficients) and the variable q that counts the number of consecutive zeros (invalid coefficients) to zero (
Step Sl).

Next, it is determined whether the variable p is 63, that is, whether all data processing of the AC component has been completed (step S2
). If NO" is determined in step S2, the variable P is incremented (step S3), and it is determined whether the value of the DCT coefficient Ap is zero (step S4). If the value of the coefficient Ap is zero, °"YES", the variable q is incremented in step S5), and the process returns to step S2.

If the value of coefficient Ap is not zero, then the value of variable q is 15
, that is, whether there are 16 consecutive zero data or not (step S6). If they are consecutive, it is determined as "'YES" and the number of consecutive zeros (value of variable q) is determined. The value divided by 16 is output as an overflow code (step S7). Then subtract 16 from variable q (
Step S8), return to step S6.

If the value of variable q is 15 or less, “NO” is returned in step S6.
It is determined that the number of consecutive zeros (value of variable q) and the value of coefficient Ap that is not zero data are output (step S9).

Then, the variable q is reset (step 510), and the process returns to step S2.

When the processing of all the AC component data is completed, step S2
``YES'' is determined, a block end code is output (step 511), and data processing for one block is ended.

[Problem to be solved by the invention] By the way, the above-mentioned "Ba5eltne 5ystea"
＊” data compression processing is at the stage where algorithms based on computer simulation are being considered.
D S P (Digital Signal Pro
Although there have been reports of hardware implementation using cessor), it takes a long time to process and is not practical.

An object of the present invention is to provide a run-length encoding circuit capable of high-speed processing with a simple configuration by converting the aforementioned run-length encoding processing into hardware.

[Means for Solving the Problems] The run-length encoding circuit according to the present invention includes a run-length counter unit that counts the number of consecutive zero data and outputs the result as run-length data, and an overflow output from the twenty-counter unit. and an overflow code erasing section that erases codes under certain conditions.

The run length counter unit includes a zero data detection unit that detects whether each of a plurality of n pieces of input data per block is zero data, and a zero data detection unit that detects whether or not each of a plurality of n pieces of input data is zero data or not, and a run length counter unit that detects whether consecutive zeros of input data are detected based on the detection result of this zero data detection unit. a counter section that counts the number of input data and outputs it as run length data; a data counting section that counts the number of input data and outputs a block end code when it detects that a plurality of n pieces of data have been input; It consists of an output control section that outputs flag data and shift pulses when valid data or an overflow code is output from the counter section, and when a block end code is output from the data counting section.

The overflow code erasing unit includes a shift register that latches input data, run length data, flag data, overflow code, and block end code, respectively, by a shift pulse, and a block end code among the overflow code and block end code latched in this shift register. and a continuity detection section that detects an overflow code adjacent to and erases the overflow code by clearing the corresponding flag data.

[For production]

In this configuration, the number of consecutive zeros (invalid coefficients) in the input data is counted by the run-length counter section, and the counted value is output as run-length data to perform data compression.

Furthermore, when the number of consecutive zeros exceeds a predetermined value, an overflow code is output once, the counter section is reset, and then counting of zero data is restarted.

Additionally, if an overflow code is adjacent to a block end code that indicates that data processing for one block has been completed, the overflow code is erased by resetting the corresponding data of the flag data that is output with the overflow code. There is. Therefore, even if the number of consecutive zero data is greater than or equal to a predetermined value, only the block end code is output without outputting an overflow code.

According to the present invention, it is possible to provide a run-length encoding circuit having a simple circuit configuration, in which the base number of a counter that counts the number of consecutive zeros can be small, and complex judgment processing is not required and high-speed processing is possible. I can do it.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of a run-length encoding circuit according to the present invention.

This embodiment consists of a run length counter section 1 and an overflow code erasing section 2.

The run length counter section 1 includes a zero data detection section 10 that detects whether input AC component data ACD is zero or not.
and a counter 11 that receives the output of the detection unit 10 and counts the number of consecutive zeros (invalid coefficients) in the data ACD.
A clear pulse C is sent to the counter 11 when the data ACD is not zero or when the counter 11 overflows.
An output control section 12 outputs flag data FD and a shift pulse SP to shift registers 20 to 24 (described later) of the data erasing section 2, and counts the number of input AC component data ACD to form one block. The data counting section 13 outputs a block end code EOB and a clear pulse CP' when it detects that input of AC component data for minutes has ended.

The overflow code erasing unit 2 collects AC component data ACD.
Shift register 2o to which is directly input, shift register 21 to which the count value of counter 11 is input as run length data RLD, shift register 22 to which flag data FD is input, shift register to which overflow code OVF of counter 11 is manually input. 23, shift register 24 into which the block end code EOB is input;
It consists of a continuity detection section 25 that detects continuity of data OVF and data EOB. Each of the shift registers 20 to 24 is composed of four stages of D-type flip-flops (hereinafter referred to as FF), and each stage of FF is driven by a shift pulse SP.

The continuity detection unit 25 includes an AND circuit 3o that takes an AND condition between each output of the FFs 23b to 23d in the second and subsequent stages of the shift register 23 and the output of the first stage 0FF 24a of the shift register 24, and a three-stage shift register 23. An AND circuit 31 that takes an AND condition between each output of each stage 0FF23c to 23d of the second stage and the output of the second stage 0FF24b of the shift register 24, the output of the fourth stage 0FF23d of the shift register 23, and the third stage of the shift register 24. It consists of an AND circuit 32 that takes an AND condition with the output of 0FF24c, and an OR circuit 33 that takes an OR condition of each output of the AND circuits 30 to 32. The output of the OR circuit 33 is input to the clear terminal CLR of the fourth stage 0FF22d of the shift register 22.

Next, the operation of this embodiment will be explained with reference to the timing chart shown in FIG.

First, the data counter 13 is cleared by a start pulse ST (FIG. (a)), and at the same time, the counter 11 is cleared by a clear pulse CP'.

Next, AC component data ACD (Figure (C)) is inputted in synchronization with the clock pulse φ (Figure (C)), and the zero data detection unit 10 detects whether or not it is zero data (Figure (D)).

When the detection unit 10 detects that the data is not zero, it outputs a shift pulse SP from the output control unit 12 to latch the data ACD in the first stage 0FF 20a of the shift register 20, and at the same time latches the flag data FD in the first stage FF 22a of the shift register 22. Latch. Further clear pulse C
The counter 11 is cleared by P.

If the AC component data ACD is zero data, the zero data detection unit 10 detects the zero data (Figure (d)), and the counter 1
Increment 1 (Figure (e)). If zero data continues, the number of consecutive zero data is counted by the counter 11.

Next, when valid data is input again as data ACD, the output control section 12 outputs a shift pulse SP
and flag data FD (FIG. (9)) are output, and the first stage FF of the shift register 20 is output by the shift pulse SP.
20a is data ACD, first stage FF of shift register 21
Run length data RLD is latched in 21a, and flag data FD is latched in the first stage FF 22a of the shift register 22. Further, the counter 11 is cleared by the clear pulse CP.

When zero data continues as data ACD and the count value of counter 11 exceeds 15, overflow code O
VF (FIG. Q1)) is output and input to the output control section 12. In response to this, the output control section 12 outputs a shift pulse S.
P and flag data FD, and shift pulse S
By P, the zero data of data ACD is transferred to FF20a, the data RLD is transferred to FF21a, and the flag data FD is transferred to FF.
22a, the data OVF is latched into the FF 23a.

When input of all AC component data is completed, the data counting section 13 outputs a block end code EOB. In response to this, the output control unit 12 outputs the shift pulse SP and flag data FD again, and transfers the data ACD to FF2.
0a, data RLD to FF21a, flag data FD to FF22a, and data EOB to FF24a.

In this way, the first stage FF2 of shift registers 20 to 24
1 for 0a to 24a, each data is shown in Figure 2 (j) to (n)
latched as shown.

Next, referring to the data configuration diagram in FIG.
The operation of step 5 will be explained.

The continuity detection unit 25 is a circuit that erases the overflow code OVF adjacent to the data EOB when the zero data of the AC component data ACD continues up to the block end code EOB. Data ACD has 63 pieces of data in one block, and the number of cases in which 16 pieces of zero data are consecutive is three times at maximum.

There are three possible cases in which data OVF and data EOB are continuous, as shown in FIGS. 3(a) to 3(C). Therefore, as shown in Figure (C), if there are a maximum of three consecutive data OVFs and further adjacent to the data EOB, four
It is necessary to detect the continuity of two data. Therefore, in this embodiment, each of the shift registers 20 to 24 has four stages, and the output of each stage of the shift register 23 to which the data OVF is input and the output of each stage of the shift register 24 to which the data EOB is input are divided into four stages. I am trying to detect continuity of data. In addition, the data OvF marked with ○ in the figure indicates the data to be output, and the data OV marked with
F indicates data to be erased.

First, data EOB is sent to FF24c of the shift register 24.
is latched, and at the same time FF23d of the shift register 23
When the data OVF is latched, the AND condition of the AND circuit 32 is satisfied, and the data flag is output from the OR circuit 33.
Clear pulse DFC is output (Figure (a)).

In addition, data EOB is stored in FF24b of the shift register 24.
is latched, FF23C of the shift register 23
If the data OvF is latched at ~23d, the AND condition of the AND circuit 31 is satisfied, and the data flag clear pulse DFC is output from the OR circuit 33 (Figure (b))
.

Furthermore, data EO is stored in the FF 24a of the shift register 24.
When B is latched, FF2 of the shift register 23
If the data OVF is latched in any of 3b to 23d at the same time, the AND condition of the AND circuit 30 is satisfied, and the data flag clear pulse DFC is output from the OR circuit 33 (Figure (C)). The clear pulse DFC clears the flag data FD latched in the final stage FF 22d of the shift register 22, invalidating the corresponding data OVF. In this way, data OVF adjacent to data EOB is erased and only data EOB is output.

〔Effect of the invention〕

According to this invention, a run length counter section and an overflow code erasing section are provided, and the run length counter section counts the number of consecutive zeros (invalid coefficients) in AC component data and outputs the counted value as run length data. At the same time, when the count value exceeds a predetermined value, an overflow code is output once, and if the overflow code is adjacent to the block end code EOB, it is erased by the overflow code eraser, so the number of consecutive zeros is The counter to count only needs 4 bits,
Further, it is possible to provide a run-length encoding circuit with a simple circuit configuration that does not require complicated judgment processing and can perform high-speed processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the run-length encoding circuit according to the present invention, FIG. 2 is a timing chart for explaining the operation of FIG. 1, and FIG. 3 is for explaining the operation of the continuity detector. FIG. 4 is a diagram showing the data compression procedure of the baseline system. FIG. 5 is a flowchart of the run-length encoding process in FIG. 4. 1...Run length counter section, 2..., i-'
Half-low code erasing section, 10... zero data detection section,
11... Counter, 12... Output control unit, 13...
・Data counting section, 20 to 24...Shift register, 2
5... Continuity detection section.

Claims (1)

[Claims] A zero data detection unit that detects whether each of a plurality of n pieces of input data per block is zero data, and a zero data detection unit that detects whether or not each of a plurality of n pieces of input data per block is zero data; a counter unit that counts the number of zeros in the input data and outputs it as run length data; and a data counting unit that counts the number of input data and outputs a block end code upon detecting that the plurality of n pieces of data have been input. and an output control section that outputs flag data and shift pulses when the input data is valid data, when an overflow code is output from the counter section, and when a block end code is output from the data counting section, respectively. a run-length counter section comprising: a shift register that latches the input data, the run-length data, the flag data, the overflow code, and the block end code, respectively, according to the shift pulse; A continuity detection unit detects the overflow code adjacent to the block end code among the overflow code and the block end code, and erases the overflow code by clearing the flag data corresponding to this overflow code. A run-length encoding circuit comprising: an overflow code erasing section.