JPH03265496A - Motor drive circuit - Google Patents

Abstract

PURPOSE:To save power and to perform smooth and highly accurate control of rotation by reading out sine wave data having a large amplitude from a memory at the starting time of rotation of a step motor and reading out a sine wave data having a small amplitude after rotation of the step motor. CONSTITUTION:A sine wave driver is provided with a ROM 1 containing four tables each storing sine wave data having different amplitude. Tables in the ROM 1 are switched based on a switching signal provided from a terminal 21 thus varying the amplitude of the sine wave. When a focus driving motor is started, amplitudes of the sine waves for phase A and B are increased. At a position where the phase A sine wave is 0 deg. immediately after rotation of the focus driving motor, amplitudes of the sine waves for phase A and B are switched to smaller amplitude.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a motor drive circuit suitable for driving a focus motor of a video camera, for example. A motor drive circuit that drives a focus motor with a sine wave includes a ROM that stores sine wave data with different amplitudes for each table, and an address generation circuit that generates an address for outputting the sine wave data from this ROM. When the step motor starts rotating, which requires a large torque, large-amplitude sine wave data is read out from the ROM, and when the step motor rotates, when the sine wave data at a predetermined angle is read out, the small-amplitude sine wave data is read out from the memory. In addition to reading out the amplitude sine wave data to save power, by changing the amplitude of the sine wave at the point when the sine wave data at a predetermined angle is read out, the amplitude applied to the step motor at the detent position can be changed, resulting in smooth rotation. This was done so that it could be maintained.

[Conventional technology]

Conventionally, a step motor has been used as a focus drive motor for controlling the position of a focus lens of a video camera because it can easily perform highly accurate control. Conventionally, this step motor is driven by a rectangular wave. However, when driving a step motor with a square wave,
Motor rotation becomes discontinuous, causing vibration and noise.

Therefore, in the past, vibrations have been absorbed using an impedance roller or the like. However, there are limits to such vibration countermeasures, and such mechanical vibration countermeasures become an obstacle to miniaturization and weight reduction.

Therefore, the inventor of the present application has proposed using a step motor as the focus drive motor and driving this step motor with a sine wave. Driving a step motor with a sine wave provides smooth rotation and reduces vibration and noise. This eliminates the need for mechanical vibration countermeasures.
It can be made smaller and lighter. Furthermore, power consumption can be reduced by driving the step motor with a sine wave.

[Problem to be solved by the invention]

A step motor requires large torque when starting rotation. While rotating, large torque is not required.

Therefore, it may be possible to save power by setting the step motor drive signal to a large amplitude at the start of rotation, and by setting the step motor drive signal to a small amplitude during rotation.

When the step motor is driven by a square wave, the 14th
As shown in the figure, the predetermined excitation pole 15 of the rotor 151
1A and the center of the predetermined excitation pole 152A of the stator 152 are at opposing positions (detent position).
The step motor rotates in steps. therefore,
Even if the step motor drive signal is switched from a large amplitude signal to a small amplitude signal at any timing, the rotation of the step motor is not affected.

However, when the step motor is driven with a sine wave, the detent position is not always reached. If the amplitude of the step motor is switched at a timing other than the detent position, a problem arises in that the rotation is not smooth.

Therefore, an object of the present invention is to save power by reducing the amplitude of the sine wave while the step motor is rotating, and to reduce the rotation by switching the amplitude of the sine wave at the detent position. An object of the present invention is to provide a motor drive circuit that allows smooth and highly accurate control.

[Means to solve the problem]

The present invention provides a motor drive circuit for driving a step motor with a sine wave, which includes a memory 1 in which sine wave data of different amplitudes are stored, and an address generation circuit 2 that generates an address for outputting sine wave data from the memory 1. When the step motor starts rotating, large-amplitude sine wave data is read out from memory 1, and when the step motor rotates, small-amplitude sine wave data is read out from memory 1 at the time when sine wave data at a predetermined angle is read out. This is a motor drive circuit characterized in that it is configured to read data.

[Effect]

For example, four tables are prepared in the ROMI, and each table stores sine wave data with different amplitudes. Therefore, by the switching signal from terminal 21, ROMI
By switching the table, you can switch the amplitude of the sine wave. This switching of the amplitude of the sine wave is performed when the focus drive motor 103 is at the detent position.

This allows smooth rotation to be maintained.

〔Example〕

Embodiments of the present invention will be described in the following order.

a, Overall configuration of sine wave driver 0 Configuration of inverting circuit C1 Thinning setting d, Configuration of thinning setting circuit in case of NTSC system e, N
Configuration 19 of a thinning setting circuit that can be shared by the TSC system and PAL system Frequency setting g, overall configuration of the video camera, autofocus control i, focus drive motor control a, overall configuration of the sine wave driver In Fig. 1, 1 is a ROM in which sine wave data is stored
It is. For example, four tables are prepared in the ROMI, and each table stores sine wave data ranging from 0 to 90 degrees with mutually different amplitudes, as shown in FIG. Each table has a capacity of (25+1) bits from 0 to 32, for example. The ROMI table is selected by a switching signal from the terminal 21. This ROMI table is switched at the timing when the step motor is at the detent position. When the step motor starts rotating, a table with a large amplitude is selected, and once the step motor rotates, a table with a small amplitude is selected. For example, by using the output of the upper 2-bit counter 3, the ROMI table can be switched at the timing of the detent position.

The address for ROMI is generated from counter 2. This address is supplied to the ROMI via the multiplexer 4 and the inversion circuit 7. Counter 2 is, for example, an 8-bit 2" counter.

The counter 2 is incremented, for example, from 0 to 512 by a clock HCK (horizontal synchronization pulse) applied from the terminal 22 via the gate circuit 6. As will be explained in detail later, the value obtained by counting the horizontal synchronizing pulses for one frame (525 in the case of NTSC system) is the number of powers of 2 (51
2), the thinning setting circuit 5 is provided. A clear signal is applied to the counter 2 from a terminal 23.

This clear signal is supplied at the timing of the detent position.

3 is the upper 2 bit counter. The upper 2-bit counter 3 is supplied with the carry of the counter 2 selected by the multiplexer 4. The upper 2-bit counter 3 generates polarity data corresponding to 0 to 90 degrees, 90 degrees to 180 degrees, 180 degrees to 270 degrees, and 270 degrees to 360 degrees. As shown in FIG. 3A, the output B of the upper 2-bit counter 3 is "0" for 0 to 90 degrees, "1" for 90 to 180 degrees, 'OJ' for 180 degrees to 270 degrees, and 'OJ' for 270 degrees to
At 360 degrees, it is "1". As shown in FIG. 3B, the output B2 of the upper 2-bit counter 3 is "0" from 0 to 180 degrees, and "1" from 180 degrees to 360 degrees.

The count output of the counter 2 is supplied to the multiplexer 4 and also to the decimation setting circuit 5. A selection signal is supplied to the multiplexer 4 from a terminal 24 .

The output of the counter 2 is bit-shifted by a multiplexer 4 according to a selection signal. This sets the frequency of the generated sine wave. And multiplexer 4
Then, 5 bits of the 8-bit count value from counter 2 are selected and output.

The thinning setting circuit 5 sets the clock HCK to be counted so that the value obtained by counting the clock HCK from the terminal 22 for one frame by the counter 2 (525 in the case of the NTSC system) becomes a power of 2 (2''=512). This is to thin out the clock HCK at approximately equal intervals.When thinning the clock HCK, the gate circuit 6 is closed by the output of the thinning setting circuit 5.

The inverting circuit 7 inverts the address every 90 degrees and advances the address. In this way, by inverting and stepping the address every 90 degrees, one period of a sine wave can be formed using 90 degrees of sine wave data stored in the ROMI.

In other words, as shown in Figure 2, ROMI has 0.1
．． 90 degree sine wave data do, dl, di, dx, . . . are stored corresponding to each address 2.3, . As shown in FIG. 4A, if addresses 0.1, 2.3, .
... are sequentially read out, and a sine wave ranging from 0 to 90 degrees is obtained. As shown in FIG. 4B, if addresses 31, 30, 29, .
, . . . are sequentially read out, and a sine wave of 90 to 180 degrees is obtained. As shown in FIG. 4C, sine wave data do, dl, dz, d are given to ROMI with addresses 0.1.2.3, .
By sequentially reading out sine wave data aa s dl s dz , (1, . As shown in the fourth diagram, 1 is stored in ROM1.
Addresses 31, 30, 29, . . . increments in the opposite direction.
・The sine wave data d31, d, is given. ,a
zq, . . . are read out sequentially, and the read sine wave data d3+, dl. , dzw, . . . by reversing the polarities, a sine wave of 270 to 360 degrees can be obtained.

Addresses that step in the opposite direction can be formed by taking the two's complement of the address. That is, for example, if a 5-bit address is incremented in sequence, 1.2.3, ... (r
O0001,J, rooolo'', rooollJ,
...) can be created that advances in the forward direction.

Taking the two's complement of this address is 31.30.29,
...("IIIIIIJ, rlllloJ, rlllo
IJ...), and an address that advances in the opposite direction can be formed.

Note that the counter returns to 0 when it reaches the maximum value.

The two's complement of roooooo is roooooo. Therefore, if we take two's complement every 90 degrees to form an address that steps in the opposite direction, then after the address reaches 31"1lllllJ and the maximum value of sine wave data is read out, , the address is Orooooo,
, returns to +, - degrees, and the minimum value of the sine wave data is read out. After that, the count value becomes rooooIJ and 2
The address obtained by taking the complement of is 31rllllll'', and the maximum value of the sine wave data is read out. For this reason, the sine wave data read out is no longer continuous.

Therefore, in one embodiment of the present invention, address 32'1
00OOOJ is provided, and the maximum value of the sine wave data is stored in this address 32. Counter is 31 rllll
When the count returns to 0 "00000" after counting up to "ll", a carry is generated. At this time, the address is orooo.

Instead of ``O'', it is read as 32 ``100OOOJ'', and the maximum value is read out.

Note that all bits of the address may be inverted instead of taking the two's complement of the address. In this case, there is no need to provide the address 32.

In FIG. 1, an inversion signal is supplied to an inversion circuit 7 via an EX-NOR gate 26. When the inversion signal applied to ROMI via this EX-NOR gate 26 is, for example, "1", the sidewalk direction of the address is inverted.

The output B1 of the upper 2-bit counter 3 is supplied to one input terminal of the EX-NOR gate 26, and the clock HCK is supplied to the other input terminal of the EX-NOR gate 26. The output B1 of the upper 2-bit counter 3 switches every 90 degrees, as shown in FIG. 3A. Therefore, the inversion circuit 7 inverts the advancing direction of the address every 90 degrees.

Further, the EX-NOR gate 26 is supplied with a clock HCK. Therefore, the state of the inverting circuit 7 is switched between the period when the clock HCK is at a high level and the period when the counter HCK is at a low level. In this way, 1
By dividing the clock into two and controlling the inversion circuit 7,
It is possible to obtain sine waves with mutually different phases.

That is, FIG. 3C and the third diagram show the addresses respectively given to ROMI when clock HCK is at high level and when clock HCK is at low level. From 0 to 90 degrees, the output B of the upper 2-bit counter 3 (FIG. 3A) is r□, so when the clock HCK is at a high level, the EX-NOR gate 26
The output of is "0". Therefore, while the clock HCK is at a high level, an address that increments in the forward direction is given from 0 to 90 degrees as shown in FIG. 3C. 0-9
When it is 0 degrees and the clock HCK is low level, EX-
The output of the NOR gate 26 becomes "1". therefore,
While the clock HCK is at low level, the angle ranges from 0 to 90 degrees.
As shown in the third diagram, an address that increments in the opposite direction is given.

From 90 degrees to 180 degrees, the output B1 of the upper 2-bit counter 3 is set to "1", so when the clock HCK is at a high level, the output of the EX-NOR gate 26 is "1".
becomes. Therefore, while the clock HCK is at a high level, an address that advances in the opposite direction from 90 degrees to 180 degrees as shown in FIG. 3C is given. 90 degrees ~ 180
and when the clock HCK is low level, EX-N
The output of the OR gate 26 becomes "0". Therefore, while the clock HCK is at a low level, an address is given that advances in the forward direction from 90 degrees to 180 degrees as shown in the third diagram.

From 180 degrees to 270 degrees, the output B of the upper 2-bit counter 3 is "0", so when the clock HCK is at a high level, the output of the EX-NOR gate 26 is "0".
”. Therefore, while the clock HCK is at a high level, an address that increments in the forward direction from 180 degrees to 270 degrees as shown in FIG. 3C is given. 180 degrees ~
When the temperature is 270 degrees and the clock HCK is low level, EX
The output of the NOR gate 26 becomes "1". therefore,
While the clock HCK is at low level, the angle is 180 degrees to 27 degrees.
At 0 degrees, an address is given that steps in the opposite direction, as shown in the third diagram.

From 270 degrees to 360 degrees, the output B1 of the upper 2-bit counter 3 is set to "1", so when the clock HCK is at a high level, the output of the EX-NOR gate 26 is "1".
Therefore, while the clock HCK is at a high level, an address that steps in the opposite direction from 270 degrees to 360 degrees as shown in FIG. 3C is given. 270 degrees~
At 360 degrees, when the clock HCK is low level, E
The output of the X-NOR gate 26 becomes "0". Therefore, while the clock HCK is at low level, 270 degrees to
At 360 degrees, addresses are given that step forward in the forward direction, as shown in the third diagram.

Sine wave data is output from ROM1 according to the address given to ROMI. This sine wave data is taken into the latch circuit 8 when the clock HCK falls. Then, at the rising edge of the clock HCK, the output of the latch circuit 8 is taken into the D flip-flop 9, and the RO
The output of MI is taken into D flip-flop lO.

Therefore, the sine wave data output from the ROMI during the period when the clock HCK is at a high level is taken into the D flip-flop 9. The sine wave data output from ROMI during the period when the clock HCK is at low level is
It is taken into the D flip-flop lO.

The output of the D flip-flop 9 is the PWM drive circuit 11
is supplied to The output of D flip-flop 10 is PWM
The signal is supplied to the drive circuit 12.

PWM drive circuits 11 and 12 generate PWM signals based on the outputs of flip-flops 9 and 10. This P
A WM signal is output from output terminals 15 and 16 and supplied to the step motor.

Outputs B and B2 of the upper 2-bit counter 3 are supplied to polarity decoders 13 and 14. The polarity decoders 13 and 14 form polarity signals as shown in FIGS. 3E and 3F. Current is passed through the step motor in the direction corresponding to this polarity.
As shown in the figure, two-phase sine waves having different phases are passed through the step motor, and the step motor is driven.

Structure of the b1 inversion circuit As mentioned above, the inversion circuit 7 which inverts the address in the sidewalk direction every 90 degrees is configured as shown in FIG.

In FIG. 5, 5-bit input addresses "81-asJ" are supplied to input terminals 31A-31E, respectively.

This input address "a1 to asJ is EX-OR gate 3
It is supplied to one input end of 2A to 32E. EX-OR
An inverted signal is supplied from the terminal 30 to the other input ends of the gates 32A to 32E.

The outputs of the EX-OR gates 32A-32E are supplied to one input end of the no-h-faders 33A-33E. The inverted signal from the terminal 30 is supplied to the other input end of the half adder 33A. The carry of the adder 33A is supplied to the other input terminal of the half adder 33B. The carry of half adder 33B is supplied to the other input terminal of half adder 33C. The carry of the half adder 33C is supplied to the other input end of the no.lambda.-fadder 33D.

The carry of the half adder 33D is supplied to the other input end of the A-fadder 33E.

The outputs of the half adders 33A to 33E and the carry of the /'1-fader 33E are the address r A for ROM1.
, -A h J are outputted from the output terminals 34A to 34F.

When forming an address that advances in the forward direction, terminal 3
The inverted signal from 0 is set to "0". Inverted signal is “0”
In this case, the input addresses "a, ~asJ" from the input terminals 31A to 31E are the EXOR gates 32A to 32E,
The signals are output as they are via the half adders 33A to 33E, respectively.

When forming an address that advances in the opposite direction, terminal 3
The inverted signal from 0 is set to "1". The inverted signal is rl,
Then, "1" is given to one input terminal of EX-OR gates 32A to 32E, so EX-OR gate 3
Each bit of addresses ra and -asJ from input terminals 31A to 31B is inverted at 2A to 32E, respectively. Then, "1" is sent from the input terminal 31A to the half adder 33A.
Since an inverted signal is supplied, the half adder 33
A to 33E, the address "i," inverted for each bit.
"1" is added to ~asJ. As a result, a two's complement address is obtained. These two's complement addresses rA and -AbJ are output from output terminals 34A to 34F.

C3 thinning setting For example, the number of lines in one frame of an NTSC video signal is 525. Therefore, the horizontal sync pulse is
The value when counted for one frame is 525, which is not a power of 2. When focus control is performed in a vertical cycle in a video camera, it is desirable that the count value of horizontal synchronizing pulses for one frame be a power of two.

Therefore, in one embodiment of the present invention, a thinning setting circuit 5 is provided, and the clocks HCK (horizontal synchronizing pulses) to be counted are thinned out at approximately equal intervals.

As a result, the value when counting the horizontal synchronizing pulses for one frame becomes 512, which is a number that is a power of two.

In the case of the NTSC system, the horizontal synchronizing pulse for one frame is 525, so in order to make the value 512 when counting for one frame, the horizontal synchronizing pulse should be counted by (525-511=13). All you have to do is thin out the sync pulses. Consider thinning out these 13 pulses at approximately equal intervals.

In the .27 counter, each bit output is a number that is a power of 2, so the count value can be thinned out for every number that is a power of 2. 1
The number of powers of 2 closest to 3 is (2'=16).

To thin out 16 pulses from 525 pulses almost equally, 3
It is sufficient to thin out one pulse every two pulses.

In this way, when one pulse count value is thinned out every 32 pulses and the count value is thinned out by 16 pulses, the original number of pulses to be thinned out is 13 pulses, so three extra pulses are thinned out. Therefore, it is necessary to stop pulling for these three pulses.

The number of powers of two closest to three is four. Therefore, as mentioned above, 4 of the 1 pulse is thinned out every 32 pulses.
Try to stop thinning out the pulses once every time.

If this is done, the number of decimated pulses per pulse will be insufficient.

Therefore, the pulse thinning is further performed once every four times when the pulse thinning is stopped.

As a result, 13 pulses are thinned out almost equally from 525 pulses.

d. Configuration of decimation setting circuit in case of NTSC system FIG. 6 shows the configuration of a decimation setting circuit in case of NTSC system.

In FIG. 6, bit b+ of counter 2, bit b2
, bit b3, bit b4, bit b.

The output of is supplied to AND gate 41. The output of the AND gate 41 becomes "1" every 32 pulses. This AN
The output of the D gate 41 sets the thinning of one pulse every 32 pulses. The output of AND gate 41 is AND
It is supplied to the gate 43 and also to the AND gate 45.

The output of bit b6 and the output of bit b6 are supplied to the AND gate 42. The output of the AND gate 42 is inverted and supplied to the AND gate 43, and
The signal is supplied to the gate 45.

By supplying the inverted output of AND gate 42 to AND gate 43, decimation is inhibited once every fourth of the 1 pulse decimation every 32 pulses. The output of AND gate 43 is supplied to OR gate 44.

Output of AND gate 41, output of AND gate 42, bit bl of counter 2, carry bit b of counter 2
, are supplied to the AND gate 45. The output of AND gate 45 is supplied to OR gate 44. By supplying the output of the AND gate 45 to the OR gate 44, one pulse is thinned out once every four pulses are prohibited.

The output of the OR gate 44 is supplied to a D flip-flop 46 and also to one input terminal of a NAND gate 47. D flip-flop 460 inverted output is NA
The signal is supplied to the other input terminal of the ND gate 47.

The output of NAND gate 47 is supplied to one input of NAND gate 48.

A clock from clock input terminal 49 is supplied to the other input terminal of NAND gate 48 and is also supplied to the clock input terminal of D flip-flop 46 . NAND
The output of gate 48 is fed to the clock input of counter 2.

e. Configuration of a thinning setting circuit that can be shared by both the NTSC system and the PAL system In the case of the PAL system, the number of horizontal synchronizing pulses in the e-frame is 625, so the number of addresses is set to a power of 2 (
2” = 512), (625-512=11
3) It is necessary to thin out the number of pulses. This is 11
This is done by uniformly thinning out the number of powers of 2 closest to 3 (27=128), stopping thinning out for 16 pulses, and then thinning out one pulse out of the 16 pulses. .

FIG. 7 shows an example in which the NTSC system and the PAL system can be used in common. In FIG. 7, the output of bit b of counter 2 and the output of bit b2 are connected to an AND gate 51.
is supplied to The output of bit b3 to bit b5 is AND
The signal is supplied to the gate 52. Output of bit b6 and bit b
, are supplied to the AND gate 53.

The switching signal from the terminal 50, the output of the AND gate 51, and the inverted output from the AND gate 52 are supplied to the AND gate 54.

The inverted output of the switching signal from the terminal 50, the output of the AND gate 5I, the output of the AND gate 52, and the inverted output of the AND gate 53 are supplied to the AND gate 55.

Output of AND gate 51, output of AND gate 52, A
The output of ND gate 53, the output of bit bIl of counter 2, and the output of carry bit b of counter 2 are supplied to AND gate 56.

The outputs of the AND gates 54, 55, and 56 are the OR gates 57
is supplied to

The output of the OR gate 57 is supplied to a D flip-flop 58 and also to one input terminal of a NAND gate 59. The inverted output of D flip-flop 59 is NA
It is supplied to the other input terminal of ND gate 59.

The output of NAND gate 59 is supplied to one input terminal of NAND gate 60.

A clock from clock input terminal 61 is supplied to the other input terminal of NAND gate 60 and also to the clock input terminal of D flip-flop 58 . NAND
The output of gate 60 is fed to the clock input of counter 2.

In the case of the NTSC system, the switching signal from the input terminal 60 is set to "0". In this case, as described above, 13 pulses are thinned out almost equally. In the case of the PAL system, the selection signal from the input terminal 50 is rl.

In this case, 113 pulses are thinned out almost equally.

19 Frequency Setting In one embodiment of the present invention, a 2'' counter is used as the counter 2 that generates an address, and the maximum count number of the counter 2 is set to a power of 2. If the address is generated using a bit shift, the frequency can be set by bit shifting. In other words, if the output of counter 2 is shifted by one bit so that the address is advanced by one step every two clocks, the frequency is set to (1/2). If the output of counter 2 is shifted in the opposite direction, the frequency will be set to double.

FIG. 8 shows the configuration of the multiplexer 4.

In FIG. 8, 8-bit outputs -b and carry bit output from counter 2 are supplied to input terminals 71A to 71J, respectively.

Selection signals S0 and SI are supplied to input terminals 74A and 74B, respectively. Selection signal S from input terminal 74A
0 is supplied to AND gates 75A and 75B, and this selection signal S0 is inverted and output to AND gate 75C.
and 75D. A selection signal S1 from an input terminal 74B is supplied to AND gates 1-75A and 75C, and this selection signal SI is inverted and supplied to AND gates 75B and 75D.

When the selection signal S0 is "1" and the selection signal SI is "1", the output of the AND gate 75A becomes "1", and the AND
The outputs of the gates 75B to 75D become r□. Therefore, switch circuits 76A, 77A, 78A, 79A, 8
0A and 81A are turned on, and the other switch circuits are turned off.

Therefore, bits b1~ from input terminals 71A~71F
The output of b6 is output from output terminals 82A to 82F, respectively.

When the selection signal S0 is "1" and the selection signal S1 is "0", the output of the AND gate 75B becomes "1", and the AND
The outputs of gates 75A and 75C175D become "0".

Therefore, switch circuits 76B, 77B, 78B, 7
9B, 80B, and 81B are turned on, and the other switch circuits are turned off.

Therefore, bits b2 to 71B of input terminals 71B to 71G
b? The outputs of 1 are output from the output terminals 82A to 82F, and 1
It is set to a bit-shifted state.

When the selection signal S0 is "0" and the selection signal S1 is "1", the output of the AND gate 75C becomes "1", and the AND
The outputs of gates 75A, 75B, and 75D become "0".

Therefore, switch circuits 76C, 77C178C17
9C180C181C is turned on and the other switch circuits are turned off.

Therefore, bits b3~ from input terminals 71C~711
The outputs up to b are output from output terminals 82A to 82F, and are set in a state shifted by 2 bits.

When the selection signal S0 is "1" and the selection signal S is "1", the output of the AND gate 75D becomes "1", and the AND
The outputs of gates 75A, 75B, and 75C become "0".

Therefore, switch circuits 76D, 77D, 78D, 7
9D, 80D.

81D is turned on and the other switch circuits are turned off.

Therefore, bits b4~ from input terminals 71D~71J
The outputs up to b are output from output terminals 82A to 82F, and are set in a state shifted by 3 bits.

Outputs a1 to a of the output terminals 82A to B2E are supplied to the inverting circuit 7 in FIG. The output from the output terminal 82F is supplied to the upper 2-bit counter 3 as a carry.

g. Overall configuration of video camera The present invention is used to drive a focus drive motor of a video camera.

FIG. 9 shows the overall configuration of a video camera to which the present invention can be applied. In Figure 9, 10
1 is a lens, and 102 is a CCD image sensor. A subject image is formed through the lens 101 on the light receiving surface of the CCD image sensor 102, and an image signal is obtained from the CCD image sensor 102.

As shown in FIG. 10, the lens 101 includes a fixed lens Fl (first group lens) and a zoom lens F2 (second group lens).
, Fixed lens F3 (3rd group lens), Focus lens F
4 (4 group lenses) are arranged. A PN filter 117 and an iris ring 118 are arranged between the zoom lens F2 and the fixed lens F3. A dummy glass 119 for cutting infrared rays is arranged opposite to the focus lens F4.

A focused position can be obtained by moving the focus lens F4. The position of this focus lens F4 is movable by a focus drive motor 103. A step motor is used as the focus drive motor 103 so that highly accurate control can be easily performed. This step motor is driven with a sine wave by a sine wave driver 113 to which the present invention is applied in order to reduce vibration and noise. Furthermore, opening and closing of the iris ring 118 within the lens 1 is controlled by the iris drive motor 104. The open/closed state of the iris ring 118 is detected by an iris position detecting device 05 composed of, for example, a Hall element. Also,
The position of zoom lens F4 is detected by zoom position detector 106. The outputs of the iris position detector 105 and the zoom position detector 106 are supplied to the system controller 112.

The output of the CCD image sensor 102 is sent to the sample hold circuit 1
07. When a complementary color checkerboard pixel array is used as the CCD image sensor 2, the sample and hold circuit 107 outputs two pixels each in the vertical direction.
The output signal of the D image sensor 102 is sampled and held. The output of the sample hold circuit 107 is sent to the AGC circuit 10.
8 to the A/D converter 109. A/
A D converter 109 digitizes the output of the CCD image sensor 102, for example, in 10 bits.

The output of the A/D controller 109 is supplied to a digital video signal processing circuit 110 and also to an optical detector 111. The optical detector 111 generates an AF detection signal for autofocus control, an AE detection signal for automatic exposure, and an AWB detection signal for auto white balance.

Optical detector III and system controller 112 are bidirectionally connected via a serial interface. Via this serial interface, signals are exchanged between the optical detector 111 and the system controller 112 every vertical period.

A focus detection area setting signal, an exposure detection area setting signal, a white balance detection area setting signal, etc. are supplied from the system controller 112 to the optical detector 111. From the optical detector 111 to the system controller 112, an AF (autofocus) detection signal, an AE (autoexposure) detection signal,
An AWB (auto white balance) detection signal and the like are supplied.

Based on the AF detection signal sent from the optical detector 111 to the system controller 112, the system controller 112 outputs a lens drive signal. This lens drive signal is supplied to the focus drive motor 103 via a sine wave driver 113. Thereby, the position of the focus lens F4 is controlled to be at the in-focus position.

Based on the AE detection signal sent from the optical detector 111 to the system controller 112, the system controller 112 outputs an iris control signal and an AGC control signal. This AGC control signal is also supplied to the AGC circuit 108 via the D/A converter 115.Thereby, the iris ring is controlled according to the level of the image signal from the CCD image sensor 102. 118 is opened and closed, and the gain of the AGC circuit 108 is set.

A digital video signal processing circuit 110 processes the luminance signal and chroma signal. These signal-processed luminance signals and chroma signals are output to D/A converters 115A and 1.
15B, each is converted into an analog signal, and outputted from output terminals 116A and 116B, respectively.

h. At the autofocus control focusing position, the level of the middle and high frequency components in the luminance signal from the CCD image sensor 102 is maximum. Therefore, C.C.D.
An evaluation value is a value obtained by integrating the middle and high frequency component level in the luminance signal from the image sensor 102 within a predetermined focus area,
Focus lens F4 so that this evaluation value becomes maximum
By controlling the position of the lens, the in-focus position can be obtained.

In the video camera shown in FIG. 9, focus control is performed based on this principle.

That is, the AF detection circuit in the optical detector 111 extracts the mid-high frequency component level in the image pickup signal from the CCD image sensor 102, and integrates this mid-high frequency component level within a predetermined focus area. A value obtained by integrating this middle and high frequency component level within a predetermined focus area is sent from the optical detector 111 to the system controller 112 every vertical period as an AF detection signal.

A drive signal is supplied from the system controller 112 based on this AF detection signal. Based on this drive signal, a <PWM signal is generated from the sine wave drive bar 113 based on two-phase sine waves having mutually different phases.

This two-phase PWM signal rotates a focus drive motor 103 configured as a step motor.

The system controller 112 detects the lens position at which the AF detection signal obtained in each vertical period is maximum, for example by hill climbing control. At this position, the focus drive motor 103 is stopped.

i. Control of Focus Drive Motor A sine wave driver shown in FIG. 1 is used as the sine wave driver 113 for driving the focus drive motor 103 having a step motor configuration.

As described above, when autofocus control is performed by capturing the AF detection signal every vertical period, the focus drive motor 103 is stopped every vertical period, and the focus drive motor 103 is stopped every vertical period, as shown in FIG. While stopped, an AF detection signal is captured at T. and,
Once the control amount is determined, the focus drive motor 103 is driven accordingly.

In the sine wave driver to which this invention is applied, as shown in FIG. number (512). Therefore, when the focus drive motor 103 is stopped every vertical period and the AF detection signal is transmitted, the focus drive motor 103 can be stopped at the detent position. That is, as shown in FIGS. 12A and 12B, when the focus drive motor 103 is stopped at time tA after moving the focus drive motor 103 for one frame, A
The focus drive motor 103 is stopped at the timing when the phase sine wave becomes 0 degrees, and the focus drive motor 103 is stopped at the detent position. Therefore, stable control can be performed.

By the way, when starting the rotation of the focus drive motor 103, a large torque is required. After the focus drive motor 103 rotates, large torque is not required.

Therefore, when starting the focus drive motor 103, a large amplitude sine wave is applied to obtain sufficient torque, and once the focus drive motor 103 rotates,
In order to save power, the amplitude of the sine wave applied to the focus drive motor 103 is reduced.

In the sine wave driver to which the present invention is applied, 1. As shown in FIG. 1, for example, four tables are prepared in the ROMI, and each table stores sine wave data with different amplitudes. Therefore, by switching the ROMI table using a switching signal from the terminal 21, the amplitude of the sine wave can be changed. Switching the amplitude of this sine wave is
This is done when the focus drive motor 103 is at the detent position. This allows smooth rotation to be maintained.

That is, as shown in FIGS. 13A and 13B, when the focus drive motor 103 is started, the A-phase and B-phase sine waves have large amplitudes. Immediately after the focus drive motor 103 rotates, the amplitudes of the A-phase and B-phase sine waves are switched to small amplitudes at a time point t1 when the A-phase sine wave reaches 0 degrees. In this way, since the amplitude of the sine wave is switched at the detent position, smooth rotation can be maintained.

〔Effect of the invention〕

According to this invention, when starting the focus drive motor 103, a large amplitude sine wave is applied to obtain sufficient torque, and when the focus drive motor 103 rotates, a sine wave is applied to the focus drive motor 103. amplitude is reduced.

Thereby, power saving can be achieved.

For example, four tables are prepared in the ROMI, each table stores sine wave data with different amplitudes, and terminal 2
By switching the ROMI table using the switching signal from 1, the amplitude of the sine wave can be switched. This switching of the amplitude of the sine wave is performed when the A-phase sine wave reaches 0 degrees. Therefore, the amplitude of the sine wave is determined at the detent position, and smooth rotation can be maintained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention, FIG. 2 is a route map used to explain the ROM table,
Figure 3 is a timing diagram used to explain one embodiment of this invention, Figure 4 is a route diagram used to explain the principle of this invention, and Figure 5 is a route diagram used to explain the principle of this invention.
The figure is a block diagram of an example of an inversion circuit, Figures 6 and 7 are block diagrams of an example of a thinning setting circuit and other examples, Figure 8 is a block diagram of an example of a multiplexer configuration, and Figure 9 is a block diagram of an example of the configuration of a multiplexer. FIG. 10 is a side view used to explain the lens configuration of the video camera to which the present invention is applied, FIG. 11 is a timing diagram used to explain motor control, and FIG. The figure is a waveform diagram used to explain the control when stopping rotation, number 13.
The figure is a waveform diagram used to explain when changing the amplitude, and FIG. 14 is a route diagram used to explain a conventional step motor. 7: Inversion circuit.

Claims (1)

[Claims] A motor drive circuit that drives a step motor with a sine wave includes a memory that stores sine wave data of different amplitudes, and an address generation circuit that generates an address for outputting the sine wave data from the memory. When the step motor starts rotating, large-amplitude sine wave data is read from the memory, and when the step motor rotates, a small-amplitude sine wave data is read from the memory when the sine wave data at a predetermined angle is read. A motor drive circuit characterized by reading data.