JPH03265240A - Data cryptographic processing circuit - Google Patents

Abstract

PURPOSE:To process a data with one cryptographic processing circuit and to miniaturize the equipment by replacing an input section and an output section when the data input/output direction is subject to switching control for the direction of data cryptographic processing direction at transmission/reception and controlling the data in two-way. CONSTITUTION:When one of input/output direction control circuits 1, 2 acts like an input circuit by using a control signal 101, the other acts like an output circuit. A latch circuit 4 latches a key for encrypting a transmission data and decoding an input data and a latch circuit 5 latches an input data. A control signal selection circuit 3 gives a data to the latch circuits 4, 5 in response to the input/output control direction. The processing circuit is provided with a cryptographic (decoding) processing circuit 6, an output data latch circuit 7, a selection circuit 8 and an output data selection control counter 9 setting a timing of selection arrangement and applies data cryptographic transmission and decoding reception under the control of a write signal control circuit 10 and a write signal enable circuit 11. Since no CPU is interposed, the constitution is simplified and the increase in the processing time is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data encryption processing circuit, and more particularly to a data encryption processing circuit used in a special number digital communication device.

[Conventional technology]

Conventionally, data encryption processing circuits had fixed data input and output sections, and could only perform data input/output (yaw direction).
It was equipped with two data encryption processing circuits of approximately the same scale.

In addition, the data output method is such that the processing status of the encryption (decryption) processing circuit is monitored by the CPU, and after confirming the completion of the processing, the
The PU performs output control and outputs data from G.
Furthermore, data is written to external circuits such as a transmitter under the control of the CPU.

FIG. 2 is a block diagram of a conventional data encryption processing circuit.

In actual operation, two circuits are provided, one for transmitting and one for receiving.

The case where the data encryption processing circuit shown in FIG. 2 is used for decryption processing will now be described as an example.

Data/key input via external circuit received from communication destination 201
．． Input enable signal 202. A key 206 and input data 207 are extracted from the decryption key latch circuit 21 and the input data latch circuit 22, which receive the write signal 203 and the latch circuit selection signal 204, respectively, and are supplied to the decryption processing circuit 23.

The decoding processing circuit 23 performs decoding processing while being supplied with a clock 205, outputs an output data latch signal 208 and processing end data 209, and then latches the decoded data in the output data latch circuit 24. The captured latch data is supplied to the output data selection circuit 25 as output data 210. The decoding processing circuit 23 also outputs a decoding processing end signal 213.

In general, in block encryption, encrypted data includes unnecessary bits and other bits that are not directly related to the data, and is processed in parallel. Therefore, in order to obtain desired output data in a time-series manner, the timing for selecting the data arrangement for reproducing the desired time-series signal from such latch output data 210 output from the output data latch circuit 24 is determined. Information and sequence selection processing are required.

The output data selection circuit 25 performs the above-described array selection processing on the latch output data 210, and the output data selection control circuit 26 performs the above-described array selection processing on the latch output data 210, and the output data selection control circuit 26 performs the above-described array selection processing on the latch output data 210. The control signal 212 as the above-mentioned timing information is generated, the output data selection circuit 25 outputs the decoded desired output data 211, and this and the decoding process end signal 213 are sent to a higher-order external circuit such as a CPU. Sent out.

The above description applies to the case of decryption, that is, when data is received. However, when data is encrypted and transmitted, the decryption key latch circuit 21 is used as an encryption key latch circuit, and the decryption processing circuit 23 is used as an encryption key latch circuit. By changing and configuring the encryption processing circuit, processing can be performed using almost the same processing procedure.

[Problem to be solved by the invention]

In the conventional data encryption processing circuit described above, the data input section and output section are fixed, so data input/output can only be performed in one direction. Therefore, in order to receive data, , it is necessary to have one data encryption processing circuit for transmission and one for reception, which has the disadvantage that the circuit configuration becomes large.

In addition, in order to output the encrypted data, the CPU constantly monitors the processing status of the encryption (decryption) processing circuit, and after confirming the completion of the processing, the CPU controls the output. This has the effect of increasing the number of processing items for the CPU, which lengthens the processing time of the system and makes the circuit configuration complex.

[Means to solve the problem]

The data encryption processing circuit of the present invention has two input/output circuits, a first and a second input/output circuit, which enable data transmission and reception by controlling the input/output direction so that when one inputs data, the other outputs data. A direction control circuit, an encryption (decryption) key latch circuit that latches a key for encrypting data to be sent and decrypting encrypted input data, and an input data latch circuit that latches input data. and, corresponding to the data input/output control direction, either the data whose direction is controlled by the first or second input/output direction control circuit is sent to the encryption (decryption) key latch circuit and the input data latch circuit. an encryption (decryption) processing circuit that encrypts data to be sent and decrypts received encrypted data; and a control signal selection circuit that causes the encryption (decryption) processing circuit to latch output data. an output data latch circuit that outputs data from the output data latch circuit, an output data selection circuit that selectively arranges data output from the output data latch circuit into predetermined time series data in encryption or decryption, and timing of selection arrangement in the output data selection circuit. an output data selection control counter circuit that performs settings; a write signal enable circuit that performs enable control for writing data sent to an external circuit; and the output data selection circuit. The write signal control circuit outputs a write signal to an external circuit to the write signal enable circuit under the control of a control counter circuit, and is configured to perform data encryption transmission and data decryption reception.

Further, the data encryption processing circuit of the present invention has a configuration in which the encryption is block encryption.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The embodiment shown in FIG. 1 has two input/output directions, a first and a second input/output direction, which enable data transmission and reception by controlling the input/output direction so that when one inputs data, the other outputs data. Input/output direction control circuits AI and B2 as control circuits, and a cipher (which latches a key for encrypting data to be sent and decrypting encrypted input data).
Decryption key latch circuit 4, input data latch circuit 5 that latches input data, and data whose direction is controlled by input/output direction control circuit A1 or B2 corresponding to the control direction of data input/output. a control signal selection circuit 3 for supplying a signal to an encryption (decryption) key latch circuit 4 and an input data latch circuit 5; A processing circuit 6, an output data latch circuit 7 that latches and outputs output data from the encryption (decryption) processing circuit 6, and predetermined time series data for encrypting or decoding data output from the output data latch circuit 7. an output data selection circuit 8 that selectively arranges the output data selection circuit 8;
an output data selection control counter circuit that sets the timing of the selection array in the input/output direction control circuit AI or B2; It is configured to include a write signal control circuit 1o that outputs a write signal to an external circuit to a write signal enable circuit 11 under the control of a counter circuit 9.

Next, before explaining the operation of the embodiment shown in FIG. 1, the basic features of the present invention will be explained first.

This data encryption processing circuit has the following four basic functions.

(1) By performing data input/output direction switching control and switching the data input section and output section, it is possible to perform data encryption processing in both directions when transmitting and receiving data.

(2> When the data input section and output section are swapped, the control associated with data input and output is also swapped in the same way to perform bidirectional control.

(3) Based on the processing end signal of the encryption (decryption) process, a clock-based count-up control is used to control the selection sequence of output data for restoring and arranging changes in the data structure based on the encryption (decryption). This is done by output, and the data is automatically output by the counter output signal.

(4) To write output data to external output,
The counter circuit (3) outputs a write signal for writing output data into an external circuit based on the clock during counting.

In this data encryption processing circuit, (1)
, By performing the processing in (2), the data encryption processing circuit, which conventionally existed independently for transmission and reception during data transmission and reception, can be configured into one circuit, and (3), By performing the processing in (4) at the same time, excess processing time caused by the CPU performing output control is eliminated, and the circuit configuration is simplified by not involving the CPU.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

First, the input/output direction is set using the output direction control signal 101, and the data input side and final output side are determined. In this embodiment, the explanation will be given assuming that the input/output direction control circuit A1 is set on the input side and the input/output direction control circuit B2 is set on the output side.

The input/output direction control signal 101 sets the input/output direction control circuit A1 to the input side, and at the same time, the input/output direction control signal 101 causes the control signal selection circuit 3 to output the latch circuit selection signal A11l and the input enable signal. A112 and
Write signal Al13 is selected as the control signal.

In order to perform encryption (decryption) processing, it is necessary to input a key first.

First, a key is input to the encryption (decryption) key latch circuit 4.

The key input is encrypted (
Select the decryption key latch circuit 4, enable the circuit with the input enable signal A112, input the keys from the data input/output A114 in order from the top, and write the write signal A.
Writing is performed by 113.

The data input/output A114 passes through the input/output direction control circuit A1, becomes a data input 134, and is written into the encryption (decryption) key latch circuit 4. After key input, input data latch circuit 5
Data is manually input to undergo encryption (decryption) processing.To input data, the input data latch circuit 5 is selected by the input circuit selection signal A11l, and the same operation as in the case of key input is performed.

After inputting the data, block encryption (decryption) processing is performed in the encryption (decryption) processing circuit 6. After the processing is completed, the encryption (decryption) processing circuit 6, the output data latch circuit 6, and the output data latch circuit 7. The processed data 139 is outputted and latched by the processed data L/Y signal 138, and latched output data 140 is outputted.

After outputting the processed data la sochi signal 138, the encryption (decryption) processing circuit 6 outputs the encryption (decoding) processing end signal 142.
is output, thereby enabling the output data selection control counter circuit 9.

After the output data selection control counter circuit 9 is enabled,
The latch performs a predetermined count-up using the clock 102, and outputs a control signal 141 for controlling the output data selection circuit 8. The predetermined count-up mentioned above is
A control signal as processing timing information necessary for block timing necessary to configure the latch output data 140 having a parallel data configuration as predetermined serial encrypted (decrypted) data, or for eliminating unnecessary bits or bits. This is done to set the timing based on the clock count, which is necessary for the 141st precept.

In this way, the output data selection circuit 8 automatically outputs the desired processing data in serial format starting from the highest order.

The output data 135 that is automatically output passes through the input/output direction control circuit B2 and is output to an external circuit.

The output data selection control counter circuit 9 sends an enable signal 14B to the write signal control circuit 10 during count-up.
is output to enable the write signal control circuit 10.

When enabled, the write signal control circuit 10 outputs an external circuit write signal 144 for writing output data to an external circuit based on the clock 102.

The output external circuit write signal 144 is converted into an input/output direction control signal 10 by the write signal enable circuit 11.
Enable processing is performed based on 1 and output. At this time, since the input/output direction control circuit B2 is on the output side, the external write signal B125 is enabled and output.

In this manner, in this embodiment, the output data selection control counter circuit 9 controls the output data selection circuit 8 to output data, and the write signal control circuit 10 and the write signal enable circuit 11 to output the external circuit write signal. Output is performed at the same time, and writing to the external circuit is performed at any time.

In this embodiment, the explanation has been made assuming that the input/output direction control circuit A1 is set to the input side and the input/output direction control circuit B2 is set to the output side, but the processing content is the same even if the input/output direction control circuit A1 is set to the input side and the input/output direction control circuit B2 is set to the output side. be. However, the input/output control direction is also reversed, and the latch circuit selection signal A111 becomes the latch circuit selection signal B121, the input enable signal A112 becomes the input B122, and the write signal A113 becomes the write signal B1.
23, the external circuit write signal B125 becomes the external circuit write signal A115.

When performing data input/output direction switching control, this data encryption processing circuit performs data encryption processing in both directions during data transmission and reception by swapping the data input and output sections. When the data input and output sections are swapped, the control associated with the data input and output can also be swapped and controlled from both directions.
This eliminates the disadvantage that conventionally, in order to send and receive data, it was necessary to have one data encryption processing circuit on the sending side and one on the receiving side.
By monitoring the processing status of the encryption (decryption) processing circuit that was performed by the PU within this circuit, and simultaneously controlling reading from the encryption processing circuit and writing to the external circuit within this circuit, This greatly eliminates the increase in system processing time due to an increase in the number of processing items of the CPU, and the complication of the circuit configuration.

〔Effect of the invention〕

As explained above, the present invention performs data encryption processing in the direction of data transmission/reception by switching the data input section and output section when performing data input/output direction switching control. In addition, when the data input section and output section are swapped, the controls associated with data input and output are also swapped and control is performed from both directions, making it possible to perform bidirectional encryption using a single data encryption processing circuit. (Decoding) processing can be performed.

Additionally, compared to conventional data encryption processing circuits, a CPU is not required for output control and write control to external circuits, which eliminates excessive processing time caused by the CPU controlling data output and writing. , furthermore, C
By not interposing the PU, the circuit configuration can be simplified and the area occupied when mounted on a device or the like can be reduced, which has the effect of downsizing the device or the like.

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional encryption processing circuit.

1... Input/output direction control circuit A, 2... Input/output direction control circuit B, 3... Control signal selection circuit, 4... Code (
Decryption key latch circuit, 5... Input data latch circuit, 6... Encryption (decryption) processing circuit, 7... Output data latch circuit, 8... Output data selection circuit, 9...
Output data selection control counter circuit, 10... Write signal control circuit, 11... Write signal enable circuit, 21... Encryption (decryption) key latch circuit, 22...
Input data latch circuit, 23... Encryption (decryption) processing circuit, 24... Output data latch circuit, 25... Output data selection circuit, 26... Output data selection control counter circuit.

Claims (1)

[Claims] 1. Two input/output direction controls, first and second, which enable data transmission and reception by controlling the input/output direction so that when one inputs data, the other outputs data. circuit and
An encryption (decryption) key latch circuit that latches a key for encrypting data to be sent and decrypting encrypted input data, an input data latch circuit that latches input data, and a data input/output circuit. control signal selection for supplying either data whose direction is controlled by the first or second input/output direction control circuit to the encryption (decryption) key latch circuit and the input data latch circuit in accordance with the control direction of the input/output direction control circuit; a circuit, an encryption (decryption) processing circuit that encrypts data to be sent and decrypts received encrypted data, and output data that latches and outputs the output data of the encryption (decryption) processing circuit. a latch circuit; an output data selection circuit for selectively arranging the data output from the output data latch circuit into predetermined time series data for encryption or decoding; and output data for setting the timing of the selection arrangement in the output data selection circuit. A selection control counter circuit, a write signal enable circuit for enabling control of writing of data sent from the first or second input/output direction control circuit to an external circuit, and a control function for the output data selection control counter circuit. and a write signal control circuit that outputs a write signal to an external circuit to the write signal enable circuit, and performs data encryption transmission and data decryption reception. 2. The data encryption processing circuit according to claim 1, wherein the encryption is block encryption.