JPH03265049A - Address conversion method - Google Patents

Abstract

PURPOSE: To delicately protect storage by allowing a special bit and a conversion index buffering mechanism provided for each segment and a lock bit concerning each lien provided for a page frame to cooperate with each other. CONSTITUTION: A hierarchical storage system is constituted to convert a virtual address supplied by CPU to a real address by using the conversion index buffering mechanism and a page frame memory. In this constitution, plural segment registers are accessed by a segment identification field among the virtual addresses supplied by CPU. Then a segment identifier and the page offset field and the byte offset field of the virtual address are connected to generate a second virtual address having more bits than the virtual address to converts it to a real address. In addition, when the special bit is set to be a prescribed value, locking is executed for every line corresponding to a lock bit provided in each line.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of the Invention The present invention relates generally to computer storage subsystems, and more particularly to storage subsystems configured in storage devices known to those skilled in the art as virtual storage. More particularly, the present invention relates to an apparatus for converting virtual addresses to real addresses and performing certain specific control functions within a storage hierarchy.

B. PRIOR ART AND ITS PROBLEMS In modern computer systems, programs execute somewhere within the system, either at some level in the storage hierarchy of cache/main memory/direct access storage (DASD) or in a distributed system network. Frequently attempts to access data or code that resides on another node. Consider how, for the most basic system, a program would have to understand what is being asked in order to have this access.

Where is the data (or code) located? Its location generally determines what kind of address should be used for access.

(For example, a 24-bit main memory address, a sector address on a disk track, or a network node address). The location also determines what kind of instruction should be used to accomplish the access (e.g. load/store/branch for main memory access, channel command word for disk access, communication for network access). protocol).

Is this data shared by other programs? Once this data is shared, no access can proceed unless a certain lock is maintained. If you do not want other programs to know about the data changes that this program is about to make, it should be directed to a store instruction or a private address.

Should the data be recoverable? If so, some journaling method must be implemented so that when needed, the data can be retrieved in the same state as before.

Assume that in such a very basic system, the program was actually required to distinguish between these at each access. Then the following will happen:

- Even in the case of simple and safe requests that occur most frequently when trying to make a program generally adaptable, in other words, for private, unrecoverable data residing in main memory. Yes, the access will be very slow.

If you fix a program to one access mode in order to make it work well, the program will not run correctly on data with different properties.

The program will be complex, large, and error-prone.

Recent systems have addressed these problems to varying degrees. For example, relocation architectures typically allow private, unrecoverable, temporary data and programs to be uniformly addressed with address sizes ranging from 16 pits to 32 bits (usually appropriate for temporary computational needs). can do. °°Indexes with appropriate relocation architecture
° When implemented using hardware, most such accesses occur at cache or main memory speeds. If this indexing hardware is not useful (
The system only accesses the relocation table structure (which is less often than once in 100 attempts). Only when the relocation table is useless (i.e. when the data is not in main memory)
゛The overhead of page absence°° occurs. Therefore,
Overhead is resolved only when truly necessary. This is the goal of good architecture and its implementation.

To maintain data beyond the scope of program execution, modern systems use software-implemented access methods instead of load/store/branch instructions.
You can request access by explicitly requesting. These access methods generally
It supports data that can be organized into a defined set of basic groups called files and files.
The ° command ° ° is commonly referred to as ° ° read/write ° ° or ° ° get / put °.

Data is not shared or unrecoverable. It may actually be stored in main memory (consisting of a buffer area). However, for each access, the program must make such an explicit read/write call.

Thus, if the access scheme is properly defined, it produces a less complex and generally applicable program than in the basic system. However, the performance of such accesses is typically inferior to that of load/store, and requires the data being accessed to be organized into appropriate base group types.

If data is to be shared or recoverable, modern systems require an explicit request to a database subsystem implemented in software. Such access is extremely slow compared to access methods for boat fishing. This is not only due to the additional functionality of locking and journal management, but also because the type of infrastructure that the subsystem supports (e.g., relationships, hierarchies) is itself more complex.

Again, the data may actually be in a buffer in main memory in a more compact structure, but each access request introduces an overhead problem.

Some systems use a technique called "checkpointing" to assist in the recovery of temporary data. In this case, if a programmer wants to write a recoverable application, he or she must deal with three different approaches. The three measures are checkpointing for computational data, explicit backup for files, and commit commands for databases.

The IBM System/38 is more advanced than most systems, at least when it comes to providing a uniform addressing structure for all data. However, this is provided at the cost that all addresses are extremely long, many accesses are extremely slow, and the architecture requires significant storage and hardware to implement;
It does not provide a uniform method for sharing or recovery.

Various techniques are known in the past for multiple computer programs executed by one or more elementary processing units to share a storage device. Storage shared by programs requires extremely large amounts of new storage capacity. Its capacity is often much larger than the actual capacity of the storage device. For example, if your system uses a 32-bit addressing scheme,
232 addressable bytes of virtual memory are available. Such virtual storage space is typically thought of as being divided into a predetermined number of regions or segments. Each segment is divided into pages of a predetermined number of lines, each line having a predetermined number of bytes. Therefore, the segment and page specifications, that is, the addresses assigned to virtual memory, can be arbitrarily specified by a program, and do not indicate actual storage locations in the main memory. Therefore, virtual segments and virtual pages are typically located anywhere throughout main memory and can be swapped in and out from external storage to main storage as needed. I do things.

Because of the variable location of segments and pages within main memory, translation from virtual addresses to true, or real, addresses is necessary. This conversion typically uses a set of address translation tables located in main memory and called page frame tables. In large virtual systems, a large number of address translation tables are used.

This can be configured in various ways. An essential feature in all such configurations is that a particular virtual address must be logically mapped to a storage location in the table that contains the real address (if any) for that virtual address.

Functionally, the operation of such an address translation table is as follows: The high order bits of a particular virtual address are used to access a particular section of said translation table. The high order bits used relate to one particular frame or segment. The lower bits are then used to check whether a particular virtual address is included therein and, if so, which real address vj reaches it. Each page table specified by a virtual frame address contains the real storage locations of all pages included in one frame. Thus: 1. If a particular frame is divided into, say, 16 pages, there will be 16 page tables for each frame, plus one page table with entries specifying a particular set of page tables. There is a separate frame table. It is understood that the above description is generalized and that there are many different ways to organize address translations using page tables and page table addressing means starting from CPU-generated virtual addresses. I want to be In later description of the preferred form of the invention, a hash address table (HAT) and an inverse page table (IPT) having a functional configuration essentially as described above will be described.
) in detail.

When actually performing address translation, regardless of the details of the overall system configuration and the use of page tables, an appropriate entry point into the page frame table is created and the page is translated using the given virtual address as an argument. A table is accessed.

The desired entry in the page table is then typically found through multiple storage accesses.

Typically, at that point it is checked whether all system protocols have been followed and, if so, the real address of the requested page is accessed from the page table. The byte portion of the virtual address, ie the °°byte offset °°, is a relative address in nature and is the same for real and hypothetical pages. Thus, once the desired real page address portion of the virtual address has been translated, the byte offset portion is concatenated with the real page address location to provide a real byte address in main memory.

As is well known in current virtual storage systems, the present invention is capable of converting recently used virtual addresses to real addresses so that virtual addresses do not have to be converted every time a storage device is accessed. The data is stored in a set of fast-accessible tables or high-speed storage devices called the registration lookaside table (DLAT) or translation lookaside buffer full (TLB). Such a table or buffer is typically a special fast-access storage device, which can be accessed even faster than the page frame table described above. This can save a computer a great deal of run time by storing frequently used virtual addresses in this table and accessing them quickly. The efficiency of the TLB address translation system is based on the fact that when a virtual page is accessed in a given program execution, the same page is subsequently accessed many times. As mentioned above, the translation from a virtual page address to a real page address depends on which line or byte is addressed, even if subsequent accesses are to different lines and bytes within the page. Regardless of the page, it is the same as far as the page is concerned.

Using TLBs can significantly reduce the translations required within the page frame table. Therefore, the performance of the entire virtual storage system can be significantly improved.

Another problem with these conventional relocation systems is handling journaling issues. That is, a copy of the data is maintained in an external storage device while the current program is running and using the data. Therefore, even if some hardware or software failure occurs, a valid copy of the original data is still available.

Such functionality has traditionally been accomplished through time-consuming and complex hardware and software, again at the cost of reduced storage performance for the required journaling functionality.

As mentioned above, virtual storage systems have been popular in computer technology for many years.

It is also well known that virtual addresses must be translated into real addresses by some relocation or address translation means.

In such address translation means, convertibility from a virtual address to a real address must be guaranteed. Although it is not possible to list all patents and papers related to this subject, the following prior art is a typical example of an address translation mechanism, and represents the prior art most closely related to the present invention.

US Pat. No. 3,828,327 to Berglund et al. shows a conventional storage control technique for expanding storage by appending high order bits to addresses. This upper bit is not part of the address specified by the program, but can be controlled by another system mode such as interrupt mode or I10 mode. II will be done. Although this patent relates to a storage expansion system, the storage expansion system is also provided with address translation hardware. U.S. Pat. No. 4,042,911 to Bourke et al. also shows a system for main memory expansion and explicitly includes address translation means.

However, these two US patents do not disclose the concept of virtual address extension, as well as the provision of special lock bits in both the TLB and page frame table.

Paper, George Radin, “The
801Minicomputer”, ACM
SI GPLAN NOTICES, Volume 17, No. 4, April 1982, pages 39-47, contains general information on experimental computers whose operating characteristics depend heavily on very fast storage subsystems. The description is shown. The relocation mechanism of the present invention may be particularly suited for such computers.

No. 4,050,084 to Bourke et al. shows a storage arrangement that includes an address relocation translator with a stack segmentation register. The special segmentation register shown in this patent is intended for storage of real addresses assigned to physical blocks within main memory, rather than storage of extended virtual addresses as used in the present invention.

U.S. Pat. No. 4,251,860 to Mitchell et al. shows a storage addressing system having a virtual addressing device to provide vast virtual address storage. This patent discloses dividing a virtual address into a segment part and an offset part. However, the segment unit and its associated segment register are used as appropriate means for performing address division, and their operation is completely different from that of the address translation mechanism of the present invention.

The system shown in U.S. Pat. No. 4,037,215 by B. frney et al. is very similar to U.S. Pat. No. 4,050,094 in that it utilizes a series of segmentation registers to specify particular blocks of real storage. . This patent also describes the use of read-only valid pits that are incorporated into special segmentation registers. These bits are quite different from the special purpose lock bits provided in the hardware of the relocation mechanism of the present invention.

US Pat. No. 4,077,059 to Gordi et al.
A hierarchical storage system is shown with special controls to facilitate journaling and copyback. This patent also shows multiple dual storage devices. This keeps current data in one storage device and notifies the other storage device of changes to facilitate subsequent journaling and copyback operations. The hardware and 1iIIItM means of this patent are quite different from the a-bit system of the present invention.

U.S. Pat. No. 4,053,948 to Hogan et al.
An address translation system is shown with special means including a counter for each entry in a registration lookaside table (DLAT).

US Pat. No. 4,218,743 to Hoffman et al. is an example of a number of patents listed below regarding the 18M System/38 relocation architecture.

This patent describes Il in a virtual memory computer system.
suggests a way to simplify the addressing handled by o. Other patents related to virtual memory system issues are No. 41
No. 70039, No. 4251860, No. 4277862
No. 4215402.

US Pat. No. 4,020,466 to Cordi et al. also shows a storage system that incorporates special means to facilitate journaling and copyback procedures. This patent has nothing to do with the lock bit control means of the present invention.

U.S. Pat. No. 3,942,155 to Law Law discloses a segmented form of a virtual storage system, but the segmentation used in this patent is different from the segmentation operation of the present invention utilized to extend virtual addresses. This is completely different.

US Pat. No. 4,215,402 is cited as an example of accessing a virtual memory conversion mechanism using various hashing methods.

SUMMARY OF THE INVENTION In accordance with the approach of the present invention, a virtual storage subsystem is provided that fully utilizes hardware and software for address translation and overall storage control functions. Data and programs in the system are recoverable, including where they are located, how long they are cataloged, whether they are shared, or private. Uniformly addressed regardless of whether it is possible or irrecoverable. This means, for example, that private, non-recoverable computational data residing in the cache can be recovered at the speed of the cache. Furthermore, even though the data is shared, access by the particular program holding the key is also done at the speed of the cache.

Thus, the configuration of the storage subsystem disclosed herein that enables such uniform line addressing or single-level storage addressing uses 32-bit virtual addresses. CPU
The 4 bits of these registers specify 16 12-bit segment registers. The contents of the selected segment register and the remaining 28 bits of the virtual address are concatenated to generate a 40-bit effective address. Therefore, it will be readily appreciated that each segment can contain up to 228 bytes of data. Note that this new 40 bit address is still a virtual address. This 40-bit address can be translated by first accessing a fast partially associative translation lookaside buffer to determine if a real address exists. If a real address does not exist, address translation is performed by referring to the page table, like other translation systems.

Another unique feature of this configuration is the locking,
A special lock bit is provided to check journaling and permissions.

Note that multiple lock bits (16 in the example embodiment) are provided in the translation lookaside buffer and page frame table for each real address. One lock bit is provided for each line within a page and is used for journaling control within the system. Access means and software means are further provided in the system, whereby these bits are accessible not only by hardware but also by software.

The main objective of the present invention is to provide a virtual storage subsystem with a very large virtual address space.

Another object of the present invention is to provide a storage subsystem that functions as a ``single level storage'' for all storage operations.

Another object of the present invention is to provide a storage subsystem that is less prone to addressing errors due to the use of incorrect translation tables.

Another object of the present invention is to provide a control mechanism that greatly facilitates journaling and associated data protection within such a virtual storage subsystem.

Another object of the invention is to provide such a control mechanism that can be used in both software and hardware.

These objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred embodiments of the invention, as illustrated in the accompanying drawings.

D. Embodiments The objects of the invention are generally achieved by the storage controller disclosed herein. This storage controller interfaces with a host CPU storage channel that implements the address translation architecture previously described in general form. The address translation architecture will be explained in more detail later. The conversion mechanism is
Contains the logic required to interface with storage devices having capacities up to 16 megabytes. The storage device may or may not be interleaved, and may be of static or dynamic type. The conversion mechanism is functionally divided into three sections (see Figure 1).

The logic of the CPU storage channel interface (CSC) 10 is implemented in section 12 of the common front end (CFE).
has. Section 12 provides the appropriate protocols from the storage channel to address translation logic 14 and storage IrIaI+ logic 16. All communications with storage channels are handled by this logic. Address translation logic translates virtual addresses received from the storage channel into real addresses used to access the storage device. The logic includes a translation lookaside buffer (TLB) configured as a two-way set-associative with 16 congruence frames. Logic is provided to automatically reload TLB entries from page tables located in main memory when necessary. Storage control logic 16 provides an interface from address translation logic 14 to storage devices. This logic also provides dynamic memory refresh control.

The present invention primarily relates to well-known computer circuits,
It relates to devices and novel combinations and functional operations of functional units, and not to their specific detailed structure. The structure, control and arrangement of such well-known circuits, devices and blocks are therefore presented in the drawings in easily understood block representations and functional diagrams showing in detail only those parts pertinent to the present invention. There is.

This is in order to avoid obscuring the invention in structural details.

The structural details will be readily apparent to those skilled in the art from the functional description alone. Additionally, the various parts of these systems have been suitably organized and functionally described to emphasize such features of the present invention. From the following description, those skilled in the art will be able to appreciate the implementation possibilities of the disclosed storage subsystem and furthermore, be able to incorporate it into any one of a variety of computer architectures.

FIG. 1 shows the aforementioned functional parts of the present address translation system. This address translation system uses VLSI technology to
It could be integrated into one logic chip.

Whether this system converts the address (handles it as a virtual address) or treats it as a real address depends on the following:
Conversion mode pit (
T bit). Each device making a request to the C5C controls the value of the conversion mode pit each time it makes a request. The T bit is taken from the appropriate field of the CPU-supplied storage access instruction. For storage accesses by I10 devices, the value of the T bit is generated by the adapter attachment. If the T bit is 1, storage addresses (instruction fetch, data load, data store) are translated. If the T bit is 0, the storage address is treated as a real address.

In the architecture disclosed herein, storage protection is not effective for storage requests that do not undergo translation.

Records of references and changes are valid for all storage devices regardless of whether a conversion occurs.

When address translation is performed, the translation operation proceeds logically as shown below.

Further, the functions of different parts may be executed in parallel instead of in a strict logical sequence as shown below.

The present address translation mechanism implements a single-level storage "addressing structure. In the preferred embodiment disclosed herein, address translation supports the following:

1. Multiple independent virtual address spaces 264 gigabytes of address space 3. On-demand paging 4. 2048-byte or 4096-byte pages 5. Storage protection 6. Shared segment for instructions and data '112
Journaling and locking of 8-byte lines 8. Real memory addressable up to 16 megabytes 9, reference and change bits per real page 10, hard for real address loads, TLB entry invalidations, and storage exception addresses There are 40 hardware-assisted storage devices each with a capacity of 256 MB.
It is treated as if it were mapped into a single 40-bit virtual address space consisting of 96 segments.

The receiver uses the upper 4 bits of the 32-bit address received from C8C to select one of the 16 segment registers, and stores the contents 1 of the selected segment register.
A 32-bit address is converted to a 40-bit (long form virtual) address by concatenating the 2 bits with the remaining 28 bits of the effective address. A translation mechanism then translates the 40-bit virtual address to a real address for storage access. As can be easily seen, it is also possible to change the size of the virtual address with only slight changes to the hardware.

Addressable storage capacity is always only 4 gigabytes. In other words, 16 segment registers each have a capacity of 256 MB.
Six segments can be specified. Thus, the operating system can create multiple independent virtual address spaces by loading appropriate values into the segment registers. In limited cases, it might be possible to create 256 completely independent 4 gigabyte address spaces in this way, but M&a few segments (such as core code) are shared by multiple address spaces. More likely.

Storage protection similar to the IBM System/370 is provided in 2 byte or 4 byte pages. 25
Protection key specified independently for each 6 MB segment (equivalent to the key in the S/370 PSW)
Storage and retrieval protection is achieved by: Note that by loading the same value (segment identifier) into different segment registers, it becomes possible to share segments between different tasks (this is particularly useful in the case of inter-task communication).

Support for persistent storage classes is provided by a set of lock bits associated with each virtual page. This lock bit effectively extends the granularity of storage protection to 2 or 12 pages of storage.
8 bytes, or 256 bytes for 4 pages), thus allowing the operating system to detect changes to persistent variables and automatically journal them. The persistent storage class here means one whose contents can be permanently stored, for example, in a disk file storage device.

The following terms are used herein and are defined here for clarity and convenience.

If byte index 2 is a byte page, O to 2047 to identify one byte within the page or page frame.
(11 bits) [O to 4095 (12 bits) for 4 byte pages]. The byte index is the lower 11 bits [12 bits] of the effective address.
taken from.

change bit Bits associated with each page frame.

Set to °1°° whenever a storage reference (write only) is successful for that frame.

Effective Address A 32-bit storage channel address generated by a device on the storage channel. This address is used by the post CPU when fetching instructions, loading data, or storing data.
It can be generated by Also, like a DMA address,
It can also be generated by a 10 device on a storage channel.

A 128-byte portion of a page with a line boundary of 128 bytes, which is the storage capacity that can be limited by one lock bit.

Lock Bit One of 16 bits associated with each page of a persistent storage segment. Each lock bit is associated with one line of storage. The values of the transaction ID1 write bit and the lock bit are combined to determine whether storage access requests are permitted or prohibited in the persistent storage segment for a line.

A storage unit of 2048 bytes [or 4096 bytes] separated by page 2048 byte [or 4096 byte] boundaries. ``Bage'' properly refers to virtual memory, while ``page frame'' refers to real memory, although historically ``page'' has been used for both virtual and real memory. .

A storage unit of 2048 bytes [or 4096 bytes] separated by page frame 2048 byte [or 4096 byte] boundaries. The page can be stored in a page frame or on external storage (
i.e. on the disk).

A page table is a combination of entries from the hash anchor table and the reverse page table in main memory, and is used to convert a virtual address to a corresponding real address (herein also referred to as HAT/IPT).

Protection Key A one-bit value in each segment register that indicates whether the currently executing process can access the data in a given segment. This protection key is functionally similar to the IBM System/370 PSW key, but
It is applied individually to each segment rather than globally to all addressable storage.

As a result of the real address translation operation, the real page index (1
0 bit to 13 bits) and the lower 11 of the effective address
A concatenation of bits [or 12 bits] (real page index 11-byte index).

Real page index O to 81 for identifying page frames in real memory
Numeric value in the range 92 (13 bits). By reducing this value to 10 bits, the maximum amount of real storage may be limited to 2M bytes in 2 byte pages.

Reference Bits Bits associated with each page frame. Set to ``1'' whenever a storage reference (read or write) is successful for that frame.

Segment ID A numeric value ranging from 0 to 4095 (12 bits) to identify a 256 MB virtual storage segment. Concatenate the segment ID and virtual page index to create 4
Specifies one page of 0-bit virtual address space.

Storage Key A two-bit value within each TLB entry that identifies the level of protection associated with a particular page.

This key is functionally similar to the storage keys associated with each System/370 page.

TLB Translation index buffer. The TLB is hardware that contains a virtual-to-real mapping (although only a portion of this mapping may be included in the TLB at any given time). Besides this mapping, each TLB entry contains other information about the page associated with it, such as the translation TD, storage key, and lock bits.

Transaction ID O to 255 to identify the "owner" of the set of lock bits currently loaded in the TLB entry
(8 bits).

A 40-bit address value formed within the present address translation mechanism by concatenating the virtual address segment ID and the lower 28 bits of the effective address. (i.e. segment ID
11 virtual page index 11 byte index)
.

If virtual page index 2 is a byte page, a number in the range O to 131072 (17 bits) to identify a page within the virtual memory segment [0 to 65536 (16 bits) if 4 is a byte page].

The virtual page index is bits 4-2 of the effective address.
0[4-19].

Symbol 11 represents connection.

The hardware required to support the present address translation mechanism is described below. Note that the field vergence can also be changed in some implementations.

The TLB consists of an arbitrary number of entries, each of which controls the translation of a page's virtual address to its real address.

The detailed configuration of the TLB depends on the implementation. Two implementations are possible. Content addressable storage (addressed by segment IDI virtual page index and containing one entry per real storage frame)
CAM). The index (ordinal number) of a CAM entry is equal to the real page index. The set-associative TLBo real page index that can be addressed by the numerical value consisting of the lower bits of the virtual page index is T.
Contained in one field of the LB entry.

The only constraint on the shape of the TLB is that the non-CAM implementation must be at least two-way set-associative. Each TLB entry is individually read from and written to by the CPU using rOR and IOW instructions. A TLB entry includes the fields shown below.

A 32-bit input effective address (from the CPU or I10 device) can be expanded to a 40-bit virtual address by first concatenating the segment identifier to the effective address. The virtual address is then provided to translation hardware for translation to an equivalent real address. Virtual addresses are translated to real addresses by the process described below.

The upper 4 bits of the input valid address are used to search the segment table and select one of the 16 segments. The 12-bit segment identifier, special segment bits, and key bits are obtained from the selected segment register. The 12-bit segment identifier is used for virtual address generation. The special segment bits and key bits are: It is used for access validation indicated by .FIG. 2 shows the format of the segment table.

The 12-bit segment identifier is concatenated with bits 4 through 31 of the input effective address to produce a 40-bit virtual address. If the 2nd page of the valid address is a page, the lower 11 bits, or if the 4th page is a page, the lower 11 bits are
Twelve bits are used as the byte address for the selected real page. These bits are not changed by the conversion process. The remaining twenty-nine (28) bits of the virtual address are then provided to the translation hardware. FIG. 3 illustrates the generation of a virtual address using a segment identifier and a storage device effective address.

The address translation system presented herein utilizes a translation lookaside buffer (TLB) that includes the translation of the last used virtual address (32 in this example). When a new virtual address is given to the TLB for translation,
TLB entries are updated from the main memory page table using hardware. FIG. 4 shows a simplified data flow of the conversion hardware, and FIG. 5 shows the format of each TLB.

The system utilizes two TLBs (2-way set-associative with 16 congruence frames) with 16 entries per ITLB. The lower 4 bits of the virtual page index are simultaneously used in both TLs.
Used to address B. The address tag entry in each TLB consists of a segment identifier concatenated with the remaining bits of the virtual page index (25 bits for page 2, 24 bits for page 4);
be compared. If either of the two comparisons are equal and that T
If an LB entry is valid (indicated by a valid bit), the associated TLB contains translation information for the given virtual address.

The real page number field (RPN) in the selected TLB entry contains the number of the real page located in main memory.

A real page number is mapped to a given virtual address. If this is not a special segment, the key bit from the TLB entry and the key bit from the segment register are used to check for a storage protection violation before access is allowed. If this is a special segment, as indicated by the special bits in the segment register, lock bit processing is performed before access is allowed. Storage device protection mechanisms, as well as special segment processing,
I'll explain later. If access is granted, main memory is accessed and the reference and modification bits associated with the page are updated. The reference and modification bit sets are also discussed below.

If the comparison of the two TLBs does not yield a match, the address translation logic attempts to reload the missing TLB entry from the page table entry in main memory. The main memory page table resides in real memory and logically consists of two parts: the hash anchor table (HAT) and the inverse page table (IPT). HAT can map any virtual address to any real page by hashing.

The inverse page table (IPT) specifies the virtual address (if any) associated with each real page frame.

The IPT is organized as an array of entries indexed by real page number, each entry containing its associated segment ID and virtual page number.

Since the IPT can be indexed by the real page number, it is very easy to determine the virtual address for a given real address. Efficiently determining the real address for a given virtual address requires mapping the virtual address to an anchor point by passing and chaining entries to resolve hash collisions.

This will be readily understood by those skilled in the art.

Hash Anchor Table (HAT) is logically IP
It is separated from T (although it is physically integrated into IPT for reasons of hardware efficiency). 6th
As shown in the figure, the hash function converts the virtual address to HAT
This entry specifies the first entry in a chain of IPT entries (real pages) with the same HAT index.

When searching a chain of IPT entries for a virtual address match, either one obtains an IPT index for the desired virtual address (and thus a real address), or no match is found (the page is not mapped).
The search ends. In this embodiment, there is one HAT and IPT entry for each page of real storage.

Conversion from a virtual address to a real address is accomplished by first exclusively ORing selected low order bits of the effective address with bits from the segment identifier. This "hashed" address is used for indexing to the HAT.

The selected HAT entry is a pointer to the beginning of the list of IPT entries to be searched for a given virtual address. Entries in the list of IPT entries to be searched are linked by pointers within each entry that specify the next IPT entry to be searched. A flag bit in the rPT entry is used to indicate the end of the search chain. Note that since hashing typically generates the same HAT address for several different effective addresses, the IPT chain to be searched will contain several virtual address entries.

For reasons of hardware efficiency, HAT and I
The PTs are combined into one structure that can be addressed with one indexing structure.

There is one entry in the combined HAT and IPT for each page of real storage.

For example, 1 Mbyte of real storage made up of 2 byte pages requires 512 entries, and 512 byte real storage made up of 4 byte pages requires 128 entries. The format of the combined HAT and rPT entries is shown in FIG. The HAT/TPT has 16 bytes for each entry, starting at an address location that is a multiple of the table size.

The first word of each entry contains an address tag.

An address tag is created by concatenating a segment identifier and a virtual page index. Note that for pages 2, the address tag is 29 bits, and for pages 4, it is 28 bits.

If page size 4 were used, a 28-bit address tag would be stored in bits 3 through 30. Bit 2 is reserved. The first word is also
Contains a 2-bit key. The 2-bit key is used for storage protection, which will be explained later.

The second word contains a HAT pointer, an IPT pointer, and a valid bit for each pointer.

The use of pointers will be explained later.

The third word contains the write protection, lock bit, and TID for the special segment. The use of these fields will also be explained later.

The fourth word is not used to reload the TLB and is reserved for future use.

The HAT/IPT base address is a field in the translation control register (described later) and is used to calculate the starting address of the main memory page table. H
The value contained in the AT/rPT base address can be multiplied by the amount shown in Table 1, depending on the storage device and the size of the page, thereby obtaining the starting address of the main memory page table. Table 1 also shows the HAT/IPT size for each storage size and page size.

4 HAT Address Generation As mentioned above, the HAT index is calculated by exclusive-ORing selected bits from the segment identifier and bits from the effective address. The number of bits used is
Choose one of the n entries with result index HAT/IPT. This passing operation is shown in FIG. Table 2 lists the bits used for HAT index generation. The storage address of the selected HAT entry is: HAT/IPT base address + HAT index 1
Calculated as 10100.

The free bit is checked to determine if the selected HAT entry has been accessed and the IPT search chain is free. If the free bit is 1, there is no page mapped to the given virtual address, and as explained below, page not present.

can be reported. If the free bit is O, an entry exists in the IPT search chain and the entry in the IPT is searched. At that time, the HAT of the selected HAT entry
A pointer field is used as a pointer to the start of the IPT search chain.

0 A previously accessed HAT pointer can be used as a starting index into the IPT. The storage address of the first IPT entry is calculated as HAT/IPT base address + HAT pointer + 10000.

The first entry in the IPT is addressed,
A comparison is made between that address tag and a given virtual address. If the two match, it means that the real page assigned to the virtual address has been found, and the absent TLB entry can be reloaded. Reloading of TLB entries will be explained later. If the two do not match, ①Access the PT pointer and continue the IPT search. IPT pointer is HAT/IPT base address + HAT pointer! 10
Calculated as 100. The IPT pointer is then accessed and the final bit is checked to determine if there are additional entries in the IPT search chain. If the final bit is O, additional entries exist and the search process continues. If the final bit is 1, there are no additional IPT entries to be searched and a "page not present" is reported.

If there are additional IPT entries to be searched,
The address of the next IPT entry for searching is: HAT/rPT base address + HAT pointer 110
Calculated as 000. This address is used to access the next entry in the IPT and a comparison is made between the address tag contained in the selected entry and the given virtual address. If they match, the real page assigned to the virtual address is found and the absent TLB entry can be reloaded. If they do not match, the pointer to the next entry to be searched is accessed and the search process continues. The address of the pointer to the next entry is HAT/
Calculated as IPT base address + IPT pointer + 10100. This word is then accessed and the final bit is checked to determine if there are additional entries in the IPT search chain. If the final bit is 1, there are no additional IPT entries to be searched and a ``Bage Missing'' can be reported. If the final bit is O, additional entries exist and the search process continues.

The current IPT pointer is used until the address tag of the IPT entry matches the given virtual address or no match is found and the final bit indicates that there are no more entries in the search chain. Then, subsequent entries are accessed through the above-described processing.

The following description summarizes the steps required to convert a virtual address to an index of an IPT entry (and thus a corresponding real address).

(1) Select the lower 13 bits of the virtual page number.

This is bits 1-19 of the effective address if a 4-byte page is used, and bits 8-20 if a 2-byte page is used.

(2) Select the 12-bit contents of the segment register that can be specified by bits 0 to 3 of the effective address. A 13-bit field is formed by concatenating the ゛°0°゛ bit to the left end.

(3) Exclusive-OR the two 13-bit fields from steps (1) and (2) to form a 13-bit hash anchor table entry number.

(4) Shift the value in step (3) to the left by 4 bits. This is the IP that physically contains the desired HAT entry.
Forms the byte offset of the start of the T entry.

(5) Calculate the address of the HAT/IPT entry.

This is done by adding the result of step (4) and the starting address of the IPT. This addition may be replaced by an OR or concatenation if the PT is constrained to start at a power-of-two byte boundary.

(6) Check free IPT chains. Check the 'E'("Empty") bit of the HAT/IPT entry.

If E=1, the IPT chain is empty (HAT pointer is invalid): the search is unsuccessful; the virtual page is not mapped.

(7) If the IPT chain is not free, select a HAT pointer from the addressed HAT/IPT entry. This 13-bit value is the first IPT in the chain of entries with the same hash result [step (3)].
is the index of the entry.

(8) Shift the IPT index value to the left by 4 bits. This should check virtual address matching.
Forms the byte offset of the start of the PT entry.

(9) Calculate the address of the IPT entry. this is,
This is done by adding the result of step (8) and the start address of the IPT. This addition may be replaced by an OR or concatenation if the IPT is constrained to start at a power-of-two byte boundary.

(10) Comparison of virtual addresses. IPT segment ID
Virtual page number from entry (28 bit or 29
The contents of the segment register specified by the effective address [step (2)] are compared with the virtual page number of the effective address.

(11) If there is a match, the search ends successfully. This entry corresponds to the desired virtual address. Its index number is equal to the requested real page number.

(12) If there is no match, check the end of the chain. IP
Check the L II (IT Last'') bit of the T entry. If L=1, it is the last IPT entry in this chain. The search was unsuccessful and the virtual page is not mapped.

(13) If it is not the end of the chain, I
Select the PT pointer field. This 13-bit value is the index of the next IPT entry to be examined.

(14) Proceed to step (8).

TLB Reload Absent TLB entries are reloaded when an IPT entry with an address tag field matching a given virtual address is found. Reloading involves selecting the least recently used TLB entry for the congruence frame of absent virtual addresses and assigning the selected entry a given virtual address tag field, corresponding real page number and key bits. to load,
Consists of. If this is a special segment as indicated by the special bit in the segment register, the write bit, TIDl and lock bit are also reloaded.

Hardware is used to determine the least recently used TLB entry in each confluence frame. Since the lower bits of the virtual address determine the congruence, all that remains is to determine which TLB should have replaced the selected entry.

One of the two TLBs is then selected based on which TLB had the longest unreferenced entry in a given congruence flask.

Once the least recently used TLB entry for a given confluence frame is determined, the selected TLB entry can be reloaded.

Address tag fields and key pits are reloaded from IPT entries contained in main memory. The address of this entry has been pre-calculated in the IPT search process. IPT calculated during the search process
Since the index is equal to the real page number, this value is used to reload the TLB's real page number field.

If this is a special segment, as indicated by the special bit in the segment register, the TID and lock bits are also reloaded. The TID and lock bits are reloaded by accessing the third word of the selected IPT entry.

Storage Access Control The present address translation mechanism provides two access control mechanisms. The first mechanism is for non-special segments and provides read/write protection for each page of real storage. The second mechanism is dedicated to special segments and is used to support persistent data types. These access control mechanisms apply only to converted accesses. If the violation is detected by either mechanism, the storage access is terminated and
Exceptions are reported as described below.

Storage device protection processing Storage device protection processing applies only to non-special segments.

Once a virtual address is associated with a real address by the TLB, the requested access can be verified to ensure proper access privileges. This feature allows each page to be marked as No Access, Read Only, or Read/
Can be marked as written.

Access control is for 1 in the selected segment register.
bit protection key, 2-bit key in TLB entry,
and whether the access is a load or store operation. Access is controlled as shown in Table 3.

Key in TLB 00 1 0 1 Protection key in segment register Table 3 Protection key processing Access Load permission prohibition permission permission permission permission permission permission storage permission prohibition permission prohibition permission permission prohibition prohibition If access is not allowed, the conversion is terminated. A protection exception is reported to the CPU.

Lock Bit Processing Lock bit processing applies only to special segments indicated by special bits in the selected segment register. Special segments are used to support persistent data. Lockbit processing allows the operating system to automatically monitor changes to persistent variables, record changes in a journal, generate shadow pages, and perform other tasks to ensure database consistency. It is possible to execute. The lock bit also refines the unit of protection from the page size (2 bytes or 4 bytes) to 128 byte or 256 byte lines by storage device protection function. In the case of 2 pages, a protection unit of 128 bytes is realized, and 4
In the case of a page, a protection unit of 256 bytes can be realized. If the page is 2, bits [21:2 of the effective address]
4] selects the lock pit of each line,
If page 4, bits [20:23 of the effective address
] selects individual line lock pits.

Access control consists of a 1-bit write key in the selected TLB entry, a lock bit value for the selected line,
It is concerned with TrD comparison and whether the access is a load or store operation.

Access is controlled as shown in Table 4.

Data storage exceptions are used to report lock bit violations. This violation does not necessarily represent an error;
It may simply indicate that the newly modified line should be processed by the operating system.

Reference and modification bits are provided for each page of real storage. These bits reside in an array external to the present address translation mechanism and are updated on demand for each storage access. A reference bit is set to 1 when the corresponding real page is accessed for reading or writing. A modified bit is set when the corresponding page is written.

Reference and modification bits can be accessed by I10 read instructions (10R) and I10 write instructions (IOW) from the associated CPU. The reference and modification bits for each page of real storage begin at the I10 address specified by the I10 base address register plus X'1000''. The I10 address is given by the following equation (d).

I10 address = address specified by the base address register + show.

Data' that can be transferred by accessing the reference bit and change bit is defined as follows.

Bit O: 29 zero.

bit 30 Reference bit. The corresponding real page is access to read or write It is set to 1 when

bit 31 change bit. The corresponding real page is When accessed for logging, l is set to

Reference bits and modified bits are not initialized by hardware. They are initialized and cleared by system software IOW instructions. Referenced and modified bits can be set by running a program that sets or clears them, so a read followed by a write that clears or sets the referenced and modified bits does not necessarily mean that it is written. There is no need to read the same data.

Control register storage configuration, page table addresses, and I1
There are several control registers used to define the 0-base address. These registers are initialized (loaded) by I10 read (IOR) and I10 write (IOW) instructions from the CPU. Their configuration and format are shown in FIGS. 9 to 18. These registers can only be accessed in supervisory program state.

The I10 base address register specifies which 64 of I10 addresses the block is assigned to the translation system. The I10 base address is 65536 (X'
10000°). The format of the I10 base address register is shown in FIG.

The I10 base address register is defined as follows.

Bit O: 23 Reserved.

Bit 24:31 110 base address. This 8 pits The value of 4 blocks of bytes are converted by the system is assigned to the system. Ru. In other words, these 8 bits are changed. ■/ recognized by the conversion system The most significant 8 bits of the 0 address Ru.

”The RAM specification register indicates the RAM size and
It specifies the starting address, refresh rate, and whether parity checking or error correction codes (FCC) are used. FCC and parity checking techniques do not form part of the present invention and are well known and will not be further described. The format of the RAM designation register is shown in FIG.

The RAM specification register is defined as follows.

Bit 0:10 Reserved.

Bits 10:18 Refresh rate. This 9-bit quantity determines the refresh cycle rate. The refresh cycle rate is equal to the value contained in bits [10:18] multiplied by the frequency of the CPU clock. Zero refresh rate 20:
27 RAM start address. This 8-bit field defines the starting address of RAM for translation and non-translation accesses. For translated accesses, RAM is selected if the translated address falls within the range specified by RAM start address and RAM size. For untranslated accesses, the RAM starting address is used along with the RAM size to determine whether the address falls within the address range specified for this storage controller. The RAM starting address is defined as a binary multiple of the RAM size and is calculated by multiplying the bits shown in Table 5 by the value specified by the RAM size.

de-energizes refresh. The refresh rate value can be calculated by dividing the desired memory refresh rate by the frequency of the CPU clock. For example, in a system with dynamic memory that requires 128 rows to be refreshed every 2 milliseconds, the refresh interval per row is 12872 milliseconds or 15.6 microseconds. If the CPU clock is 200 nanoseconds, the desired refresh rate value is 15.6
Microsecond/200 nanosecond, Sunawachi, 78 (X'04E'). This requires loading X"04E' into the refresh rate.

Refresh rate is FOR sequence initialized to X’01A” as part of the You can set it.

- For example, if a storage device size of 256 is specified, 6
One of the four 256 byte boundaries is bit[20:2
5] as the RAM start address. If bits[20:25] are 011101, the RAM
Starting address x'o.

740000''. If a RAM size of 1 Mbyte is specified, then one of the 16 1 Mbyte boundaries is addressed by bits [20:23] of the RAM! start address. If bits [20:23] Then, the RAM start address is x'.

0900000'.

Bit 28:31 RAM size. This 4-bit file The RA connected to this conversion system Define the size of M. RAM size is 64 bytes as shown in Table 6 below. You can choose between Wear.

ROS Specification Register The ROS specification register defines the RO3 starting address, ROS size, and whether parity is provided by the ROS.

ROS is accessible in both translation and non-translation modes. The format of the ROS designation register is shown in FIG.

The RO3 designation register is defined as follows.

Bit O: 19 Reserved.

Bit 20: 27 ROS start address. This 8bitsoff The yield is based on the converted access and In both cases of untranslated access Specifies the starting address of ROS in Ru. For converted access, the The exchanged address is the RO5 start address. range specified by space and ROS size. If it is within the range, ROS is selected. Ru. In case of access that cannot be converted, table bit 28=31 RAM size ooooo.

No RAM 001 Not O111 at 64 000 001 010 011 100 101 110 1111 to 128 to 256 12K M M M M 6M RO3 start address along with ROS size address is used to control this storage. Within the address range specified for the device Determine whether it is included. R The start address of the OS is the ROS size. Defined as a binary multiple and shown in Table 7 Values that can be specified using bits and ROS size It is calculated by multiplying by

Ladle ladle u! J! For example, if a ROS size of 64 is specified, then 256
One of the 64 byte boundaries is bit[20:27]
is specified as the RO3 start address. If bits [20:27] are 110010, the ROS start address LtX'0OC80000°.

Bit 28:31 ROS size. This 4-bit file RO3 is connected to the conversion system. Specify the size of The ROS size is 64 bytes as shown in Table 8 below You can select from up to 64MB. Ru. If RO3 is not used, Set [28:31] to zero. It will be done.

Ward Ward table Bit 28:31 ooooo.

001 to 111 000 001 010 011 100 101 110 1111 ROS Size RO8 None 64 to 128 to 256 to 12K M M M M M 6M Translation Control Register The Translation Ig Register (TCR) is set when the TLB is successfully reloaded by the hardware. whether interrupts are generated, whether parity is used for referenced and modified arrays, and the size of each page (2 bytes or 4 bytes).
bytes), and main memory page tables (HAT and I
(a combination of PTs).

The format of the conversion control register is shown in FIG.

The conversion control register can be defined as follows.

Bit O: 20 It's fully booked.

Bit 21 Enable interrupt when TLB reload is successful.

This bit can be used to report that the TLB was successfully reloaded by the hardware. If set to 1, the TLB reload pit (bit 22) of the SER is set to 1 when an exception reply is generated due to successful reloading of the TLB by the hardware. If this bit is set to zero, successful reloading of TLB entries by hardware is not reported. This function can be used to evaluate TLB performance using software.

Bit 22 Parity for reference and change arrays. child external references and Is parity used for changing arrays? Indicate whether or not. This bit is set to 1. referenced and modified array. Use parity. If this bit is set to zero, the reference and Do not use parity for changing arrays.

Bit 23 Page size. 2 to the byte page Use the value O, and the value 4 for the byte page. 1 is used.

Bits 24:31 HAT/IPT base address. This 8-bit field is used to specify the starting address of the HAT/IPT entry in main memory. By multiplying the value contained in this field by a constant determined by the real storage size and page size, the starting address of the HAT/IPT entry can be determined. If the page size is 2 bytes, the base address can be specified by bits [24:31], and if the page size is 4 bytes, the base address can be specified by bits [25:31]. Constants for each storage size and page size are listed in Table 1.

The storage exception register (SER) is used to report errors in the conversion process and system errors that occur in storage accesses.

A separate bit is assigned for each error condition detected by the conversion system. If multiple errors occur, each error can be reported by setting the appropriate bit. Bits set by previous errors are not reset by subsequent errors.

SER is initialized to zero by the FOR sequence. Once an exception is reported, system software clears the SER after the exception has been handled. The format of the storage exception register is shown in FIG.

The storage exception register is defined as follows.

Bit O: 21 Reserved.

Bit 22 TLB reload successful. This bit is Interrupts due to TLB reload success are allowed. If the reload is successful when Then, it can be set to l.

Bit 23 Reference and Modify Array Parity Ra. Parity on reference and change arrays This bit is set when an error is detected. bit is set to 1.

bit 24 Attempt to write to RO3. ROS address empty An attempt is made to write to an address included between This bit is set to 1 if I can finish it.

bit 25 IPT specification error. In IPT search chain This bit is displayed when an infinite loop is detected. The cut can be set to 1. infinite loop For example, the system software The value of the IPT pointer is incorrect due to an error. is specified, and as a result, the IPT point is the previous element in the current IPT search chain. This occurs when an entry is specified.

bit 26 External device exception. R3C other than ROMP If the above device causes an exception This bit is set to 1.

bit 27 Multiple exceptions. in the storage exception register 2 or more before the exception indicator is cleared Exception (IPT specification error, page failure) location, designation, protection, or data) This bit is set to 1 if the I can do it.

This bit typically indicates that the system software was unable to handle the exception. However, this bit can also be set if an exception is caused by a load multiple (LM) or store multiple (STM) instruction. This is because the LM or 37M instruction attempts to store or load all registers that can be specified by the 7 instructions before the instruction is aborted by an exception.

bit 28 Page not available. Which TLB entry and and main memory page table entries are also temporarily does not include translations for virtual addresses. If the conversion is terminated due to The bit is set to 1.

Bit 29 specified. This bit can be set to 1 if the translation is completed because two TLB entries were found for the same virtual address.

bit 30 protection. Storage for non-special segments Storage device access is prohibited during device protection processing. I changed my mind because I found out that it was stopped. This bit is set to 1 when the conversion is completed. is set to

bit 31 data. Tiger for special segment Transaction ID/lock bit processing , storage access is prohibited. The conversion ended because it was found that This bit is set to 1 if It will be done.

The storage exception address register (SEAR)
Contains the valid storage address that caused the exception reported by the storage exception register (SER) for data loads and store requests from . If the exception is caused by a ROMP instruction fetch or an external device, 5EAR is not loaded.

The format of the storage device exception address register is shown in FIG.

The storage exception address register is defined as follows.

Bit O:31 Storage Exception Address. The 32-bit valid storage address that caused the exception reported by SER. In case of multiple errors (bit 27 of SER is set to 1), the address contained in 5EAR is the address of the oldest exception.

The translated real address register (TRAR) contains the real storage address determined by the real address calculation operation. The real address calculation function determines whether the virtual address has been mapped to the real memory at the present time, and if the virtual address has been mapped, determines the corresponding real address. The real address calculation function will be explained later. The format of the real address register to be converted is shown in FIG.

The real address translation register is defined as follows.

Bit O Invalid bit. This bit failed to convert If so, it can be set to 1 and the conversion is successful. If successful, it can be set to 0.

bit 1 near zero. This 7-bit field is always It is zero.

Bits 8:31 Real memory address. This 24-bit field contains the real storage address. This real storage address is mapped to a given virtual address if the translation is successful. This field is set to zero if the conversion fails.

The transaction identification register (TID) contains an 8-bit identifier of the task that is currently defined as the ``owner'' of the special segment. Once the segment defined by the special bit in the selected segment register is defined as a special segment, lock bit processing as described in Section 6.2 is applied to storage accesses. Lock bit processing uses the value contained in the TID and the TL
The TID entry in B is compared to determine whether storage access is allowed. The format of the transaction identification register is shown in 16th rgJ.

The transaction identification register is defined as follows.

Bit O: 23 Reserved.

Bit 24:31 Transaction identifier. This 8 bits value specifies the owner of the special segment. Set.

The 16 segment registers contain segment identifiers, special bits, and key bits. A 12-bit segment identifier specifies one of 4096 256 Mbyte virtual storage segments. The special bit indicates that it is a special segment and lock bit processing is applied. The keypit indicates the level of access authority associated with the currently executing task regarding storage access within a given segment. The format of each segment register is shown in FIG.

The contents of each segment register are defined as follows.

Bit 0:17 It's fully booked.

Bit 18:29 Segment identifier. This 12 bit The value is 4096 256MB temporary Specify one of the memory segments do.

Bit 30 Special bit. For special segments, this bit can be set to 1; for non-special segments, this bit is set to zero.

bit 31 Keepit. This bit Regarding access within the Permission level for the task being executed Determine the Storage device access control Using this bit for It is shown in Section 6.2.

In the disclosed embodiment, each of the two TLBs is one
It has 6 entries. These entries provide the translation and control information needed to translate virtual addresses to real addresses. Additionally, each TLB entry also contains additional information used for storage access control. Since the contents of the TLB can be automatically updated from the main memory page table by hardware, when a read follows a TLB entry write, it is not necessarily necessary to read the same data that was written. Furthermore, changing the TLB entry may cause unpredictable results, since changing the TLB entry will break the correspondence between real and virtual addresses. Accessing the contents of the TLB is for diagnostic purposes only and should only be done in non-translation mode. Writing to a TLB entry in non-translation mode, with all other translation accesses prohibited, will be followed by a read and will read the same data that was written.

Each TLB entry is logically a 66-bit variable (excluding reserved bits) that includes a 25-bit address tag, a 13-bit real page number, a valid bit, a 2-bit key, a write bit, and an 8-bit transaction ID. ,
and 16 lock bits. Each TLB
Entries are divided into three individually addressable fields. The format of each TLB field is described below.

” The TLB address tag field contains the upper 25 bits of the segment identifier 11 page index if page 2 is present, and the upper 24 bits of the segment identifier 11 page index if page 4 is the address tag field of each TLB entry. The format is shown in Figure 18.1.

The contents of each TLB address tag field are defined as follows.

Bit o: 2 Reserved.

Bit 3:27 address tag. This field is 2 If the page is segment identifier 1 1Top 25 virtual page indexes If the page contains bits and there are 4 pages, then Contains the upper 24 bits of . page 4 , the address tag is bit [3: 26].

Bit 28:31 Reserved.

The ``'TLB Real Page Number, Valid Bit (V), and Key Bit (Key)'' field contains the real page number assigned to the virtual address contained in the address tag field of the TLB entry. This field further includes a valid bit indicating that the given TLB entry contains valid information, and a keypit for the required access privileges for the given page. The format of this field for each TLB entry is shown in Figure 18.2.

The contents of the real page number, valid, and key bit fields can be defined as follows.

Bit O: 15 Reserved.

Bit 16:28 Actual page number. This 13 bit fee out of 8192 real pages. Specify one. Less than 8192 If you use pages that don't have them, Required to address the page in Only the lowest bits can be used.

bit 29 Valid bit. selected TLB entry This bit if the file contains valid information. is 1. TLB entry is invalid This bit is 0 if information is included.

Bit 30:31 Keepit. This 2-bit field defines access privileges for each page. to justify Regarding the use of the key pit It is shown in Section 6.1.

”　TL　B write bit, transaction ID.

and the lockpid field contains the write bit, transaction ID, and lock bit assigned to the virtual address contained in the address tag field of the TLB entry if the TLB entry is for a special segment. The format of this field for each TLB entry is shown in Figure 18.3.

TLB write bit, transaction ID.

The contents of each of the and lock bit fields are defined as follows.

Bit o: 6 It's fully booked.

bit 7 Write bit. This bit is set to related to each page in case of Define access privileges. rock bit The use of this bit in The details are shown in Section 6.2.

Bit 8:14 Transaction identifier. This 8 bits field is in a special segment. The tag that currently owns the selected page Define the screen. For lock bit processing About the use of these bits in was explained earlier.

bit 15:31 0 tsukbitsuto. This 16 bit fee 2K for special segments. or each "line" in the page in 4. Define access privileges for 1 If the line is 2 and the page is 128 bars 256 bytes for 4 pages It is. in lock bit processing 6° for the use of these bits This will be explained in Section 2.

The conversion mechanism provides hardware support for frequently requested conversion functions. This hardware allows selective invalidation of TLB entries and performs a "real address load" function similar to that in the IBM System/370 family of computers.

When changing the virtual-to-real address mapping, it is necessary for the system software to synchronize the contents of the TLB with the contents of the page table in main memory. Both TLB and page frame table entries must be removed (invalidated) to prevent obsolete mapping information from being used in subsequent transformations.

This system provides three functions to support synchronization of the contents of page tables in main memory and TLB entries. These functions can be used to invalidate the entire contents of the TLB or only selected TLB entries. 6 of the I10 addresses recognized by the system
4 to a specific I10 address within the byte block
These functions are called by a write instruction (IOW). Address assignments for each of these functions are provided to the system as needed.

The entire TLB invalidation function invalidates all TLB entries. This function forces the contents of the TLB to be updated in the page table in main memory in preparation for subsequent conversions.

An I10 write to an address related to this function is
Invalidate all B entries. Data transferred with the I10 write command is not used.

° The TLB entry invalidation function in the specified segment invalidates all TLB entries having the specified segment identifier. Subsequent translations using this segment identifier update the contents of the TLB from the page table in main memory.

An I10 write to the address associated with this function invalidates the TLB entry with the specified segment identifier. Bit [0: of data transferred by I10 write command]
3] is used to select the segment identifier.

All TLB entries containing this segment identifier are invalidated. Subsequent translations with valid addresses in the invalidated segment cause the contents of the TLB to be updated from the page table in main memory.

Invalidating a TLB Entry for a Specified Effective Address The seed function invalidates a TLB entry with a specified valid address.

Subsequent translations with effective addresses within the page containing the specified effective address update the contents of the TLB from the page table in main memory.

I10! to the address related to this feature! The entry invalidates the TLB entry with the specified valid address. I
10 Bits of data transferred by write command [0:31
] is used as a valid address. A normal translation process is applied using the contents of the segment registers included in the present address translation mechanism.

The ``Real Address Computation'' function is used by system software to determine whether a given virtual address is currently mapped to real memory and, if so, which real address is assigned to that virtual address. determine whether

If a virtual address is not mapped, its use will result in a page fault; this information is important for system routines that run with interrupts disabled. I
Since most of the I10 operations are performed using real addresses, the results of the virtual to real address translation are required by the System I10 routines.

The real address calculation function calculates the I
Bit [O:31] of the data transferred by the ◇I10 write command called by the 10il write is used as the effective address. This effective address is used for the normal translation process, but the translation result is loaded into the translated address register (FIG. 15) (TRAR) and is not used for storage accesses. TRAR contains a bit indicating whether the translation was successful, and if the translation was successful, it also contains the corresponding real storage address.

Normal storage protection processing and lock bit processing is accomplished upon successful conversion. The result of the real address calculation function is T
It can be obtained by reading I10 of RAR.

A byte block at I10 address 64 is assigned to the translation system. A block of 64 bytes is I1
It begins at the I10 address specified by the 0 base address register. The I10 base address is defined to be on the 64 boundary. The I10 address assignments listed in Table 9 are displacements within a specified 64 byte block.

The absolute I10 address is equal to the I10 base address plus this displacement.

displacement ooooo.

to 00F 010 011 012 013 014 015 016 Table 9 Allocation segment register O to 15 I10 Base address register Storage device exception register Storage device exception address register Translated real address register Transaction ID register Transaction control register RAM specification register 017 018 019 to 01F 020 -02F RO3 designation register RAS mode diagnostic register reserved TLBO address tag field for TLBO entries 0 - 15 030 - 03F TLBI address tag field for TLBO entries 0 - 15 040 - 04F for TLBO entries 0 - 15 TLBO real page number, valid bit, and key bits 050 to 05F 060 to 06F 070 to 07F 080 081 for TLBO entries O to 15 TLBI real page number, valid bit, and key bits for TLBO entries 0 to 15 TLBO write bits, transaction ID, and lock bits TLBI write bits, transaction ID, and lock bits for TLBO entries 0 to 15 Invalidate TLB entries in all TLB invalidation specification segments 0082 0083 084 or FFF 000 or FFF 000 or TLB Entries for Specified Effective Addresses Invalidate Real Address Reference and Change Bits for Load Reservation Pages O through 8191 FFFF Reservation Conclusion From the above description of the preferred embodiment of the invention, lock bits are provided in both the TLB and the page frame table. It will be apparent to those skilled in the art, however, that various changes may be readily made in the form and details of the system hardware and software without departing from the spirit and scope of the invention utilizing conventional segmentation schemes. Obviously, such changes include, but are not limited to, changes in storage sizes, register sizes and control field definitions, address sizes, page frame table access methods and organization, and hash addressing methods. do not have.

E1 DETAILED DESCRIPTION OF THE INVENTION In accordance with the present invention, the special bits provided in each segment register cooperate with lock bits provided for each line in the translation index buffer and page frame table. This allows for more fine-grained memory protection. This is particularly useful for journaling control within the system.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram of the main parts of the address translation and access control system of the present invention. FIG. 2 is a diagram showing the format of the segment register used in this address translation mechanism. FIG. 3 is a combination of a functional block diagram and a data flow diagram illustrating the conversion of effective addresses to virtual addresses. FIG. 4 is a combination of a block diagram and a data flow diagram showing the entire address translation mechanism from effective addresses to real addresses. FIG. 5 is a diagram showing the structure and contents of a translation index buffer mechanism used in the entire address translation mechanism of the present invention. FIG. 6 is a conceptual diagram of a combined hash anchor table/reverse page table and a data flow diagram illustrating the operation of such a table when no TLB entry is found for a given virtual address. be. FIG. 7 is a diagram schematically showing the structure and contents of an actual hash anchor table/reverse page table stored in the storage device. FIG. 8 shows the format of the reference and change bits used with each I10 address. FIG. 9 is a diagram showing the configuration of the I10 base address register. FIG. 10 is a diagram showing the format of the RAM designation register. FIG. 11 is a diagram showing the format of the RO3 designation register. FIG. 12 is a diagram showing the format of the conversion control register. FIG. 13 is a diagram showing the format of the storage exception register. FIG. 14 is a diagram showing the format of the storage exception address register. FIG. 15 is a diagram showing the format of the real address register to be converted. FIG. 16 is a diagram showing the format of the transaction identification register. FIG. 17 is a diagram showing the contents of one of the 16 segment registers. Figures 18.1, 18.2 and 18.3 schematically illustrate the format of the three fields utilized for each page reference in each of the translation index buffers. Note that in the embodiment disclosed herein, there are two independent translation index buffers, each of which can store 16 real page references at a time.

Claims (1)

[Scope of Claim] In a hierarchical storage system in which a virtual address supplied by a central processing unit is translated into a real address using a translation lookaside buffer and a page frame table, a segment identification field of the virtual address; A plurality of segment registers are provided for storing a segment identifier having a larger number of bits than the segment identifier and special bits related to the segment identifier, and a lock bit is provided for each line constituting a page in both the conversion index buffer mechanism and the page frame table. accessing the plurality of segment registers by means of the segment identification field of the virtual address provided by the central processing unit, and accessing the segment identifier stored in the addressed segment register and the The page offset field and the byte offset field of the virtual address are concatenated to generate a second virtual address having more bits than the virtual address, and the second virtual address is converted to a real address, and the special bits are An address conversion method characterized in that, if the lock bit is set to a predetermined value, locking is performed for each line according to the lock bit.