JPH0326096A - Cpu resetting system for controller to be supervised - Google Patents

Abstract

PURPOSE:To reset a controller to be supervised by sharing a communication transmission line by switching and outputting the reset signal of a pattern decided in advance not existing in an normal operation instead of a transmission signal from a supervisory control part for master station. CONSTITUTION:When the occurrence of abnormality in the controller 12 to be supervised is conjectured and a switch 21 is operated, a switch 23 is switched and connected from a transmission/reception part 15 to a reset pattern generator 20 side via a switch control part 22, and the reset signal of the pattern decided in advance not existing in the normal operation of a signal to be transmitted is sent to the controller 12 to be supervised via the switch 23 and a transmission line 13. A reset pattern detector 24, when detecting the reset signal, outputs a detected signal to a reset control part 25, and resets a CPU in a supervisory controller 18 for slave station compulsorily. In such a way, the controller 12 to be supervised can be reset by sharing the communication transmission line between the supervisory controller 11 and the controller 12 to be supervised.

Description

[Detailed Description of the Invention] [Summary] Monitoring information of a predetermined target is notified to the monitoring device, and the monitored device is monitored by the monitoring device! Regarding the method of remotely resetting the CPU in the +310 device from the supervisory control device, the central processing A C-viewer υml that sends a transmission signal from the main station monitoring unit 811111 equipped with the device to the transmission path via the transmitting and receiving unit.
The transmitting/receiving section receives the transmitted signal through the transmission line, and the slave monitoring section equipped with a central processing unit transmits/receives the monitoring information obtained via the external input/output section according to the received signal. In a monitoring system comprising a monitored control device that transmits signals to the monitor tswis"a via a transmission path and displays them on a display operation section of the monitoring word control device, when the signal transmitted through the transmission path is normal, a reset pattern generator that generates a reset signal of a predetermined pattern that does not exist, and a reset signal from the reset pattern generator that generates a reset signal from the main station supervisory section when there is no response from the monitored control device. and a switching output means for switching output to the transmission path instead of the transmission signal.Ill!
A reset pattern detector is provided in the II equipment and detects the reset signal inputted through the transmission line, and a central processing device in the slave station monitoring and control unit is activated by the detection signal from the reset pattern generator. A reset control unit for forcibly resetting is provided in the monitored control device.

[Industrial application field]

The present invention relates to a CPLJ reset method for a monitored TSM device, and in particular, it notifies the monitoring information of a predetermined target to the monitoring 'II'llJ device, and performs monitoring? The present invention relates to a method for remotely resetting a CPUti in a monitored υIm device controlled by a J2 ill lit device from a monitoring 1i1J control device.

A monitoring IIJim device (hereinafter also referred to as "main station") is connected to one or more monitored 1m devices (hereinafter referred to as "main station") located in a remote location.
Monitoring information of the monitored target by the "slave station" is collected by polling, etc., and the operation of the slave station is monitored based on this information.
In such a monitoring system, if the CPU in the slave station stops functioning due to a latent software bug, strongly reset the CPU in the slave station from the outside,
It needs to be restored. [Prior Art] A monitoring Mw device, which is a master station, is operated by a human, while a monitored ILW device is an unmanned slave station located remotely from the master station, and the slave station monitors a predetermined monitoring target. , the monitoring information obtained thereby is transmitted by polling from the main station. The master station displays and analyzes this monitoring information, and also monitors the operation of the slave station itself, and performs Ii1w on the slave station according to the analysis result.

Each of the master station and slave station is equipped with a central processing unit (CPU), which constitutes a supervisory control unit that is the main part of each, but it may stop functioning due to a latent software bug. In such a case, since there is no response from the slave station, the master station sends a signal to forcefully reset the CPU of the slave station.

[Problem to be solved by the invention]

However, conventionally, the above-mentioned reset signal was transmitted from the master station to the slave station using a dedicated transmission line different from the transmission line normally used between the master station and the slave station, and it was transmitted separately from the monitoring 11WJ device. A remote control Ill device for resetting the cPU and a transmission line for the reset signal are required, making the monitoring system expensive.

The present invention has been made in view of the above points, and the present invention has been made in view of the above points.
It is an object of the present invention to provide a CPU reset method for a monitored vIWJ'sWl that resets a monitored iIII device by sharing a communication transmission path between the IIi device and the monitored Ill control device.

[Means to solve the problem]

8l! FIG. 1 shows a basic configuration diagram of the present invention. In the same figure, 1
1 Ltlli? QIljllllll 1 2 is connected to the monitored υ1 equipment mr via the transmission line 13. The main station monitoring control section 14 in the supervisory W4IljwJ device 11 is a central processing I! ! It is equipped with a device that transmits i
! 15 and the transmission line 13 to the monitored Ill device 1
Send a signal to 2. Further, 16 is a display operation unit that displays monitoring information from the monitored device 12,
IJID-equipped W112! Perform operations such as output of 1119 information.

sllII) The device 12 to be monitored has a transmitting/receiving section 17. Slave station monitoring control unit equipped with a central processing unit 18. External input/output section 1
9, etc., and transmits the monitoring information obtained via the external input/output unit 19 to the monitoring control II device 11 in accordance with the received signal.

In a monitoring system having such a configuration, the present invention provides the monitoring TSM device 1211 with a reset pattern generator 20, a switching output means consisting of a switch 21, 23, and a switch control unit 22, while the monitored TAII device 12 It is characterized in that it includes a reset pattern detector 24 and a reset control section 25.

The pattern generator 20 described above generates a reset signal of a predetermined pattern that does not exist when the signal transmitted on the transmission line 13 is normal. Further, the switching output means switches and outputs the reset signal from the pattern generator 120 to the transmission path 13 instead of the transmission signal from the transmitter/receiver 15 when there is no response from the monitored MS device 12.

Meanwhile, the reset pattern detector 24 detects the reset signal. Further, when the reset control section 25 receives a detection signal from the reset pattern detector 24, it forcibly resets the central processing II in the slave station monitoring υ1 control section 18.

(Operation) The master station monitoring sIJiI1 section 14 is connected to the slave station monitoring control section 18 via the transmitting/receiving section 15 and the transmission line 13 by software.
Polling is performed for . Then, the subordinate supervisor? lI
The I+11 section 18 responds to the above polling via the transmitting/receiving section 17 by software, collects monitoring information, sends control information, etc. to the external input/output section 19, and also sends the monitoring TSM via the transmission path 13. monitoring information etc. is sent to the device 111.

As a result, during normal operation, the display operation section 16 displays the monitored tS.
Monitoring information from the W unit 12 is displayed, and the monitored all equipment 1212 is controlled based on information operated by the operating unit.

On the other hand, if the central processing unit (CPU) of the slave station monitoring IIlw1 section 18 stops functioning due to a software bug or the like, the master station monitoring control section 14 will no longer be able to respond to polling, and a display to that effect will be displayed on the operation section. 16 and notify the maintenance personnel.

This display allows maintenance personnel to
Waiting for the occurrence of an abnormality, the switch 21 is operated. As a result, the switch 23 is connected via the switch 611111 section 22 from the transmitting/receiving section 15 to the reset pattern generator 20 side, and the reset jrA of the predetermined pattern is transmitted to the monitored device via the switch 23 and the transmission line 13. 12
Send to.

When the reset pattern detector 24 detects this reset signal, it outputs the detection signal to the reset control section 25, which forcefully resets the CPU in the slave station monitoring TSM section 18.

〔Example〕

FIG. 2 shows a monitoring device 1 which constitutes the main part of the present invention.
1 shows a circuit diagram of the Ikkiura example. In the figure, the same components as in FIG. 1 are designated by the same reference numerals. In FIG. 2, the transmitter/receiver 15 is a communication IC (URT: Unfversat
Receiver Transmitter) 3
0, a clock generator 31, and a communication IC 3.
0 is controlled by the software of the main station monitoring IllWJ unit 14, and is controlled by, for example, the known eye DL. C (H io
h ievelData Link Control)
Sends and receives data in the format specified by the procedure. Further, the clock generator 31 generates a clock having a period equal to one time slot of this data.

That is, the communication IC 30 is as shown in FIG. 3(A).
8-bit flag pattern F. 8-bit address field A. 8-bit control field C. Information fields marked by ■1 to 1■ of the manager. The HDLG format transmission data "XD", which is one frame consisting of a 16-bit check pit and an 8-bit flag pattern F, is transmitted, and the reception data TXR of the same frame format is received.Here, the flag sequence F is "01111110J". This is an 8-bit bit string with a fixed pattern, and in order to prevent this pattern from appearing in other frames, if 5 "1"s are consecutive, "O
” is automatically inserted.

The clock from the clock generator 31 is shown in FIG.
) is a symmetrical square wave with a period of one time slot, as shown by TXC.

Further, in FIG. 2, reference numeral 16a denotes a main part of the display operation section 16, which includes a latch circuit 32, a light emitting diode 33,
, a reset switch 21, an inverter 34, etc. The light emitting diode 33 is turned on when there is no response from the monitored tsmvlw.

Reference numeral 35 denotes a main station reset sIJl1 section, which includes 16-bit counters 36 and 37 and a DIM flip-flop 38. The counter 36 is connected to the reset pattern generator 20.
The counter 37 and the flip-flop 38 constitute the switch controller 20. The Q output signal of the flip-flop 38 is applied to the selector 39 forming the switch 23 as a select signal.

Next, to explain the operation of this embodiment, the slave station (supervised station)
illi! If there is no response from the I device>, low level data is latched in the latch circuit 32, and the light emitting diode 33 is turned on. As a result, the switch 21 is turned on either manually by the maintenance person or automatically from time t1 to t3, as shown in FIG. 3(C).

On the other hand, the counter 36 receives the clock TXC from the clock generator 31, and the level of the clock TXC is inverted every time it counts 8 clocks TXC from its Q4 output terminal.
The square wave shown in B) is output as a reset signal. Therefore, this reset signal is a fixed pattern with a 16-bit period in which 8 consecutive bits of "ON" and 8 consecutive bits of "1" alternately appear, and this is a pattern that does not exist in the HDLC format described above. To,
The reason why the reset pattern is a pattern that does not exist in HDLC is to prevent it from being erroneously received as data by the transmitting/receiving section 17''C' of the slave station since the transmission path used during normal operation is shared.

The carry output of the counter 36 mentioned above is output as shown in FIG. 3(D) every time the clock TXC is counted by 16.
It is applied to the clock terminal of flip-flop 38, while it is applied to the clock terminal of counter 37. here,
Since a signal having the opposite phase to that shown in FIG. 3(C) is inputted to the data input terminal of the flip-flop 38 via the inverter 34, as shown in FIG. 3(E), the time t! The signal that becomes high level at the carry output time t2 immediately after is flip flop 0.
It is taken out from the Q output terminal of the pin 38.

During the period when the Q output M of the flip 70 is at a high level, the selector 39 selects and outputs the reset signal shown in FIG. 3(B) from the Q4 output terminal of the counter 36 as transmission data.

When the counter 37 counts eight carry outputs from the counter 36 at time t4 in FIG. 3(D), it outputs a high level signal from its 04 output terminal and resets the flip-flop 38. As a result, the Q output signal (select signal @) of the flip 7 lobe 38 becomes 0-level at time t4 as shown in FIG. 3(E), and the selector 39 is switched to the communication IC 30 side tI1111.

In this way, the selector 39 of the monitoring TSM device 11 shown in FIG. 2 repeatedly outputs a reset signal having a 16-bit reset pattern eight times.

In addition, FIG. 4 has been re-illustrated by changing the time axis from FIG. 3, and FIG. 4 (A) shows the signal shown in FIG. E), the select signal shown in Fig. 4(
C) largely shows the reset signal and transmission data shown in FIG. 3<8).

Next, the configuration and operation of one embodiment of the monitored control device 12, which constitutes another essential part of the present invention, will be described with reference to FIGS. 5 and 6. FIG. 5 shows an embodiment of the monitored control device 12.
In Figure M, the same components as in Figure 1 are given the same reference numerals. In FIG. 5, the transmitter/receiver 17 is the transmitter/receiver 1
5, it is composed of a communication fc (LJR) 41 and a clock generator 42.

Also, 43 is the slave station reset fee section, and the reset pattern detector is 24.4m! Continuation verification circuit 44 and 1 second timer 45
It becomes more. 4 luck matching circuit 44 is I for question 1 m 4 times! The circuit outputs, for example, a high-level signal at that point when the signal is inputted.

Furthermore, the slave station monitoring lIl control! h18 is 1041 for communication
driver/receiver 46. connected to the driver/receiver 46. CPU47. Driver/Receiver 48. It is composed of an OR circuit 49 and the like. The CPL147 is configured to be reset by the output signal of the OR circuit 49. Further, the driver/receiver 48 is connected to the external input/output section 19.

Next, we will monitor the configuration shown in Figure 5! iIJIft device 12
To explain the operation of the monitor IliIIIl device (main station) 11, a reset IIIl is performed at time t1 as shown in FIG. If the reset pattern detection B24 shown in FIG.
Every time a 6-bit predetermined reset pattern is detected, a detection signal is output as shown in FIG. 6(C).

As described above, since the reset pattern is transmitted eight times in succession, eight detection signals are extracted from the reset pattern 1 to the pattern detector 24 every 16 time slots.

The four-way verification circuit 44 outputs a high-level verification signal as shown in FIG. 6(D) at time t4 when the above-mentioned detection signal is inputted continuously for 417J times, and starts the one-second timer 45. The reason why the one-second timer 45 is not started until the detection signal is received four times in a row is to prevent W4ilJ operation due to noise or the like.

The 1-second timer runs for 1 second from the above startup time t4, as shown in Fig. 6 (
As shown in E), a high level reset signal is generated and applied to the reset terminal of the CPU 47 through the OR@ path 49 to forcibly reset the CPU 47. The reason why the reset signal was held for 1 second is that although the time required for resetting differs depending on the type of CPυ47, 1 second is sufficient for resetting.

It should be noted that the present invention is not limited to the above-described embodiments; for example, the reset pattern may be a fixed pattern that does not exist during normal operation, and may also be used for changes that are not specified by the encoding method (data modulation method). The pattern can also be a reset pattern.Also, although it is normal for there to be l! number of slave stations 12, when an abnormality occurs, there are usually two at the same time.
Although it is possible to supply reset signals to them at the same time (for example, by adding a unique 'It@ assigned to each slave station as a header, or by adding a reset pattern to each slave station), it is possible to supply a reset signal to them at the same time. ).

(Effects of the Invention) As described above, according to the present invention, the CPU of the unmanned monitored IIiIl device installed in a remote location is
By simply adding a simple circuit, you can share the transmission path used during normal operation and perform a reset without using SW equipment or a dedicated transmission path, reducing system costs compared to conventional systems. It has features such as being able to

[Brief explanation of drawings]

Fig. 1 is a diagram of the wiring structure of the present invention, Fig. 2 is a circuit diagram of an embodiment of the main part of the present invention, and Figs. 3 and 4 are respectively 28! ! FIG. 5 is a circuit diagram of an embodiment of another essential part of the present invention, and FIG. 6 is a time chart for explaining the operation.
The figure is a time chart for explaining the operation of FIG. In the figure, 11 is the monitoring 11111 translation, 12 is the monitored system m*a, 13 is the transmission path, 14 is the main station monitoring control unit, 15.17 is the transmitting/receiving unit, 16 is the display operation unit, and 18 is the slave station monitoring unit. t. 19 is an external input/output section, 20 is a reset pattern generator, 21.23 is a switch, 22 is a switch υIII) section, 24 is a reset pattern detector, and 25 is a reset control section.

Claims (1)

[Claims] A supervisory control device (11) that sends a transmission signal from a main station supervisory control unit (14) equipped with a central processing unit to a transmission path (13) via a transmitting/receiving unit (15); The transmitting/receiving section (17) receives the transmission signal via the transmission line (13), and the slave station monitoring control section (18) equipped with a central processing unit sends the signal to the external input/output section (1
9) is transmitted to the supervisory control device (11) via the transmitting/receiving section (17) and the transmission line (13) in accordance with the received signal, and In a monitoring system comprising a monitored control device (12) displayed on a display operation section (16), a reset that generates a reset signal of a predetermined pattern that does not exist when the signal transmitted on the transmission path (13) is normal. pattern generator (
20), when there is no response from the monitored and controlled device (12), the reset signal from the reset pattern generator (20) is replaced with the transmission signal from the main station supervisory control unit (14), (13) and switching output means (21, 22, 23) for switching output to the monitoring and control device (11).
a reset pattern detector (24) included in the transmission line (13) to detect the reset signal inputted through the transmission line (13); and a detection signal from the reset pattern generator (24) to detect the slave station monitoring control unit. (18) A CPU reset method for a monitored controlled device, characterized in that the monitored controlled device (12) is provided with a reset control unit (25) for forcibly resetting the central processing unit. .