JPH03257621A - Floating point multiplying circuit - Google Patents

Abstract

PURPOSE:To improve the throughput of multiplication by selecting any one of the data of a multiplied result, data shifting one digit to left in the matissa part of the multiplied result and the output data of an arithmetic result register storing data, for which the multiplied result is normalized by a normalizing shifter, according to a normalizing amount deciding signal. CONSTITUTION:Based on floating point data 10 and 20 to be inputted to a multiplier 1, a normalizing amount deciding circuit 6 calculates the normalizing amount of a multiplied result 100 from the multiplier 1. The circuit 6 outputs 00 and a circuit 8 selects the output of an intermediate result register 2. When the normalizing amount is one digit on the left side, the circuit 6 outputs 01 and the circuit 8 applies the mantissa part of an output 200 from the register 2 to a left-side one digit shifter 5 and normalizes the mantissa part by shifting one digit to the left side. Then, normalized data 500 is selected and outputted as an output signal 800. When the normalizing amount is neither 0 digit nor 1 digit, the circuit 6 outputs 1X and the circuit 8 selects normalized data 400 from an arithmetic result register 4. Thus, the through-put of a floating point multiplying instruction can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a floating point multiplication circuit, and more particularly to a floating point multiplication circuit used in an information processing device.

Prior Art Conventionally, this type of floating-point multiplication circuit consists of a multiplier that multiplies the mantissa, an intermediate result register that stores the multiplication result of the mantissa output from this multiplier, and a normalized state of this intermediate result register. It consists of a normalization shifter that normalizes data that is not normalized.

In such a multiplication circuit, most of the input data is normalized data, so in most cases the normalized amount of the multiplication result before normalization stored in the intermediate result register is "0" digit or 1 left It is a digit.

However, the multiplication result stored in the intermediate result register is first normalized using a normalization shifter, and then stored in the operation result register. The configuration is such that the data is then transferred to an external register of the floating-point multiplication circuit. For this reason,
Even if the amount of normalization is small, it takes one clock cycle for the normalization process regardless of the amount of normalization. As a result, there is a drawback that processing performance is not improved.

OBJECTS OF THE INVENTION An object of the present invention is to provide a floating point multiplication circuit with improved multiplication processing performance.

Structure of the Invention A floating point multiplication circuit according to the present invention comprises a multiplication means for multiplying floating point data, a normalization shifter means for normalizing the multiplication result from the multiplication means, and a mantissa part of the multiplication result from the multiplication means. 1-digit shifter means for shifting by one digit, and a normalized amount of the multiplication result from the mantissa part of the floating-point data input to the multiplication means, and a normalized amount of 0 digit, left 1 digit, or other. A normalization amount determination means for outputting a determination signal; and when the normalization amount determination signal from the normalization amount determination means indicates a 0-digit normalization amount, the multiplication result from the multiplication means is selected, and the multiplication result from the multiplication means is selected; selecting the output of the one-digit shifter means when the normalization amount determination signal indicates the normalization amount of the first digit on the left; and selecting means for selecting the data normalized by the normalization shifter means when the data is normalized by the normalization shifter means.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention includes a multiplier 1 that performs multiplication of floating point data 10 and 20, and an intermediate result register 2 that receives the multiplication result 100 that is the output data of this multiplier 1. , a normalization shifter 3 that normalizes the output data 200 of the intermediate result register 2, an operation result register 4 that stores the data 300 normalized in the normalization shifter 3, and the output data of the intermediate result register 2. Is the normalized amount of the multiplication result 100 output from the multiplier 1 by inputting the left 1 digit shifter 5 which shifts the mantissa part of 200 by 1 digit to the left and the mantissa parts of floating point data 10 and 20? A normalization amount judgment circuit 6 that outputs a normalization amount judgment signal 600 indicating whether it is the left 1 digit or something else, and a normalization amount judgment signal 600 from this circuit 6 is stored, and the normalization amount judgment signal 600 is stored until the multiplication instruction ends. Flip-flop (FF) 7 that holds this signal 600, output data 400 of operation result register 4, output data 500 of left 1-digit shifter 5, and output data 200 of intermediate result register 2 are transferred to FF 7. In this embodiment, the calculation result selection circuit 8 selects by controlling the output signal 700 and outputs the calculation result as the output data 800, and the output signal 700 of the FF 7 is manually used as one factor for branch address generation. and an arithmetic control circuit 9 that controls a high-speed floating-point multiplication circuit.

Next, the operation of one embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, the normalization amount determination circuit 6 includes a multiplier 1
The normalized amount of the multiplication result 100 from the multiplier 1 is determined based on the floating point data 10 and 20 to be input to the multiplier 1.

When it is determined that the normalized amount is 0 digits, the circuit 6 performs “
00'' is outputted, stored in the FF 7, and then given as a selection signal to the operation result selection circuit 8. The selection signal causes the circuit 8 to select the output of the intermediate result register 2.

On the other hand, the arithmetic control circuit 9 executes the multiplication instruction in two steps: a "multiplication step" and a "storage step to an external register of this multiplication circuit." A similar operation occurs when the circuit 6 determines that the normalized amount is one digit on the left.

When it is determined that the normalized amount is the left 1 digit, the circuit 6 outputs “
In the multiplication step in which 01° is output, “01” is output to the FF 7, and the normalized mass-produced one-digit multiplication result from the multiplier 1 is stored in the intermediate result register 2. Furthermore, F.F.
7 outputs "01" as the output signal 700, so the arithmetic control circuit 9 omits the normalization step.

In the storing step of this circuit 9, the output signal 7C of the FF7
- In response to “01° as 0, circuit 8 sets register 2
The mantissa part of the output 200 is given to the left 1-digit shifter 5. left 1
The digit shifter 5 normalizes the mantissa by shifting it one digit to the left. The selection circuit 8 selects the normalized data 500 and outputs it as an output signal 800.

When the normalized amount is neither 0 digit nor 1 digit, the circuit 6
' is output as the normalization amount determination circuit 600. X” indicates that this bit is optional.

In response to “IX” of the signal 600, the calculation result selection circuit 8
is the normalized data 400 from operation result register 4
Select. That is, the output signal 700 of FF7 or “I
X”, “multiplication step”, “normalization step”,
3 of “Step of storing this multiplication circuit in an external register”
Executes a multiplication instruction by stepping.

DETAILED DESCRIPTION OF THE INVENTION As described above, the present invention provides a normalization amount determination circuit that outputs a normalization amount determination signal indicating whether the normalization amount of a multiplication result is 0 digit, left 1 digit, or something else; Depending on the amount judgment signal, which of the data of the multiplication result, the data obtained by shifting the mantissa part of the multiplication result by one digit to the left, and the output data of the operation result register storing the data obtained by normalizing the multiplication result by the normalization shifter is selected. By providing a selection circuit that selects whether the normalized amount of the multiplication result is 0 digit or 1 digit on the left, the normalization processing operation and the storage operation to the external register of this multiplication circuit can be performed in one step, and the floating This has the effect of improving the processing performance of decimal point multiplication instructions.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention. Explanation of symbols of main parts 1... Multiplier 2... Intermediate result register 3... Normalization shifter 4... Arithmetic result register 5... ...Left 1-digit shifter 6...Normalization amount judgment circuit 7...Flip-flop (F F) 8...
...Arithmetic result selection circuit 9...Arithmetic control circuit

Claims (1)

[Claims] (1) Multiplication means for multiplying floating point data, normalization shifter means for normalizing the multiplication result from the multiplication means, and one-digit shifter means for shifting the mantissa part of the multiplication result from the multiplication means by one digit. and a normalization amount determination that calculates the normalization amount of the multiplication result from the mantissa part of the floating point data input to the multiplication means and outputs a normalization amount determination signal as to whether it is 0 digit, left 1 digit, or something else. and when the normalization amount judgment signal from the normalization amount judgment means indicates a normalized amount of 0 digit, selects the multiplication result from the multiplication means, and selects the multiplication result from the multiplication means, When indicating the normalized amount, the above 1
The output of the digit shifter means is selected, and the normalization amount determination signal is 0.
and selecting means for selecting data normalized by the normalization shifter means when the normalized amount indicates a normalized amount that is neither a digit nor a left digit.