JPH03256168A - Logical simulation system - Google Patents

Abstract

PURPOSE:To reduce an initializing work time by about 10 or 20% as compared with convensional technique by allowing a logical simulator to check whether the inside of an LSI for logical simulation has been completely initialized or not in the initializing work. CONSTITUTION:The outputs of flip flops (FFs) 11 to 13 in the LSI 10 are retrieved by the logical simulator. The FF whose output is in an unsteady state out of the FFs 11 to 13 in the LSI 10. Then, the FF numbers of the unsteady FFs and the number of unsteady FFs are displayed on the logical simulator. The total number of unsteady FFs is also displayed. Thus, the unsteady, i.e. uninitialized, FFS can easily be decided and logical information and I/O states relating to the FFs 11 to 13 can be observed at a glance, so that logical inspection work can easily e executed and the efficiency of logical simulation can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic simulator used during LSI development, and particularly to a logic simulation method suitable for evaluating results after execution of a simulation.

[Conventional technology]

LSIs are developed through a design process such as logic design, logic design verification such as logic simulation, and layout design, as well as a chip production process and testing process. The most important step in the design process is μ, the logic design verification process that involves logic simulation.

This logic simulation is a task of applying input signals to the LSI and checking whether the output results match expected values. In actual logic simulation, it is necessary to initialize the logic inside the LSI prior to the logic simulation. This is because the logic inside an LSI is not only a combinational logic circuit made up of logic gates such as NAND and OR, but also a sequential logic circuit made up of 7 flip-flops. I don't know if it will become ``1'' or ``1''. Therefore, in order to faithfully simulate this, the initial state of the 7 lip-flop in the logic simulator is set to an undefined state @X# (a state that is neither 10' nor '1').
It is treated as such.

Further, factors that cause an undefined state to occur during execution of logic simulation include, for example, a short circuit in which output signals are connected to each other. If this undefined state is latched to the flip-flop 7, the output of the flip-flop 70 will also become undefined.

[Problem to be solved by the invention]

In the prior art described above, normal logic simulation cannot be performed unless the logic state inside the LSI is initialized to the "0" state or the "1" state and the undefined state ""X" is removed. Here, flip-flop 1 in FIG.
It is assumed that the initial state of 1 is an undefined state t x s. Therefore, for example, by giving "0" to the data D1 and changing the clock CK1, for the flip 70 knob 11,
It is necessary to hold '0'.This kind of processing is done in LS
This must be done and initialized for all 7 lip-flops inside I. Otherwise, the undefined state will propagate to the other seven lipfrogs, making it impossible to perform normal logic simulation.

In addition, when checking whether all seven flip-flops inside the LSI have been initialized, the logic verifier must check the output states of the flip-flops, which is very time-consuming. was there.

Further, during execution of the logic simulation, the flip-flops inside the LSI are in an undefined state, and a large number of undefined states are output to the external terminal of the I-bar, which may make it impossible to evaluate whether the simulation is normal or not. In this case, the logic verifier must trace back and find out which 7-lip 70 tubes inside the I and SI are in an undefined state and the logic related to the LSI external terminal that is outputting the undefined state.
There was also the problem that logic verification took time and logic simulation efficiency decreased.

An object of the present invention is to facilitate the detection of flip-flops in an undefined state and to improve the efficiency of logic simulation and logic verification work.

[Means to solve the problem]

In order to achieve the above object, the present invention searches for the output state of a flip-flop that holds data in the LSI in a logic simulator that checks the logic function of an LSI, and searches for the output state of a flip-flop that holds data in the LSI, The location and number of flip-flops in the state are now displayed.

In addition, in a logic simulator that checks the logic function of an LSI, specify the internal or external terminal of the LSI that is outputting an undefined state at a specific time, and The logic is verified and the logic information of the flip-flop in an undefined state and the elements related to the seven flip-flops and the input and output states of the logic related to the flip-flop are displayed.

[Effect]

In the logic simulation method according to the present invention, as shown in FIG. 1, a logic simulator searches the outputs of the seven lip-flops inside the LS 110 in FIG. 2.

Then, 7 lip-flops whose outputs are in an undefined state are stored. This operation is performed for all seven lip-flops inside the LS110. Thereafter, the number and number of flip-flops that are in an undefined state as shown in FIGS. 5 and 6 are displayed on the logic simulator. In other words, as shown in Fig. 5, when the logic verifier inputs the range of the pattern he wants to search, from the 1st step to the 5th step in the figure,
The logic simulator searches the outputs of flip-flops according to the flowchart in Figure 1, detects flip-flops in an undefined state, and calculates the number of the flip-flop and the period in which it has been in an undefined state, for example as shown in Figure 5. The 7-lip flow tube numbered A3'' is displayed as being in an undefined state from the 1st step to the 3rd step.The total number of 7-lip steps and 70 knobs in an undefined state is also displayed.

Further, in the example of FIG. 6, a flip-flop in an undefined state is detected and displayed at the fifth step.

In this way, an undefined state, that is, an uninitialized flip-flop can be easily found, so that the necessary LSI initialization work in logic simulation is simplified.

Also, as shown in FIG. 7, the logic verifier is in an undefined state, that is,
When an internal or external terminal P outputting an undefined value "X" is specified, the logic simulator searches for a flip-flop that is in an undefined state according to chart 70 in the figure. Then, the logic information and input/output status of the logic related to the flip-flop are displayed as shown in FIG. in this way,
Since a flip-flop in an undefined state can be easily identified and the logic information and input/output state related to the flip-flop can be seen at a glance, logic verification work is facilitated and logic simulation efficiency is improved.

〔Example〕

Hereinafter, a method for searching a flip-flop having an indefinite value according to an embodiment of the present invention will be explained with reference to FIGS. 1 to 6. First, the internal configuration of the LSI shown in FIG. 2 will be explained. 10
is an LSI, 11, 12.13 are flip-flops that hold data, 21 is the positive output of flip-flop 11, and 2
2 is the positive output of the flip-flop 12, 23 is the positive output of the 7-lip flop 13, 24 is the negative output of the 7-lip flop 13, and 14.15 and 16.17 are logic gates. Further, FIG. 3 is a timing chart in LSllo of FIG. 2. The output 21 of the flip-flop 11 is
The first step is an undefined state "X#," and the second step is to give "0" as data D1 and raise the clock CK1 to hold "0", so that the output 21 becomes 10#. Similarly, at the 6th step, the undefined state ""X# is latched and output 2
1 becomes an undefined state @X#. Also, flip-flop 1
The output 22 of 2 is also from the 1st step to the 2nd step.
In the undefined state 1X'', the data ``1#'' is held from the 5th step, and the output 22 also becomes @1j'. Similarly, the positive output 25 and negative output 24 of the 7-lip flop 15 are in an undefined state "X#" from the 1st step to the 5th step, hold "1#" at the 4th step, and the positive output 26 is "1#". The negative output 24 outputs "0". Also, output 01゜0
2.03 is the output 2 of flip-flock 11, 12.15
1.22, 23.24 as logic gates 14, 15, 16 .
17 and output as shown in FIG.

Next, the search operation will be explained according to the flowchart shown in FIG. First, when the logic verifier specifies the range to be searched (from the 1st step to the 5th step) as shown in Figure 5, the logic simulator starts from the first step (1st step) of the specified range, Start searching all 7lips 70tubs. First, it is determined whether the state of the output 21 of the 7-lip flop 11 numbered A1 is indeterminate. In this case, as can be seen from FIG. 4, the state is in an undefined state 1X#. Therefore, the number A1 of this 7 lip-flop is stored. Similarly, the 7-lip 70 tube 12 with number A2 and the flip-flop 15 with number A3 are searched. Once all 7 lip-flops have been searched, the step to search is updated. If the search range is within the specified range, the search is performed again using the same flow. In FIG. 5, since it is specified to search from the 1st step to the 5th step, the logic simulator searches the flip-flops 11, 12 and 13 in the LS110 from the 1st step to the 5th step.
Check the output status. As a result, as shown in FIG. 4, the undefined state at the first step of one search range is the flip 70 with numbers AI, A2 and A3.
At knobs 11, 12, and 13, the second step is number A.
2. In the 7-lip flip-flop 12.13 of Al, the third step is the flip-flop 13 with number A5, and there are no 7-lip 70 flip-flops in an undefined state in the fourth and fifth steps. The logic simulator displays this result as shown in FIG.

That is, the flip-flop 11 with the number A1 is in the first step of the period, the 7-lip flop 12 with the number A2 is in the undefined state from the first step to the second step, and the flip-flop 13 with the number A5 is in an undefined state from the first step to the fifth step. is displayed.

In addition, the button also displays the total number of 70 lip types that are in an undefined state within the search range. In FIG. 5, a total of three elements, including the line and flip-flops 11, 12, and 13, are undefined, so the total number is shown as three elements.

In this way, compared to the conventional technology in which all the states of flip-flops inside the LSI were checked by a logic verifier, the logic simulator verifies the states, making the verification work easier and improving the efficiency of logic simulation.

As another example, as shown in FIG. 6, it is possible to search for 7 lip-flops in an undefined state by searching only one step. For example, in FIG. 6, only the second step is searched. As a result, 7 lip-flop 12 with number A2 and 7 lip-flop 13 with number A3 are in an undefined state, and the total number is expressed as 2 elements. In this case as well, the same effects as in the embodiment shown in FIG. 5 can be obtained.

Next, an embodiment will be described with reference to FIGS. 7 to 9, in which when an internal or external terminal outputting an undefined state is specified, a flip-flop causing the problem can be searched. First, the logic verifier designates the terminal that outputs the undefined state 1X, that is, the external terminal 01 as shown in FIG. 8. At the same time, the step (time) that outputs the undefined state "X".

Specify 6 steps. Then, the logic simulator first searches for the element outputting from external terminal 011C, that is, the logic gate 15 with number B2 in FIG. Display related logic information and timing charts. Since the aforementioned element is a logic gate 15 and not a flip-flop from FIG. 2, next, the inputs 25, 25 of the logic gate 15, that is, the output of the logic gate 14 numbered B1 and the positive output of the flip-flop 13 numbered A3. Search for the status of. In this case, as shown in FIG. 9, the output of the logic gate 14 with number B1 is in an undefined state @
It becomes. Also, as described above, a check is made again to see if the logic gate 14 with number B1 is a 7-lip flop. Here, since it is not a flip-flop, the input state of the logic gate 140 with number B1 is similarly searched. Input P11 in FIG. Input PI2... is the long sword terminal of the element.

As shown in FIG. 9, the input 21 (output from the element numbered A1) is in an undefined state "X#.The input 21 is the output from the element numbered A1.
Since the output is from the flip-flop 70 block 11 of No. 1, it can be identified as the flip-flop which is in an undefined state @ The logic information related to the knob 11, such as the logic gate 14, and the timing chart are displayed as shown in FIG. 8. Also, the internal terminal, for example, the output 25 of the logic gate 14 numbered B1 in FIG. Even if the external terminal 01 is specified, the search is performed according to the chart 70 in FIG. be able to.

In this way, by simply specifying the internal terminal or external terminal to be searched and the search time (search step), flip-flops that are in an undefined state can be identified, which saves the logic verifier from analyzing the logic relationships inside the LS110. can be omitted. Therefore, the logic verification work can be easily completed in a short time, and the efficiency of logic simulation is dramatically improved.

〔Effect of the invention〕

When initializing the inside of an LSI for logic simulation, logic verifiers used conventional technology to check whether it was completely initialized or not by checking 7 lips and 70 pieces inside the LSI. , can be performed by a logic simulator in the present invention.

Further, in the present invention, uninitialized flip-flops can also be identified at a glance. Therefore, it is possible to solve the problem that logic simulation cannot be reliably performed due to incomplete initialization. Therefore, the initialization work time can be reduced by about 10 to 20 steps compared to the prior art.

Furthermore, according to the present invention, even if the 7 flip-flops inside the LSI become undefined fli4 during execution of a logic simulation, the logic simulator can identify the 70 flip-flops. Therefore, as shown in FIG. 11, when an undefined state is output, logic analysis in 310, which was performed by a logic verifier in the conventional technology, designation of internal signals for tracing inside the LSI in 311, and simulation results in 513. In the present invention, the task of evaluation only requires specifying the terminal and time at 501 in FIG. Therefore, logic verification work can be easily performed, and the logic simulation period can be reduced to approximately the same amount as in the conventional stirrup.

[Brief explanation of drawings]

1 is a flowchart explaining the operation of one embodiment of the present invention, FIG. 2 is a diagram of internal logic information of the LSI of the present invention, FIG. 5 is a timing chart of FIG. Explanatory diagrams of the search status in the flowchart shown in Figures 5 and 6.
The figure is an explanatory diagram when displaying the search results in Figure 1, and Figure 7.
The figure is an explanatory diagram of the operation of another embodiment of the present invention, Figure 8 is an explanatory diagram of the display of the search results in Figure 7, and Figure 9 is an illustration of the display of the search results in Figure 7.
Figure 10 is an explanatory diagram of the search state in the 0-chart, and Figure 10 is an explanatory diagram of the search method for 7 flip-flops in an undefined state in the present invention. It is a diagram. 10, i...LS1 11.12.13...Flip-flop 14.15,
16.17...Logic gate. 16) Figure 5 JP-A No. 3 256168 (8) No. 10 No. 11 L\l σK D 10 On the drawing, it is ``indeterminate dog 1 character/ni''...the solution to Naruko's theory.

Claims (1)

[Claims] 1. In a logic simulator that checks the logic function of an LSI, the output state of a flip-flop that holds data within the LSI is searched, and the output state of a flip-flop that holds data is found to be in an undefined state that is neither 0 level nor 1 level. A logic simulation method characterized in that the location and number of flip-flops are displayed on the logic simulator. 2. In a logic simulator that checks the logic function of an LSI, specify the external terminal of the LSI that is outputting an undefined state at a specific time, and check the internal logic of the LSI that is outputting to the specified terminal. , identify the flip-flop that is in an undefined state, and further display on the logic simulator the logic information of the element related to the flip-flop and the input state and output state of the logic related to the flip-flop. Features a logical simulation method.