JPH03254498A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce power consumption, power noise and radiation by providing a decoder applying precharging only to a precharge device connecting to a signal readout line selected by a selector. CONSTITUTION:The storage device is made up of a decoder 1 applying precharging only to a precharge device 4 connecting to a signal readout line selected by a selector 7 and a synchronizing device 9 synchronizing a decoder output with a precharge timing, the precharge device 4 connects to the synchronizing device 4 and the precharge device 4 precharging the signal readout line synchronously with the decoder output is selected. That is, only the selected signal readout line is pre-charged. Thus, power consumption, power noise and radiation are reduced easily.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory device equipped with selection means for selectively performing a precharge operation during signal reading.

Conventional technology In recent years, as LSIs have become more highly integrated and highly functional, RAM
In LSIs equipped with storage devices such as ROM and ROM, the storage capacity of the storage devices is increasing significantly.

A conventional semiconductor memory device will be described below.

FIG. 2 is a block diagram of a conventional semiconductor memory device, in which 20 is a decoder for selecting an address line, and 21 is a decoder for selecting a signal read line.

Reference numeral 22 denotes a precharge device having a plurality of precharge sections 221 to 224 connected to the signal readout line, and a precharge signal 20[1 is supplied to each of the precharge sections 221 to 224. 23 is a precharge section 221
This is a storage element array having a plurality of storage element column parts 231 to 234 connected to signal readout lines corresponding to 224 and connected to the decoder 20. 24 is memory element row 2
A first selector device 25 has a plurality of selector sections 241 to 244 connected to signal readout lines in correspondence with 31 to 234; Output 25
5 is a second selector device to which the contents of the selected memory element of the memory element array 23 are output;
Connected to 1.

The operation of the semiconductor memory device configured in this manner will be described below. First, precharge signal 20
When 0 becomes high level, the signal read lines connected to the precharge sections 221 to 224 of the precharge device 22 are precharged. Further, the precharge signal 200 is passed through the inverter 26 to the output permission 2 of the decoder 20.
08, and at this time, all outputs of the decoder 20 become low level. Next, when the precharge signal 2H becomes low level, the precharge sections 221 to 224 of the precharge device 22 stop precharging the signal readout line.

Further, since the output permission input 208 of the decoder 20 becomes high level, the decoder 20 outputs the address inputs 205 to 20.
The address line selected by 7 is set to high level. The storage elements of the storage element array 23 selected by the address line output their stored contents to the signal readout line. The stored contents of the selected signal readout line are input to the selector sections 241 to 244 of the first selector device 24, selected by the address inputs 203 and 204 input to the decoder 21, and input to the second selector device 25. Second selector device 2
5 is an address input 201 input to the decoder 21;
A further selection is made in step 202, and as a result, the contents of the memory element selected in address input H1-2117 are outputted to data output 255.

Problems to be Solved by the Invention However, in the above-mentioned conventional configuration, all signal read lines are precharged when reading a storage signal.
This has the problem of high power consumption, and high power supply noise and radiation.

The present invention solves the above-mentioned conventional problems, such as power consumption,
It is an object of the present invention to provide a semiconductor memory device that can reduce power supply noise and radiation with a simple configuration.

Means for Solving the Problems In order to solve the above problems, the semiconductor memory device of the present invention includes:
Equipped with a decoder to precharge only the precharge device connected to the signal readout line selected by the selector, and a synchronizer to synchronize the decoder output with the precharge timing, and connect the precharge device to the synchronizer. However, a precharge device that precharges the signal readout line in synchronization with the decoder output is selected.

Effect: With the above configuration, the selection means for precharging only a part of the precharge device including the signal readout line selected by the address signal is provided, so that only the selected signal readout line can be precharged. This makes it possible to easily reduce the power consumption, power supply noise, and radiation of the semiconductor device.

Example An embodiment of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram showing the configuration of a semiconductor device in one embodiment of the present invention. In FIG. 1, 2.3 is a decoder, 4 is a precharge device consisting of a plurality of precharge sections 41 to 44, 5 is a storage element array consisting of a plurality of storage element columns 51 to 54, and 6 is a plurality of selectors ill to 54 is a first selector device, 7 is a second selector device, 8 is an inverter, and decoder 20.2L in the conventional example
It has the same configuration as the precharge device 22, the memory element array 23, the first and second selector devices 24, 25, and the inverter 26. 1 is a decoder for precharging only the precharging sections 41 to 44 of the precharging device 4 connected to the signal readout line selected by the second selector device 3; a synchronizing device connected to this decoder 1; 9 is the input precharge signal 10
5 is each precharge part 4 of the precharge device 4
1 to 44 as precharge select signals 101 to 104.

The operation of the semiconductor memory device configured in this manner will be described below. First, address signals 121, 12
2, for example, the storage element array 5 of the first selector device 6.
1 is selected by the second selector device 7 as the data input cuff 01, and when the precharge signal 105 becomes /S I level while this data input cuff 01 is selected, the address signal 12
1 and 122, the precharge select signal 1[11 selected by the decoder 1 becomes low level, and the other precharge select signals 102 to 104 become high level. As a result, only the precharge section 41 corresponding to the storage element array 51 of the precharge device 4 performs precharging, and the other precharge sections 42 to 44 operate so as not to perform precharging. Among them, only the memory element column 51 selected by the second selector device 7 is precharged. Next, when the precharge signal 105 becomes low level, the output 128 of the inverter 8 becomes high level, and the decoder 2 sets only the address lines selected by the address signals 125 to 127 to high level. The signal readout line is selected by the selector device 6.7 according to the address signals 121-124, and finally the contents of the storage element selected by the address signals 121-127 are outputted to the data output cuff 05.

As described above, according to this embodiment, by precharging only the precharge sections 41 to 44 of the precharge device 4 including the signal readout line selected by the address signal, power consumption can be reduced and the power supply Noise and radiation can be easily reduced.

Note that this embodiment can be applied to a semiconductor memory device consisting of a read-only memory (ROM) or a random access memory (RAM).

Effects of the Invention As described above, according to the present invention, since precharging is performed only on a part of the precharging device including the signal readout line selected by the address signal, power consumption, power supply noise, and radiation can be reduced. can be easily realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the structure of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the structure of a conventional semiconductor memory device. 1.2.3... Decoder, 4... Precharge device, 5... Storage element array, 6.7... First and second
Selector device, 9... Synchronization device, 1[11-104.
...Precharge select signal, 105...Precharge signal, 121-127...Address signal, 705
...Data output.

Claims (1)

[Claims] 1) a precharge device that precharges a signal readout line, a selector that selects a signal readout line, and a decoder that causes only the precharge device connected to the signal readout line selected by the selector to perform a precharge operation;
A semiconductor memory device having a synchronization device for synchronizing a decoder output with a precharge select signal selectively supplied to a precharge device.