JPH03251912A - Electronic equipment with system clock switching function - Google Patents

Abstract

PURPOSE:To improve the working efficiency of an electronic equipment by switching automatically the frequency of a system clock in accordance with the ambient tempera ture. CONSTITUTION:When the temperature exceeds a set level, an alarm module 17 informs a CPU 10 of the comparison result showing a high temperature. Thus, the CPU 10 sets a selection signal 16 at logic '1'. A selection circuit 15 outputs selectively the clock signal given from an oscillation circuit 14 to the CPU 10 as a system clock 11. Thus, the CPU 10 works synchronously with the clock 11. The processing ability of the CPU 10 is deteriorated owing to a low working speed. However the working of the CPU 10 is stabilized owing to a margin secured in terms of timing. The signal 16 is set at logic '0' with a low temperature, and the circuit 15 outputs selectively the clock signal given from an oscillation circuit 13 to the CPU 10 as the clock 11. Thus, the processing ability of the CPU 10 is improved synchronously with the clock 11 having a rather high frequency. As a result, the processing ability of the CPU 10 can improve its processing ability and work effectively in a satisfactory temperature environment. When the environment is deteriorated, the processing ability is rather deteriorated. Thus, the stable working is secured with no occurrence of errors.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention relates to electronic equipment that operates in synchronization with a system clock, and particularly to achieve both equipment performance and reliability against changes in ambient temperature. This invention relates to a system clock switching method suitable for.

(Prior Art) Conventionally, in order to improve the processing speed of electronic devices, such as electronic computers, efforts have been made to improve the architecture and speed up the electronic circuits. To achieve this speedup,
In general, high-speed semiconductor elements are used to construct circuits that operate in synchronization with an extremely high-frequency system clock.

By the way, I, which is the core of semiconductors, especially electronic computers,
The operating characteristics of C (integrated circuit) vary depending on various factors. Therefore, in order to guarantee the stability and reliability of their products, manufacturers assume the worst possible environmental conditions under which computers will be used, and design them with margins to ensure normal operation under those conditions. I do. For example, temperature is the most familiar environmental condition. When the temperature is high, the operating speed of the IC decreases slightly, and when the temperature is low, the IC can operate at a higher speed. If a design without a timing margin is made based on the characteristics at room temperature without taking this into consideration, an error will occur when the temperature changes and the temperature reaches a high temperature state. In order to prevent this, we calculate various timings based on the IC characteristics at the upper limit of the computer's allowable temperature range, and then decide on a system clock frequency value that can guarantee reliable operation. This is done by designing. That is, the frequency of the system clock is fixed at a value assuming normal operation.

(Problem to be solved by the invention) As mentioned above, in conventional electronic devices such as electronic computers that have built-in electronic circuits that operate in synchronization with a system clock, the frequency of this system clock is set based on the assumption that the system clock is operating under normal conditions. , and has a certain processing capacity regardless of whether the ambient temperature is high or low. On the other hand, if it were possible to assemble a circuit that directly reflects the capabilities of ICs, etc., the processing capacity of electronic equipment would be, for example, if the processing capacity at room temperature is 100, then the processing capacity at high temperature would be 95. Processing capacity at low temperature is 10
5. In other words, in order to guarantee stable operation at high temperatures, conventional electronic devices have to settle for lower processing power than their actual value at room or low temperatures, and even if reliability is ensured, there are problems with device performance. Ta.

This invention was made in view of the above circumstances, and its purpose is to automatically switch the system clock frequency in accordance with changes in ambient temperature, so that equipment can To provide an electronic device having a system clock switching function that can operate with increased processing capacity and, when the temperature environment deteriorates, prioritize stable operation without causing errors and operate with slightly lower processing capacity. It is in.

[Structure of the Invention] (Means for Solving Problem i) The present invention provides a clock generation circuit that generates a plurality of clock signals with different frequencies in an electronic device that operates in synchronization with a system clock, and this clock generation circuit. a selection circuit that selects one of the plurality of clock signals generated by the system clock according to the selection signal for generation and output of the system clock; and a selection circuit that detects the surrounding FM temperature and sets the state of the selection signal according to the detected temperature. The system is characterized in that the frequency of the system clock is switched in accordance with temperature changes. The above-mentioned clock generation circuit may include a plurality of oscillation circuits that generate clock signals of different frequencies, or a multi-bit binary counter that performs counting operations based on oscillator output, and at least a portion of the multi-bit output is A binary counter used as a clock signal, and a decoding circuit that decodes the output of this binary counter and outputs a signal to initialize the counter when the output value reaches a value determined by the state of the above selection. It is possible to configure it by having the following.

(Operation) According to the above configuration, one of the plurality of clock signals having different frequencies is selected from the selection circuit according to the state of the selection signal, and is used as the system clock as it is or corresponds to the selected clock signal. Used for generating the frequency system clock. Since the state of the selection signal is switched and set in accordance with the ambient temperature, the frequency of the system clock is switched in accordance with temperature changes. As a result, for example, when the temperature is at ambient temperature or below room temperature, electronic equipment operates with a higher frequency system clock to increase its processing power, and when the temperature is high, it switches to a lower system clock.
Prioritizing stable operation without errors, it is possible to operate with reduced processing capacity.

In addition, in order to generate multiple clock signals with different frequencies, in addition to the configuration using oscillation circuits for the number of clock signals,
By using a configuration using a multi-bit binary counter, the clock generation circuit can be simplified. In a configuration using this binary counter, the counter is decoded by decoding the 8 counters and initializing the counter when its output value (count value) reaches a value determined by the state of the selection signal. It can be operated as a desired n-ary counter, and it is possible to output clock signals of various frequencies corresponding to the state of the selection signal from each output bit position of the counter.

(Embodiment) FIG. 1 shows a block configuration of a computer according to an embodiment of the present invention. In the figure, 10 is a CPU that forms the core of the computer and performs calculations and various processes in synchronization with the system clock 11, and 12 is a CPU (a system clock generation circuit that generates a system clock II used in one section). The system clock generation circuit 12 has an oscillation circuit 13 that generates a clock signal for system clock generation with a slightly higher frequency that is used to increase processing capacity when the ambient temperature is below normal temperature. It is equipped with an oscillation circuit 14 that generates a clock signal for generating a system clock of a slightly lower frequency that is used for stable operation in the state of , and a selection circuit 15. The system clock 11 selects either one of the clock signals generated by
It is selected as follows.

Here, when the selection signal 1G is "0", the oscillation circuit 1
Clock signal from 3 or oscillation circuit 1 if “1”
The clock signal from 4 can be selected respectively. 17 is an alarm module having an ambient temperature detection function. The alarm module 17 compares and determines whether the detected ambient temperature is higher or lower than the set temperature, and notifies the CPU10 of the result. CPU10
has a function of setting the state of the selection signal 16 according to the temperature comparison result of the alarm module 17.

Next, the operation of the configuration shown in FIG. 1 will be described using as an example the case where the system clock 11 has a cycle of 60 ns when the temperature is high, and the cycle of the system clock 11 when the temperature is low (below room temperature) is 50 ns.

First, at startup (initial state) when the electronic computer shown in FIG. Set. Selection circuit 1
5 is an oscillation circuit 14 in response to a selection signal 16 of logic “1”.
Select a clock signal with a period of 60 ns from . The 60 ns cycle clock signal selected by the selection circuit 15 is applied to the CPU10 as the system clock 11.
be shared. As a result, the CPU 10 starts operating in synchronization with the system clock 11 having a period of 60 ns, and the system clock 11 having a slightly lower frequency guarantees operation for a period until the CPU 10 starts functioning normally.

Now, when CPU 10 starts functioning normally, the CPU
The U 10 switches and sets the state of the selection signal 16 according to the temperature comparison result of the alarm module 17. First, when the ambient temperature is higher than the set temperature, the alarm module I7
The CPU 10 is notified of the temperature comparison result indicating a high temperature. When the temperature comparison result of the alarm module 17 indicates a high temperature, the CPU 1O sets the selection signal 16 to the selection circuit 15 to logic "1" as in the above startup. In this case, the selection circuit 15 selects the clock signal with a period of 60 ns from the oscillation circuit 14 as the system clock 1.
1 and selectively outputs it to CPU1(+.This causes the CPU
Similarly to the startup described above, Ul0 operates in synchronization with the system clock 11 having a slightly lower frequency with a period of 60 ns. In this state, although the processing capacity decreases because the operation speed becomes low, there is a margin in terms of timing, so stable operation can be expected even under high temperatures.

On the other hand, when the ambient temperature is lower than the set temperature, the alarm module 17 notifies the CPU10 of a temperature comparison result indicating a low temperature. When the temperature comparison result of the alarm module 17 indicates a low temperature, the CPU 10 sets the selection signal 1B to the selection circuit 15 to logic "0", contrary to the above-mentioned startup or high temperature. In this case, the selection circuit 15 selectively outputs the clock signal with a period of 50 ns from the oscillation circuit 13 to the CPU10 as the system clock 11.

As a result, the CPU 10 can operate with increased processing capacity in synchronization with the system clock 11 having a slightly higher frequency of 50 ns.

As described above, according to the configuration shown in FIG.
O) can be operated with increased processing capacity, and stable operation with sufficient timing can be achieved by switching the frequency of the system clock 11 to a lower value in a harsh environment under high temperatures. Incidentally, electronic computers of the minicomputer class and above are often used in environments that are well controlled, including temperature. For this reason, the temperature described as the upper limit temperature in the product specifications is
This only happens when the air conditioner breaks down, and this kind of abnormal situation does not occur often.

Therefore, it is wasteful to assume stable operation under such abnormal conditions and to operate with reduced processing capacity even under normal conditions as in the past. On the other hand, in the configuration shown in Figure 1,
Under normal conditions, it operates with increased processing capacity, but only when the air conditioner breaks down and the temperature environment becomes poor, the processing capacity is reduced and priority is given to stable operation until the air conditioner is repaired and the temperature environment returns to a good level. You can try to use it. therefore,
For the user, this is equivalent to installing an electronic computer with more advanced processing capabilities, and for the manufacturer, it is equivalent to providing a highly reliable computer that is resistant to temperature fluctuations.

In the configuration shown in FIG. 1, the CPU 10 switches and sets the state of the selection signal 16 according to the temperature comparison result of the alarm module I7, but as shown in FIG.
A temperature detection circuit 21 independent from Ul0 is provided, and this temperature detection circuit 21 directly outputs the selection signal 16 to the selection circuit 15.
It is also possible to switch and set the state of. That is, in the configuration shown in FIG. 2, the ambient temperature is detected in the temperature detection circuit 21. The temperature detection circuit 21 compares and determines whether the detected ambient temperature is higher or lower than the set temperature, and based on the determination result, if the temperature is high, the logic is "1"; if the temperature is low, the logic is "1".
A selection signal 16 of "0" is output to the selection circuit I5.

The subsequent operation is similar to the configuration shown in FIG. In FIG. 2, the same parts as in FIG. 1 are given the same reference numerals. Further, for convenience of explanation, the same reference numerals are also given to the CPU.

Now, in the configurations of FIGS. 1 and 2, clock signals of different frequencies are transmitted through independent oscillation circuits (13, 14).
However, it is also possible to generate a plurality of clock signals with different frequencies using one binary counter. A system clock generation circuit using this binary counter will be explained with reference to FIGS. 3 and 4. Note that Figure 3 is the same as Figure 1.
4 corresponds to the structure in FIG. 2, and the same parts as in FIGS. 1 and 2 are given the same reference numerals and detailed explanations are omitted.

In FIGS. 3 and 4, 30 is a system clock generation circuit corresponding to the system clock generation circuit 12 in FIG. The system clock generation circuit 30 includes a crystal oscillator 31 and a clock generation circuit 32 that generates two types of clock signals with different frequencies based on the output pulse signal from the crystal oscillator 31. This clock generation circuit 32 includes, for example, a 3-bit binary counter 33 that counts the output pulse signal from the crystal oscillator 31, and outputs Q2 (MSB), Ql, and Q of the counter 33.
O (LSB) is decoded and the value is determined by the state (0 or 1) of the selection signal 1B (selection signal 16 from CPU10 in Figure 3, selection signal 16 from temperature detection circuit 2I in Figure 4). In this case, the counter 33 has a value of 0, for example.
'', and a decoder 35 that outputs a preset signal 34 for presetting. In this embodiment, the decoder 35 outputs "Q2" if the selection signal 16 is "0".
If it is "1" when QI QO' - "111", an active preset signal 34 is output when "Q2 QI QO" - "100". The system clock generation circuit 30 further includes a selection circuit 36 that selects either the Q1 output or the Q2 output of the binary counter 33 in response to the selection signal 16, and a selection circuit 36 that selects one of the Q1 output and Q2 output of the binary counter 33, and a signal (clock signal) selected by the selection circuit 36. A flip-flop (hereinafter referred to as F/F) 37 is provided for shaping the clock into a double-period clock.

Next, the operation of the configuration shown in FIGS. 3 and 4 will be explained using the crystal oscillator 3.
Taking as an example the case where the output pulse signal from 1 has a period of 10 ns, the system clock 11 at high temperature has a period of 100 ns, and the system clock 11 at low temperature has a period of 80 ns, the timing charts in FIGS. 5(a) and (b) are shown. Refer to and explain. Note that FIG. 5(a) is a timing chart when the selection signal 16 is "0", and FIG. 5(b) is a timing chart when the selection signal 16 is "1".

First, the 3-pit No. 1 binary counter 33 in the clock generation circuit 32 performs a counting operation using an output pulse signal with a period of 10 ns from the crystal oscillator 31.

A 3-bit output representing the count value of the binary counter 33, ie, outputs Q2 to QO, is supplied to a decoder 35. This decoder 35 receives a selection signal 16 (in FIG.
A selection signal 16 from 0 (in FIG. 4, a selection signal 16 from the temperature detection circuit 21) is also supplied. The selection signal 16 is "0" when the temperature is low, as is clear from the above embodiment.

When the selection signal 16 is “0”, the decoder 35 outputs Q2 to Q1 of the binary counter 33 as “Q2 QI
When QO-1 is "111" (when the count value is 7), an active preset signal 34 is output to the binary counter 33.

As a result, the binary counter 33 is preset to the value "0". That is, the binary counter 33 receives the selection signal I
At low temperatures when the value is 6 or 0, it operates as an octal counter as shown in FIG. 5(a). In this case, the period of the Ql ratio output of the binary counter 33 is four times that of the output pulse signal of the crystal oscillator 31, that is, 40 ns.

The Ql and Q2 outputs of the binary counter 33, which operates as an octal counter at low temperatures, are supplied to the selection circuit 36. When the selection signal 16 is "0" as in this embodiment, the selection circuit 36 selects the Q1 output of the binary counter 33, that is, the clock signal with a period of 4Qns, as shown in FIG. 5(a). . A clock signal with a period of 40 ns (Q1 output of the binary counter 33) selected by the selection circuit 36 is supplied to the F/F 37, and the fifth
As shown in Figure (a), the clock signal with double period, that is, 8
The clock signal is shaped into a clock signal with a period of 0 ns, and is supplied to the CPU IQ as a system clock II for low temperatures.

- When the power and high temperature are high, the selection signal 16 (in Fig. 3, the CPU1
The selection signal 16 from 0, the selection signal 16 from the temperature detection circuit 21 in FIG.
The active preset signal 34 is output to the l/inary counter 33 when the Q2 to Q1 outputs of "Q2 QIQO" - "100" (when the count value is 4).

As a result, the binary counter 33 is preset to the value "0". That is, the binary counter 33 receives the selection signal 1
At low temperatures when the value is 6 or 1, it operates as a quinary counter as shown in FIG. 5(b). In this case, the Q2 output of the binary counter 33 has a period five times that of the output pulse signal of the crystal oscillator 31, that is, 50 ns.

The Ql and Q2 outputs of the binary counter 33, which operates as a quinary counter at high temperatures, are supplied to the selection circuit 36. The selection circuit 36 selects the Q2 output of the binary counter 33, that is, the period 50n, as shown in FIG.
Select the clock signal of s. A clock signal with a period of 50 ns (Q2 output of the binary counter 33) selected by the selection circuit 36 is supplied to the F/F 37,
As shown in FIG. 5(b), the CPU10 is shaped into a clock signal with a double period, that is, a clock signal with a period of 100 ns, and is used as a system clock It for high temperature operation with a slightly lower frequency that allows more margin in terms of timing compared to low temperature operation. is supplied to

The above describes the case where the system clock is output by switching two types of clock signals with different frequencies depending on whether the ambient temperature is higher or lower than the set temperature based on one set temperature, but this is not the only case. do not have. For example, it is possible to set three or more temperature ranges and output the system clock by switching between three or more types of clock signals with different frequencies depending on which temperature range the ambient temperature is in. Further, the present invention is applicable not only to electronic computers but also to general electronic devices having electronic circuits that operate in synchronization with a clock.

[Effects of the Invention] As detailed above, according to the present invention, by automatically switching the system clock frequency in accordance with changes in ambient temperature, the device If the temperature environment deteriorates, stable operation without errors can be prioritized, and the processing capacity can be reduced slightly.

[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2 is a block diagram showing another embodiment of the invention, and Fig. 3 is a block diagram showing the configuration of Fig. 1. A block configuration diagram showing an embodiment in which a system clock generation circuit using a binary counter is applied. FIG. 4 is a block configuration diagram showing an embodiment in which a system clock generation circuit using a binary counter is applied to the configuration shown in FIG. 2. 5 are timing charts for explaining the operation of the configurations shown in FIGS. 3 and 4. FIG. lO...CPU511...System clock, 12
．． 30... System clock generation circuit, 13.14.
...Oscillation circuit, 15, 36...Selection circuit, 16...
Selection signal, 17... Alarm module, 21... Temperature detection circuit, 31... Crystal oscillator, 32... Clock generation circuit, 33... Pinary count, 35... Decoder, 37... Flip-flop P (F/F). Wll Ward

Claims (3)

[Claims] (1) In an electronic device that operates in synchronization with a system clock, there is a clock generation circuit that generates multiple clock signals with different frequencies, and one of the multiple clock signals generated by this clock generation circuit is connected to the system clock. A selection circuit that selects a generated output according to a selection signal; and means that detects ambient temperature and sets the state of the selection signal according to the detected temperature, and the system is configured to follow temperature changes. An electronic device having a system clock switching function characterized by switching the clock frequency. (2) The electronic device having a system clock switching function according to claim 1, wherein the clock generation circuit includes a plurality of oscillation circuits that generate the clock signals of different frequencies. (3) The clock generation circuit is a multi-bit binary counter that performs counting operation based on an oscillator output,
At least a part of the multi-bit output is used as the clock signal by a binary counter, and the output of this binary counter is decoded, and when the output value becomes a value determined by the state of the selection signal, the counter is initialized. 2. The electronic device having a system clock switching function according to claim 1, further comprising a decoding circuit that outputs a signal for switching the system clock.