JPH03250649A - Multi-layer organic film circuit board - Google Patents
Multi-layer organic film circuit boardInfo
- Publication number
- JPH03250649A JPH03250649A JP2045537A JP4553790A JPH03250649A JP H03250649 A JPH03250649 A JP H03250649A JP 2045537 A JP2045537 A JP 2045537A JP 4553790 A JP4553790 A JP 4553790A JP H03250649 A JPH03250649 A JP H03250649A
- Authority
- JP
- Japan
- Prior art keywords
- organic film
- dielectric constant
- circuit board
- conductive paste
- film circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims abstract description 5
- 239000000126 substance Substances 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 abstract description 5
- 229910052763 palladium Inorganic materials 0.000 abstract description 4
- 239000004642 Polyimide Substances 0.000 abstract description 3
- 229920002492 poly(sulfone) Polymers 0.000 abstract description 3
- 229920001721 polyimide Polymers 0.000 abstract description 3
- 229910002696 Ag-Au Inorganic materials 0.000 abstract description 2
- 229910002710 Au-Pd Inorganic materials 0.000 abstract description 2
- 229910052802 copper Inorganic materials 0.000 abstract description 2
- 229910052737 gold Inorganic materials 0.000 abstract description 2
- 230000010354 integration Effects 0.000 abstract description 2
- 229910052804 chromium Inorganic materials 0.000 abstract 1
- 229910052759 nickel Inorganic materials 0.000 abstract 1
- 229910052709 silver Inorganic materials 0.000 abstract 1
- 239000010408 film Substances 0.000 description 16
- 239000000758 substrate Substances 0.000 description 6
- 239000000919 ceramic Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- -1 polytetrafluoroethylene Polymers 0.000 description 3
- 239000004695 Polyether sulfone Substances 0.000 description 2
- 229920006393 polyether sulfone Polymers 0.000 description 2
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 2
- 239000004810 polytetrafluoroethylene Substances 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野１
本発明は、集積度の高いＬＳＩ実装用基板に関し、特に
、直接ＬＳＩを実装でき、微細多層配線か可能な多層有
機フィルム回路基板に関するものである。[Detailed Description of the Invention] [Industrial Application Field 1] The present invention relates to a highly integrated LSI mounting board, and particularly to a multilayer organic film circuit board on which an LSI can be directly mounted and capable of fine multilayer wiring. be.
［従来の技術およびその課題］
従来、集積度の高いＬＳＩの実装用基板としては、直接
ＬＳＩを実装でき、かつ微細多層配線が可能な多層セラ
ミック基板が用いられていた。[Prior Art and its Problems] Conventionally, multilayer ceramic substrates have been used as mounting substrates for highly integrated LSIs, on which LSIs can be directly mounted and fine multilayer wiring is possible.
しかしながら、上述した従来の多層セラミック基板は、
誘電率（ＡＳＴ）ｌ ０１５０の測定方法において、１
０６Ｈ２の周波数での値〉か７〜８程度なので、ＬＳＩ
を実装し、コンピュータ等に組み込んだ場合、高速演緯
時の遅延時間か長くなるという欠点かある。即ち、多層
回路基板を含めた導体内の電気信号伝播速度（Ｖ）は次
式で示される。However, the above-mentioned conventional multilayer ceramic substrate
In the method for measuring dielectric constant (AST) l 0150, 1
The value at the frequency of 06H2> is about 7 to 8, so the LSI
When implemented and incorporated into a computer, etc., there is a drawback that the delay time during high-speed latitude operation becomes long. That is, the electric signal propagation velocity (V) within a conductor including a multilayer circuit board is expressed by the following equation.
（ただし、Ｃ：光速、ε：誘電率、に：定数）すなわち
誘電率（ε）が小さいほど、電気信号伝播速度（Ｖ）が
速くなり、高速演算が実現できる。また、多層セラミッ
ク基板は、厚みが厚く、重量も重いので、扱い難く、か
つ耐衝撃性に弱く、破損しやすいという欠点がある。(where C: speed of light, ε: dielectric constant, and N: constant) That is, the smaller the dielectric constant (ε), the faster the electric signal propagation speed (V) becomes, and high-speed calculation can be realized. Furthermore, multilayer ceramic substrates are thick and heavy, making them difficult to handle, and having low impact resistance and being easily damaged.
本発明は、以上述べたような従来の事情に対処してなさ
れたもので、電気信号伝播の遅延時間が短く、かつ軽重
量で取り扱いの容易な多層回路基板を提供することを目
的とする。The present invention has been made in response to the conventional circumstances as described above, and an object of the present invention is to provide a multilayer circuit board that has a short delay time in electrical signal propagation, is light in weight, and is easy to handle.
［課題を解決するための手段］
本発明は、誘電率３．５以下、熱変形温度１５０ ’Ｃ
以上の物質からなる有機フィルム層を介して複数の導体
層を積層したことを特徴とする多層有機フィルム回路基
板である。[Means for Solving the Problems] The present invention has a dielectric constant of 3.5 or less and a heat distortion temperature of 150'C.
This is a multilayer organic film circuit board characterized in that a plurality of conductor layers are laminated via organic film layers made of the above substances.
［作用］
高集積度ＬＳＩの基板への実装では、ＬＳＩヘアチップ
を基板上に直接搭載するＣＯＢ （Ｃｈａｐｏｎ Ｂｏ
ａｒｄ）技術か採用されている。ベアチップと基板との
接続には、ワイヤボンディング法等が必要となってくる
。ワイヤボンディング法では、チップと基板を金等のワ
イヤーを介して、熱と荷重で圧着接続される。従って、
これらの接続時には、熱が伴うため、部材には耐熱性が
要求される。通常の熱および超音波併用ホンディングの
条件下では、熱変形温度が１５０℃以上のフィルムであ
れば使用上支障はきたさない。[Function] When mounting a highly integrated LSI on a board, COB (Chapon Bo), in which the LSI hair chip is directly mounted on the board, is used.
ard) technology has been adopted. A wire bonding method or the like is required to connect the bare chip and the substrate. In the wire bonding method, a chip and a substrate are crimped and connected via a wire made of gold or the like using heat and load. Therefore,
Since heat is generated when these connections are made, the members are required to have heat resistance. Under normal thermal and ultrasonic honding conditions, any film with a heat deformation temperature of 150° C. or higher will not pose any problem in use.
なあ、この熱変形温度は、ＡＳＴＭ Ｄ６４８の測定方
法において、１８．６ Ｋｇｆ／ｃｍ２の荷重での値を
用いるものとする。For this heat distortion temperature, the value at a load of 18.6 Kgf/cm2 is used in the measurement method of ASTM D648.
また、多層回路基板の誘電率か３．５以下であれば、電
気信号伝播の遅延時間を実用上支障かない程度に短くす
ることができる。Further, if the dielectric constant of the multilayer circuit board is 3.5 or less, the delay time of electrical signal propagation can be shortened to a level that does not cause any practical problems.
本発明においては、上記のような熱変形温度と誘電率を
有する有機フィルムを導体層間に用いているので、上述
した機能を有する以外に、厚みを薄くすることができ、
しかも軽重量で取り扱いか容易になる。In the present invention, since an organic film having the above-mentioned heat distortion temperature and dielectric constant is used between the conductor layers, in addition to having the above-mentioned functions, the thickness can be reduced.
Moreover, it is light in weight and easy to handle.
このような誘電率３．５以下、かつ熱変形温度１５０℃
以上の条件を満足する低誘電率有機フィルムとしては、
例えば、ポリテトラフルオロエチレン、ポリイミド系、
ポリスルホン、ポリエーテルスルホン、ビスマレイミド
トリアジン等が挙げられる。Such a dielectric constant of 3.5 or less and a heat distortion temperature of 150℃
As a low dielectric constant organic film that satisfies the above conditions,
For example, polytetrafluoroethylene, polyimide,
Examples include polysulfone, polyethersulfone, bismaleimidotriazine, and the like.
［実施例］
次に、本発明の実施例について図面を参照して説明する
。[Example] Next, an example of the present invention will be described with reference to the drawings.
第１図は、本発明の一実施例の構成図である。FIG. 1 is a configuration diagram of an embodiment of the present invention.
第２図は、これらの構成部材を積層した多層有機フィル
ム回路基板実装の一例を示す。両図に示すように、本発
明の多層回路基板は、３．５以下の低誘電率で、かつ熱
変形温度か１５０ ’Ｃ以上の耐熱性を有する有機フィ
ルム１を作成し、このフィルム１上にバイアホール２を
おけ、さらに導電性ベスト３にて配線パターンを印すリ
し、それらを複数層積層した構成となっている。低誘電
率有機フィルムとしては、ポリテトラフルオロエチレン
、ポリイミド系、ポリスルホン、ポリエーテルスルホン
、ビスマレイミドトリアジン等を用いることかできる。FIG. 2 shows an example of mounting a multilayer organic film circuit board in which these constituent members are laminated. As shown in both figures, in the multilayer circuit board of the present invention, an organic film 1 having a low dielectric constant of 3.5 or less and a heat resistance of 150' C or more at a heat distortion temperature is prepared, and the organic film 1 is coated on this film 1. A via hole 2 is placed in the top, a wiring pattern is further marked with a conductive vest 3, and a plurality of layers are laminated. As the low dielectric constant organic film, polytetrafluoroethylene, polyimide, polysulfone, polyethersulfone, bismaleimide triazine, etc. can be used.
フィルムの厚みとしては、１０〜３００柳、好ましくは
３０〜１００珈が適切な厚みである。バイアホールは、
パンチ、ドリル等にて容易にあけることができる。The appropriate thickness of the film is 10 to 300 mm, preferably 30 to 100 mm. The via hole is
It can be easily opened with a punch, drill, etc.
導電性ペーストとしては、Ｐｔ、 Ａｕ−１）ｔ。As the conductive paste, Pt, Au-1)t.
Ａｕ−Ｐｄ−Ｐｔ、Ａｇ−Ｐｄ、Ａｕ−Ｐｄ。Au-Pd-Pt, Ag-Pd, Au-Pd.
Ｐｄ、ＡＵ、Ａｇ−Ａｕ、Ａｃｔ、Ｃｕ、Ｎ １゜Ｃｒ
等を主成分としたものを用いることができる。Pd, AU, Ag-Au, Act, Cu, N 1゜Cr
It is possible to use a material containing etc. as the main component.
この多層有機フィルム回路基板上に、第２図に示すよう
に、ＬＳＩヘアチップ４を搭載し、ワイヤ５を介して基
板と接続させる。As shown in FIG. 2, an LSI hair chip 4 is mounted on this multilayer organic film circuit board and connected to the board via wires 5.
本実施例においては、基板へのワイヤホンディングを何
ら支障なく行うことができ、かつ高速演算時の遅延速度
が短くなると共に、有機フィルムを用いているので軽重
量でコンパクトな回路基板か得られる。In this example, wire bonding to the board can be performed without any problems, the delay speed during high-speed calculation is shortened, and since an organic film is used, a light weight and compact circuit board can be obtained. .
［発明の効果］
以上説明したように、本発明の多層回路基板は、集積度
を保持したまま直接ＬＳＩの実装かでき、微細多層配線
も可能となると同時に、コンピュタ等の電気信号伝播の
遅延時間を短くてきる効果がある。[Effects of the Invention] As explained above, the multilayer circuit board of the present invention allows LSI to be directly mounted while maintaining the degree of integration, enables fine multilayer wiring, and at the same time reduces the delay time of electrical signal propagation in computers, etc. This has the effect of making it shorter.
また、有機薄型フィルムを積層しているので、厚みも薄
く、重量も軽くなり、回路基板をコンパクトにてきると
いう効果もある。Additionally, since organic thin films are laminated, it is thinner and lighter in weight, which also has the effect of making the circuit board more compact.
第１図は本発明の一実施例の構成図、第２図は第１図実
施例の多層有機フィルム回路基板実装の。
−例でおる。
１・・・有機フィルム
２・・・バイアホール
３・・・導電性ペ
スト
４・・・ヘアチップ
５・・・ワイヤFIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a diagram showing the mounting of the multilayer organic film circuit board of the embodiment of FIG. -I'll give you an example. 1... Organic film 2... Via hole 3... Conductive paste 4... Hair chip 5... Wire
Claims (1)
質からなる有機フィルム層を介して複数の導体層を積層
したことを特徴とする多層有機フィルム回路基板。(1) A multilayer organic film circuit board characterized in that a plurality of conductor layers are laminated via an organic film layer made of a substance having a dielectric constant of 3.5 or less and a heat distortion temperature of 150° C. or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2045537A JPH03250649A (en) | 1990-02-28 | 1990-02-28 | Multi-layer organic film circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2045537A JPH03250649A (en) | 1990-02-28 | 1990-02-28 | Multi-layer organic film circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03250649A true JPH03250649A (en) | 1991-11-08 |
Family
ID=12722131
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2045537A Pending JPH03250649A (en) | 1990-02-28 | 1990-02-28 | Multi-layer organic film circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03250649A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5969426A (en) * | 1994-12-14 | 1999-10-19 | Mitsubishi Denki Kabushiki Kaisha | Substrateless resin encapsulated semiconductor device |
-
1990
- 1990-02-28 JP JP2045537A patent/JPH03250649A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5969426A (en) * | 1994-12-14 | 1999-10-19 | Mitsubishi Denki Kabushiki Kaisha | Substrateless resin encapsulated semiconductor device |
| US6071755A (en) * | 1994-12-14 | 2000-06-06 | Mitsubushi Denki Kabushiki Kaisha | Method of manufacturing semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6995322B2 (en) | High speed circuitized substrate with reduced thru-hole stub, method for fabrication and information handling system utilizing same | |
| JP2966972B2 (en) | Semiconductor chip carrier, module mounting the same, and electronic device incorporating the same | |
| US4754371A (en) | Large scale integrated circuit package | |
| US4539622A (en) | Hybrid integrated circuit device | |
| JP3004071B2 (en) | Package for integrated circuit | |
| JPH0220848Y2 (en) | ||
| JP2002252297A (en) | Electronic circuit device using multilayer circuit board | |
| JP2011139083A (en) | Multi-chip electronic package having laminate carrier and assembly of the package | |
| JPH0325082B2 (en) | ||
| JPH01307236A (en) | Electronic device assembly and its manufacture | |
| US5350886A (en) | Mounting substrate | |
| KR950028575A (en) | Power hybrid integrated circuit device | |
| JPS5994441A (en) | Semiconductor device | |
| US6717276B2 (en) | Two-metal layer ball grid array and chip scale package having local interconnects used in wire-bonded and flip-chip semiconductor assembly | |
| JPH03250649A (en) | Multi-layer organic film circuit board | |
| JPH05144971A (en) | Structure of chip carrier | |
| JPH07202053A (en) | Semiconductor device | |
| JPS6319896A (en) | Multilayer interconnection board | |
| JPH0462457B2 (en) | ||
| JPH07312380A (en) | Device and preparation with thin film overlay that interconnects bond pad of semiconductor device to lead framethat is,flex circuit | |
| JPH11121934A (en) | Low loss multilayered wiring board | |
| JPH0312988A (en) | Metal conductor thick film printed wiring board | |
| JPH0425144A (en) | Semiconductor device using tape for three-layer tab and manufacture of tape for three-layer tab | |
| JPS62271442A (en) | Hybrid integrated circuit | |
| JPS61276398A (en) | Multilayer circuit board |