JPH0325063B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in an unbalanced transmission circuit used for transmitting and receiving data signals in an air conditioning control device or the like.

[Prior art]

In conventional air conditioning control equipment, when data signals are transmitted between the control unit and terminal devices such as sensors or actuators, it is done through a data collection panel, and each terminal device and data collection panel Since each individual wiring is used to connect between the two, the amount of wire required for wiring increases,
This has disadvantages such as increased wiring man-hours.

Therefore, in recent years, a system has been proposed in which the control unit and each terminal are directly connected via a common transmission path. "Balanced Transmission Circuit" (Utility Application No. 57-56691) has been disclosed.

However, in such an unbalanced transmission circuit,
If the output transistor continues to be on for some reason, the common transmission path will remain occupied by the terminal device in this state, and communication between other terminal devices and the control section will be interrupted. This results in the disadvantage that it is impossible to transmit and receive data signals between the two.

[Summary of the invention]

The purpose of the present invention is to eliminate such drawbacks of the conventional technology at once, and to detect this and disconnect the output transistor from the transmission line if the output transistor continues to be on for a certain period of time or more. The present invention provides an extremely effective unbalanced transmission circuit with a fault detection function.

〔Example〕

Hereinafter, details of the present invention will be explained with reference to figures showing examples.

Figure 1 is a circuit diagram showing the configuration, and the control unit CT
and each terminal device TE ₁ to _{TE o} are connected in parallel by a power line L ₁ , a signal line L ₂ and a common line L ₃ that constitute a common transmission path, and from the power supply E of the control unit CT,
A power supply voltage is applied between the power supply line _L1 and the common line _L3 .

However, the control unit CT and the terminals TE ₂ to _{TE o} are
It has the same configuration as the terminal TE ₁ , and uses the signal line L ₂ in a time-sharing manner, and connects the control unit CT and each terminal.
Data signals are transmitted and received individually between TE ₁ and TE _o .

That is, for example, if transmission data SD occurs in terminal TE ₁ , its "H" (high level),
Drive transistor depending on “L” (low level)
Q ₁ turns on and off, and the bias voltage applied to the base of output transistor Q ₂ by resistor R ₁ is varied via resistor R ₂ .
The transistor Q2 whose emitter-collector is inserted between the power supply line _L1 and _the transistor _Q3 via the current limiting resistor _R3 is also turned on and off, and the signal line is accordingly turned on and off. The voltage level of _L2 repeats "H" and "L", and the data signal is transmitted.

However, between the emitter and collector of transistor Q ₃ for switching is inserted between transistor Q ₂ and signal line L ₂ , and the transistor
The voltage level at the connection point (level judgment point) between Q ₂ and Q ₃ is applied to the control comparator CP ₁ , and the resistors R ₄ and R ₅
When the voltage level at _the connection point becomes "H", a comparison output _of "H" is generated. ₇ , the transistor Q ₃ through the diode D ₁ and the constant voltage diode ZD to facilitate turning off the transistor Q ₃
However, if the on/off state of transistor Q ₂ is normal, the terminal voltage of capacitor C ₁ will not rise above a predetermined value, and when transistor Q ₂ is on, the transistor “L” is the voltage required for _Q3 to turn on.
and the collector of the transistor Q ₃ is connected to the common line L ₃ via the matching resistor R _L1 connected between the signal line L ₂ and the common line L ₃ . When transistor Q ₂ is turned on and off, transistor Q ₃ is also turned on and off.

On the other hand, in the reception state where the transmission data SD is "L" and the transistor _Q2 is off,
If there is a transmission from the control unit CT, the voltage level of the signal line _L2 repeats "H" and "L", which causes the resistor
It is applied to the receiving comparator _CP2 via _R8 , where it is compared with the above-mentioned reference voltage to detect the received signal, and the comparison output is sent out as received data RD.

Note that the comparator CP ₂ is given positive feedback by the resistor R ₉ and is given hysteresis characteristics, so once the comparison output is generated, even if the voltage level of the received signal changes slightly, , the comparative output is maintained stably.

In addition, among the matching resistors R _L0 , R _L1 to R _Lo , if R _L0 is set to R _L0 ≪ R _L1 to _{R Lo} , the terminal
Even if TE ₁ to _{TE o} increase or decrease, their parallel combined resistance value remains constant, and a data signal at a constant voltage level is always sent to signal line L ₂ .

In contrast to the above, due to the transmission data SD being maintained at “H” and the transistor Q ₂ being short-circuited, the transistor Q ₂
If the on state continues for a certain period of time or more, the transistor _Q3 maintains the off state and disconnects the transistor _Q2 from the signal line _L2 .

In other words, as shown in Figure 2, which shows the waveforms of each part in Figure 1, the voltage level at the connection point (a) and the voltage level at the signal line _L2 (b) change simultaneously depending on whether transistor _Q2 is turned on or off. However, the transistor
When Q ₂ remains on, capacitor C ₁ is continuously charged by the comparison output of comparator CP ₁ “H” for a certain period of time determined by the time constant of resistor R ₆ and capacitor C ₁ . After T, capacitor
When the terminal voltage (c) of C ₁ exceeds a predetermined value, the diode D ₁ is turned off and the bias voltage of the transistor Q ₃ is cut off, so that the transistor Q ₃ remains in the off state.

Note that the resistor _R10 is provided to stabilize the input voltage of the comparator _CP1 when the transistor _Q3 is turned off.

Therefore, if the comparison output of the comparator _CP1 continues to be "H" for a certain period of time T or more, the transistor _Q2 is disconnected from the signal line _L2 , and the voltage level (b) becomes "L".
Then, data signals can be freely transmitted and received between the other terminals TE ₂ to _{TE o} and the control unit CT.

However, the conductivity of the transistors Q ₁ to _{Q 3} may be selected depending on the polarity of the signal line L ₂ , and the comparator
The same effect can be achieved by using another voltage discrimination circuit as CP ₁ , and various modifications are possible, such as using a timer or the like as a time limit circuit.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, by adding a simple circuit, an output transistor that is continuously on is automatically disconnected from the signal line, and the output transistor is automatically disconnected from the signal line. Since the influence is eliminated, great effects can be obtained in unbalanced transmission circuits connected to a common transmission path.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing waveforms at various parts in FIG. _Q1 to _Q3 ...transistor, _R1 to _R9 , R _L0 , R _L1
~R _Lo ...Resistor, C ₁ ...Capacitor, CP ₁ ,
CP ₂ ... Comparator, L ₁ ... Power line, L ₂ ... Signal line,
L ₃ ...Common line.

Claims (1)

[Claims] 1. Consisting of a control unit and a plurality of terminal devices connected in parallel to the control unit by a power line, a signal line, and a common line, the control unit supplies power to each terminal device. It is an unbalanced transmission circuit that performs data transmission between each terminal and each terminal, and its emitter is connected to the power supply line through a resistor, and its collector is connected to the level judgment point. a transistor and its emitter connected to the level determination point,
a switching transistor whose collector is connected to the signal line and turns on and off together with the output transistor; a matching resistor connected between the signal line and the common line; a receiving comparator having a hysteresis characteristic to determine the voltage level at the connection point between the resistor and the signal line; and a receiving comparator having a predetermined level comparison output when the voltage level at the level determination point is higher than a reference voltage level. The control section and the timer circuit maintain the switching transistor in an off state when receiving a comparison output of a predetermined level from the comparator continuously for a predetermined period of time or more. An unbalanced transmission circuit with a failure detection function, characterized in that it is provided in all of the terminals.