JPH03250467A - (controlling) method for control device in information recording disk device - Google Patents

Abstract

PURPOSE:To improve the function of the control device without increasing its cost by using a disk whose recording tracks are divided into plural sectors in the case of connecting the control device between a host computer and an information recording disk and recording/reproducing information in/from each sector. CONSTITUTION:Elements to be controlled by a microcomputer 3 are constituted of three elements, i.e. a DMA controller 4, an ECC 6 and a formatter 7. In the case of reproducing information by using the elements, the formatter 7 is driven by the controller 4 prior to the processing operation of the 1st sector by using registers 4a, 4b built in the controller 4 and registers 6a, 6b built in an ECC 6 and registers 7a, 7b built in formatter 7 to complete the processing operation of the 1st and 2nd sectors. When operation errors are generated in the 1st and 2nd sectors, all the elements are stopped without being held at a data waiting state to remove malfunction due to noise.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a control method in a control device for an information recording disk device, which is connected between a host computer and an information recording disk device and controls the disk device. Regarding.

(Prior Art) In recent years, information recording disk devices such as magneto-optical disk devices have been used for recording computer data, document files, and the like.

The magneto-optical disk cartridge used in this magneto-optical disk device is a magneto-optical disk for recording/playback that can be freely erased and rewritten, and is made of resin for ease of handling and to make it removable from the recording/playback device. It is housed in a case.

FIG. 6 is a configuration diagram showing an example of a magneto-optical disk used in the disk device shown in FIG. 7, which will be described later. FIG. 6(A) is a bottom view and FIG. 6(B) is a partially enlarged sectional view.

As shown in the figure, the conventional magneto-optical disk 22 has a substrate 22a made of transparent resin, such as polycarbonate, on one surface of which is made of Fe, Co, etc. for recording and reproducing information using the magneto-optic effect. , TbGd, etc.
O film) 22b is formed, and a protective film 22c made of ultraviolet curing resin or the like is further formed thereon, and a disk 2 is formed in the center.
A hub 24 made of a metal plate for driving No. 2 is fixed,
As described above, this disk 22 is housed in a resin case (not shown) and becomes a magneto-optical disk cartridge.

In the recording area 23 of the magneto-optical film 22b of the disk 22 where information is recorded/reproduced, a large number of recording tracks are formed in a spiral or concentric pattern at a pitch of 1.5 μm. Each recording track has 21 sectors each consisting of a management area in which management information is recorded in advance and a data area in which information is recorded/reproduced.

This management area is provided at the beginning of each sector, and this data area is provided following the management area.

FIG. 7 is an explanatory diagram of the recording and reproducing operation of an example of a magneto-optical disk device controlled by the control device of FIG. 2, which will be described later.

As shown in the figure, the conventional magneto-optical disk device 21 is
The magneto-optical disk 22 is mounted and used, and the base 25, electromagnet 26, and optical recording/reproducing device! 27, a feed device 40, etc.

The above-mentioned magneto-optical disk 22 is driven by a spindle motor (not shown) fixed to the base 25.
The protective film 22c is rotated at 0 rpm and
An electromagnet 26 disposed on the side with a gap in between applies a perpendicular bias magnetic field of a predetermined polarity to the magneto-optical film 22b as required. Moreover, the substrate 22a
From the side, information is recorded and reproduced onto and from the magneto-optical film 22b using a laser beam 36 from the optical recording and reproducing device 27.

This optical recording/reproducing device 27 includes a laser diode 28,
Collimating lens 29, beam splitter 30, rising prism 31, objective lens 32, polarizing beam splitter 33, condensing lens 34A.

34B, photodiodes 35A, 35B, etc.

The laser light emitted from the laser diode 28 is collimated by a collimating lens 29, and then shaped into a predetermined beam cross-sectional shape by a beam shaping prism (not shown).
The light passes through and enters the rising prism 31. The laser beam 36 reflected by the rising prism 31 is converted into a light spot 37 with a minute diameter by the objective lens 32.
on the recording track of the recording area 23 of the disk 22,
The light is irradiated onto the surface of the magneto-optical film 22b.

A light spot 3 irradiated onto the surface of this magneto-optical film 22b
7 has a light intensity suitable for recording when the disk device 21 is operating in the recording mode, and has a light intensity suitable for recording when the disk device 21 is operating in the playback mode.
The laser diode 28 is controlled by an output control device (not shown) so as to have a light intensity suitable for reproduction.

In this recording mode, the magneto-optical film 22b on the recording track is
The perpendicular magnetization direction of is only where the light spot 37 hits.
This is reversed by the bias magnetic field generated by the electromagnet 26, thereby recording this digital signal.

In the case of the reproduction mode, the direction of rotation of the polarization plane of the laser beam reflected on the surface of the magneto-optical film 22b changes depending on the perpendicular magnetization direction of the magneto-optical film 22b due to the magneto-optic effect. , the objective lens 32 and the rising prism 31, the beam is reflected by the beam splitter 30, and is incident on the polarizing beam splitter 33 via a half-wave plate (not shown). The laser beam transmitted through the polarizing beam splitter 33 is transmitted through the condensing lens 34.
A, the laser beam is focused by the photodiode 35A, converted into an electric signal, and output as a detection signal.The laser beam reflected by the polarizing beam splitter 33 is focused by the condenser lens 34B and sent to the photodiode. 35B, it is converted into an electrical signal and output as a detection signal.

At this time, the magnitudes of both detection signals change in opposite directions depending on the direction of rotation of the polarization plane due to the action of the polarization beam splitter 33, so the digital signal is reproduced from the difference between these two detection signals. be exposed.

Of the optical recording/reproducing device 27, the laser diode 28, the collimating lens 29, and the beam splitter 30
, polarizing beam splitter 33, condensing lenses 34A, 34
B, photodiode 35A.

A fixed part unit 27-1 consisting of 35B etc. is fixed to the base 25, and a movable part unit 27-2 consisting of the raising prism 31, objective lens 32 etc. is attached to the movable part 40b of the feed device 40. It is installed.

In this feed device 40, the movable part 40b is connected to the base 25.
The drive force of the linear motor 40a of this device 40 fixed to moves the optical spot 37 in the radial direction of the disk 22 along a guide rail (not shown) via a bearing 40c, and directs the light spot 37 to the recording area of this disk 22. The recording track is searched by performing a so-called feeding operation in which the recording track 23 is moved from the inner diameter to the outer diameter. Note that this base 25 is configured to be held by the main chassis of the device 21 (not shown) via a vibration isolating mechanism (not shown).

In addition, so-called focus servo, which automatically makes the focus of the optical spot 37 follow the surface of the magneto-optical film 22b in response to surface wobbling of the disk 22, is based on a focus servo signal based on the detection signal output. Based on this, the vertical position of the objective lens 32 is controlled by a focus servo actuator 38 mounted on the movable part 40b of the feed device 40.

Also, due to the eccentricity of the disk 22, the optical spot 3
The so-called tracking servo that automatically tracks the disk 22 on the recording track is based on a tracking servo signal based on a detection signal output from the management area, and the position of the objective lens 32 in the radial direction of the disk 22 is controlled by the movable part 40.
Tracking servo actuator 39 mounted on b
This is done by controlling the The movement range of the optical spot 37 in the radial direction of the disk 22 due to this tracking servo operation is normally limited to about several hundred μm. Servo operation,
The feed operation is responsible for rough positioning.

The operation of the conventional magneto-optical disk device 21 described above has been outlined to explain its operating principle, but in actual operation, the recording mode is erase (erase), record (write). ) and verification.

That is, in the conventional magneto-optical disk 22 described above,
Since the magneto-optical film 22b cannot be overwritten, which is possible with magnetic tapes, magnetic disks, etc., prior to the recording operation, the recording section is first erased, and then the recording operation is performed. be exposed. Moreover, this magneto-optical film 2
Since 2b lacks reliability, a verification operation is performed after this recording operation. In other words, playback (read) of this recording section
is performed, the recorded signal and the reproduced signal are compared, and if they match, the process moves to the next operation. In the case of non-coincidence, the recorded signal of this portion is recorded again in a pre-provided alternative area, and then a so-called alternative process is performed in which verification and recording addresses are changed.

Control of the magneto-optical disk device 21 is performed by a control device connected between this device 21 and a host computer.

FIG. 2 is a block diagram showing an example of a control device for a conventional magneto-optical disk device that performs the control methods shown in FIGS. 1 and 9, which will be described later. FIG. In the diagrams for explaining the operation, (A) shows the state in the recording mode, and (B) shows the state in the playback mode.

As shown in FIGS. 2 and 8, the conventional control device 1 includes a host computer 41 and the magneto-optical disk device 2.
1.

This control device] includes an interface 2, a microcomputer (hereinafter abbreviated as microcomputer) 3, a DMA (direct memory access) controller 4, a buffer memory 5, and an error correction circuit (hereinafter abbreviated as FCC) 6.
, a formatter 7, a mechanical control circuit 8, and the like.

This interface 2 is connected to the host computer 4.
] and the microcomputer 3, and also relays data exchange between the host computer 41 and the DMA controller 3. The microcomputer 3 controls the operations of the DMA controller 4, ECC 6, formatter 7, and mechanism control device 8. The DMA controller 4 controls data exchange between the interface 2 and the buffer memory 5 and between the buffer memory 5 and the ECC 6 based on instructions from the microcomputer 3. The buffer memory 5 temporarily stores data based on commands from the DMA controller 4. E.C.C.
6 adds an error correction code based on the instructions from the microcomputer 3;
Performs verification operations, error detection/correction, etc. The formatter 7 modulates and demodulates data based on instructions from the microcomputer 3. The mechanical system control device 8 has a built-in microcomputer (not shown) for mechanical system control, and controls each operation of the above-mentioned magneto-optical disk device 21 based on commands from the microcomputer 3.

As shown in FIG. 8(A), in the recording mode, the host computer 41 outputs signals such as recording commands and recording section designation to the microcomputer 3 via the interface 2. Recording data is supplied to the buffer memory 5 via the interface 2 and the DMA controller 4. During a recording operation, the ECC 6 adds an error correction code to the record data from the buffer memory 5, and the formatter modulates the data to generate a record signal. The mechanical system control device 8 instructs the disk device 21 to switch between a search operation, an erase operation, a recording operation, and a collation operation, controls the bias magnetic field by the electromagnet 26, controls the output intensity of the laser diode 28, The position of the objective lens 32 relative to the recording section is controlled, and during recording operation in this disk device 21, recording signals are sequentially recorded one sector at a time in consecutive sectors of the recording track in the recording area 23 of the disk 22. be done.

After the recording operation is completed, the disk device 21 supplies a reproduction signal for a collation operation to the format tough. The formatter demodulates the reproduced signal, the ECC 6 compares the reproduced data from the formatter 7 with the recorded data from the puffer memory 5, and if necessary, the microcomputer 3 performs the above-mentioned alternative processing. The microcomputer 3 then reports the end of the recording command to the host computer 41.

As shown in FIG. 2B, in the playback mode, the host computer 4 outputs signals such as playback commands and playback section designation to the microcomputer 3. Based on this command, the mechanical system control device 8 instructs the disk device 21 to switch between search operation and playback operation, controls the electromagnet 26, controls the laser diode 28,
The position of the objective lens 32 in the reproduction section is controlled, and a reproduction signal is supplied from the disk device 21 to the format tough. In this format tough, the reproduced signal is demodulated, and in the ECC 6,
Error detection and correction of the reproduced data is performed, and the reproduced data is output to the host computer 41 via the buffer memory 5.

Note that this ECC 6 includes a format communication section, a processing section,
The DMA controller is composed of three parts: the communication part, and since it takes time for error correction in this processing part in playback mode, the operation timing for the same sector in these three parts is automatically determined by one sector's worth of playback data. Each sector] is sequentially supplied with a delay of one sector, whereby the processing speed is increased.

Next, a description will be given of registers provided in the DMA controller 4, ECC 6, and formatter 7, into which commands from the microcomputer 3 related to control of recording and reproducing operations are written.

FIG. 3 is a block diagram of a register control device for two systems of registers in the control device of FIG. 2, and FIG. 4 is an explanatory diagram of the operation of two systems of registers in the control device of FIG.

As shown in FIG. 2, the DMA controller 4, EC
C6 and Format Tough each have two registers, registers (1) 4a and 6a.

7a and registers (2) 4b, 6b, and 7b. Registers 4a and 4b of this DMA controller 4
For example, the operation command written to the next sector is one that instructs the content of the operation for the next sector and the method of displaying the status signal that is the result of this operation (normal completion, error occurred, etc.), and the operation command for the next sector. There are methods for specifying the address of the buffer memory 5 to be used.

Further, the operation commands written to the registers 6a and 6b of the ECC 6 are those that instruct the operation contents for the next sector and the display method of the status signal, and the operation commands written to the registers 7a and 7b of the format tough are as follows. one for instructing the operation contents for the sector and the display method of the status signal, one for specifying the sector number in which this operation is to be performed, and whether to perform a kickback operation to jump the light spot 37 to the previous track after the operation is completed. There are things that specify whether or not.

The DMA controller 4, ECC 6, and formatter 7 have switches for alternately switching between two registers, register (1) 4a and register (2) 4b, 6a and 6b, and 7a and 7b as shown in FIG. Each register control device 9 is provided with a circuit 10, two electronic switches, an electronic switch (1) SWI and an electronic switch (2) SW2, a register write circuit 14, and the like.

This register write circuit 14 writes a register (1) (sometimes abbreviated as R1) 4 based on a command from the microcomputer 3.
A, 6a, 7a and registers (2) (sometimes abbreviated as R2) 4b, 6b, 7b are used to alternately write operation instructions related to the control of the recording/reproducing operation described above.

Further, the switching circuit 10 alternately executes operation commands written in two systems of registers, register (1) 4a and register (2) 4b, 6a and 6b, and 7a and 7b. ) Electronic switches connected to 4a, 6a, 7a (1) SWI and resistors (2) 4b, 6b
, 7b and the electronic switch (2) SW2 connected thereto are alternately switched.

The second switching circuit 10 includes an order determining circuit 11, a register setting signal generating circuit 12, a priority order determining circuit 13, and the like.

The register write circuit 14 writes the register (1) 4a based on a command from the microcomputer 3.

6a, 7a and register (2) Register (1), which is the rising edge of a rectangular wave that rises from low to high at the time the above-mentioned operation command is written to 4b, 6b, and 7b.
and the write end signal of the register (2) is sent to the order determination circuit 1.
1 and the register setting signal generation circuit 12, respectively.

This order determination circuit 11 determines the order in which the write end signals of register (1) and register (2) are generated, and if the write end signal of register (1) comes first, it is high; The first write signal of register (1) becomes low when the write end signal is first, and the first write signal of register (2) becomes high when register (2) comes first and becomes low when register (1) comes first. The first write signal is generated and this register (1)
and the first write signal of register (2) are respectively supplied to the priority order determining circuit 13.

In addition, in the register setting signal generation circuit 12, from the time when the write end signal of register (1) and register (2) is generated until the time when fl1 of the reset signal of register (]) and register (2), which will be described later, arrives. Setting signals for register (1) and register (2), which are rectangular waves that sustain , are respectively generated and supplied to the priority order determination circuit 13. The setting signals of registers (1) and (2) are high when the registers are set (movement instructions have been written), and low when they are not set (movement instructions have not been written). , and the register (
Registers (1) and (2) that operate according to operation instructions of registers (1) and (2) occur at the end of the sector in charge of these registers, or when an abnormality occurs in the sector immediately before the sector in charge of these registers. Each is reset by a reset signal. The reset signals of register (1) and register (2) are also supplied to the priority order determining circuit 13 for confirmation.

In this priority determination circuit 13, the register (1
) and the pre-write signal of register (2) and the setting signal of register (1) and register (2) are determined according to the judgment table 13a provided in this circuit 13 at the timing of the sector start signal representing the start of each sector. It will be judged. This judgment table 13a shows that when only one of the two systems of registers is set, the set register is selected (at the start of an operation instruction for only one sector or for normal operation of an operation instruction for multiple sectors). (in progress state), if both are set, connect the register that was written first (such as when starting an operation instruction to multiple sectors) to execute this operation instruction, or set both. If not, both registers are released (at the end of the operation command or when an error occurs), thereby providing a criterion for stopping the operation.As a result of this determination, the priority order determination circuit 13 sends a message indicating that the signal is high. An execution signal of the register (1), which is a signal for turning on the switch and turning it off when it is low, is supplied to the switch (1) SWI, and an execution signal of the register (2) is supplied to the switch (2) SW2.

Therefore, the sector start signal functions as a determination timing signal that provides the timing for the above-mentioned determination, and
It also provides the timing for starting execution of the operation command written in one of the two registers, and is generated after the light spot 37 reaches the start point of the management area of each sector. Therefore, it is generated at a timing slightly delayed from the start point of each sector.

Next, the operation of these two systems of registers will be explained using FIG.
The figure shows the operation when focusing on any one of the DMA controller 4, ECC 6, and format tough.

Before the light spot 37 reaches the starting point of the first sector 1, first, the operation command related to the operation to this sector 1, which is the safeter in charge of register (1), or the register (1)
When the write is written to the register (1), the write end signal for the register (1) described above is generated.Next, when the operation command for the sector 2, which is the sector in charge of the register (2), is written to the register (2), the write end signal of the register (1) is generated. 2) The write end signal is generated. Then, at the timing of the sector start signal indicating the start of sector 1, if the setting signals of register (1) and register (2) are both high without being reset due to an abnormality, then according to the judgment table 13a described above, , the operation instruction written in this register (1) is executed for sector 1. When the light spot 37 reaches the end point of sector 1, the setting signal of this register (1) is reset to low based on the sector end signal indicating the end of the sector, and this register (1) It is reset by the input circuit 14.

Since the sectors on the recording track of the disk 22 are arranged consecutively, the setting signals of registers (1) and (2) are set at the timing of the start signal of sector 2 following the end signal of sector 1. The determined operation command written in register (2) is executed for sector 2.

On the other hand, during the operation to sector 2, triggered by the above-mentioned reset of register (1), an operation instruction for sector 3, which is the next sector in charge of register (1), is written to register (1). The write end signal (1) is generated. Thereafter, register (1) and register (2) operate alternately, and the same operations are performed sequentially for sectors 3 and 4 as well.

Next, an explanation will be given of an abnormality handling operation when an operation error occurs in the ECC 6, formatter 7, etc. in the control device 1.

FIG. 5 is a block diagram of the malfunction treatment circuit in each component of the control device shown in FIG. FIG. 9 is an explanatory diagram of abnormality processing operation showing an example of a conventional control method in the control device of FIG.
) is a data count error in the ECC for sector 3 in playback mode, (B) is an uncorrectable error in the ECC for sector 2 in playback mode, and (C) is a data count error in the ECC for sector 2 in playback mode. In the case of an address error in the formatter for 3, (D) in the same figure shows a data number error in the ECC for sector 1 in playback mode, and (E) in the same figure shows an uncorrectable error in the FCC for sector 1 in playback mode. In the case of (F) in the same figure, there is an address error in the formatter for sector 1 in the reproduction mode.

As shown in FIG. 2, the DMA controller 4, ECC 6, and format tough of the above-mentioned control device 1 are provided with malfunction treatment circuits 4c, 6c, and 7c, respectively.

Further, the types of operational errors that may occur in each of these components of the control device 1 are as follows. In the ECC 6, in the recording mode (recording operation), a data number error occurs when the number of recording data instructed by the microcomputer 3 and the number of recording data requested by the formatter 7 do not match, and in the recording mode (verification operation). At this time, there is a collation error, which is a case where the comparison result between the recorded data from the DMA controller 4 and the reproduced data from the formatter 7 does not match, and in the reproduction mode, the number of reproduced data according to the command of the microcomputer 3 and the reproduced data from the formatter 7 There are data number errors, which occur when the numbers do not match, and uncorrectable errors, which occur when errors cannot be corrected for the reproduced data from the formatter 7. In addition, in this format tough, an address error occurs when the address of a sector to be recorded cannot be detected in the disk device 21 in the recording mode (recording operation), and an address error occurs when the address of the sector to be reproduced is detected by a command from the microcomputer 3 in the reproduction mode. In addition to address errors, which occur when an address cannot be detected in the disk device 21, all operational errors of the mechanism control device 8 and the disk device 21 are treated as operational errors of the formatter 7. In addition,
No operational error occurs in the DMA controller 4.

As shown in FIG. 5(A), this DMA controller 4
The operation abnormality treatment circuit 4c is composed of an automatic operation stop circuit d.

Then, when an operation error notification signal is supplied from the ECC 6 to the automatic operation stop circuit 4d to notify that an operation error has occurred in the ECC 6 or the format tough, which will be described later, the automatic operation stop circuit 4d An automatic operation stop signal is output that causes the DMA controller 4 to stop its own operation at a prompt, predetermined timing.
The operation is stopped at a predetermined timing as soon as possible, as will be described later. Also, this automatic operation stop signal is a DMA
The status signals are also supplied to the registers 4a and 4b built into the controller 4, and the above-mentioned status signals are outputted from these registers 4a and 4b in response to the control signal from the microcomputer 3, thereby performing the repair operation. .

As shown in FIG. 6B, the operation abnormality treatment circuit 6C of the ECC 6 includes an automatic operation stop circuit 6d, an operation error notification circuit 6e, an operation error detection circuit 6f, and the like.

When an operation error of the type described above occurs in this ECC 6, an operation error signal is supplied to the operation error detection circuit 6f, and this operation error is detected by the operation error detection circuit 6f, indicating that an operation error has occurred. An operation error occurrence signal indicating that the automatic operation stop circuit 6d
and the operation error notification circuit 6e. In the operation error notification circuit 6e, an operation error notification signal is output to the DMA controller 4 and formatter 7, respectively, in response to the operation error occurrence signal.

Also, the operation error notification signal from this formatter 7,
The signal is supplied to an automatic operation stop circuit 6d and an operation error notification circuit 6e, respectively. In response to the operation error notification signal from the formatter 7, in the recording mode, the operation error notification circuit 6e outputs the operation error notification signal to the D M
It is output to the A controller 4. Furthermore, as will be described later, during the playback mode, even if an operational error occurs in the formatter 7 and the formatter communication section,
This operation error notification signal is configured not to be output to the DMA controller 4.

In this case, the operation stoppage in the DMA controller 4 is as follows.
The configuration is such that this is performed in response to an operation stop command from the microcomputer 3. Further, in the automatic operation stop circuit 6d,
In response to the operation error occurrence signal or operation error notification signal, the automatic operation stop signal is output, and as a result, the ECC6
The operation is stopped at a predetermined timing as soon as possible, as will be described later.

This automatic operation stop signal is also supplied to the registers 6a and 6b built in the ECC 6. Further, an operation error content signal indicating the type of operation error as described above is supplied from the operation error detection circuit 6f to the registers 6a and 6b, and the register 6a is supplied to the registers 6a and 6b in response to the control signal from the microcomputer 3. .

The above-mentioned status signal is outputted from 6b, and the above-mentioned repair operation is performed thereby.

As shown in FIG. 2C, the malfunction treatment circuit 7C of the Fusu-Mazda 7 includes an automatic operation stop circuit 7d, an operation error notification circuit 7e, an operation error detection circuit 7f, and the like.

When an operation error of the type described above occurs in the formatter 7, the mechanical system control device 8, and the disk device 21, an operation error signal is supplied to the operation error detection circuit 7f, and the operation error detection circuit 7f This operation error is detected and the operation error occurrence signal is detected.
The signal is supplied to an automatic operation stop circuit 7d and an operation error notification circuit 7e, respectively. In this operation error notification circuit 7e, an operation error notification signal is outputted to the ECC 6 in response to this operation error occurrence signal. Further, the operation error notification signal from the ECC 6 is supplied to the automatic operation stop circuit 7d. In this automatic operation stop circuit 7d, the automatic operation stop signal is outputted in response to the operation error occurrence signal or operation error notification signal, whereby the operation of the format tough is stopped at the earliest possible predetermined timing as described later. be done.

This automatic operation stop signal is also supplied to the registers 7a and 7b built into the format tough.

Further, an operation error content signal is supplied from the operation error detection circuit 7f to the registers 7a, 7b, and the registers 7a, 7 are supplied in response to the control signal from the microcomputer 3.
The above-mentioned status signal is outputted from b, and the above-mentioned repair operation is performed thereby.

A conventional control method for the control device 1 configured as described above is to set the registers 4a and 4b, 6a and 6b, and 7a and 7b of the DMA controller 4, ECC 6, and formatter 7 during the playback mode. In this case, the settings for the first and second sectors are performed before starting the processing operation for this first sector, and the settings for the third and subsequent sectors are performed by processing for one sector in Format Tough in ECC6 and Format Tough. At the end of each operation, the DMA controller 4
In the DMA controller communication section, the DMA
This is performed every time the transfer operation of one sector worth of playback data to the controller 4 is completed.

As shown in FIG. 9(A), in the playback mode, when the data number error occurs in the formatter communication unit of the ECC 6 for sector 3 during the playback operation for sectors 1 to 4, The automatic operation stop signal stops the operation of sector 4 in the formatter communication section of the ECC6 and the operation of sector 3 in the processing section and DMA controller communication section of the ECC6, and the operation error notification signal stops the operation of sector 4 in the formatter communication section. As for stopping the operation of the DMA controller 4, the microcomputer 3 has enough time to stop the operation by software.
This is carried out for sector 3 in response to an operation stop command from .

As shown in (B) of the same figure, when an uncorrectable error occurs in the processing unit of the ECC 6 for sector 2 during playback operation for sectors 1 to 4 in the playback mode, automatic operation stops. The signal causes sector 4 in the formatter communication section of the ECC 6 to be changed to sector 3 in the processing section and DMA controller communication section of the ECC 6.
At the same time, the operation of sector 3 in the DMA controller 4 and sector 4 in the format tough is stopped by the operation error notification signal.

As shown in (C) of the same figure, when the address error occurs in the formatter 7 for sector 3 during the reproduction operation for sectors 1 to 4 in the reproduction mode, the automatic operation stop signal causes the formatter to stop. 7 to 1
stopping the operation of sector 4 in the formatter communication section of the ECC 6 and stopping the operation of sector 3 in the processing section and the DMA controller communication section by the operation error notification signal;
The operation of the DMA controller 4 is stopped for sector 3 in response to an operation stop command from the microcomputer 3, since there is enough time to stop the operation by software.

As shown in (D) of the same figure, when the data number error occurs in the formatter communication section of the ECC 6 regarding the sector in the playback mode, an automatic operation stop signal is sent to the ECC6.
Regarding sector 2 in the formatter communication section of CC6, the operation for sector 1 in the processing section and DMA controller communication section of ECC6 is stopped, and the operation error notification signal causes sector 2 in formatter 7 to be stopped.
DMA controller 4
In this case, since the registers (1) 4a and (2) 4b are set for sectors 1 and 2, these sectors are in a data waiting state.

As shown in (E) of the same figure, when the uncorrectable error occurs in the processing section of the ECC 6 for sector 1 during playback mode, an automatic operation stop signal causes the formatter communication section of the ECC 6 to issue an ECC error for sector 3.
At the same time, the operation of sector 2 in the processing unit 6 and the DMA controller communication unit is stopped, and the operation of sector 2 in the DMA controller 4 and sector 3 in the formatter 7 is stopped in response to the operation error notification signal.

As shown in (F) in the same figure, when the address error occurs in the format tough for sector 1 in the playback mode, the automatic operation stop signal stops the operation for sector 2 in the format tough, and In response to the error notification signal, the operation of sector 2 in the formatter communication section of the ECC 6 and sector 1 in the processing section and DMA controller communication section is stopped, and the DMA controller 4 stops the operation of sector 1 and sector 2 in the register (1) 4a. and register (2
) 4b is set, so sector 1 and sector 2 are in a data waiting state.

Note that the data waiting state of the DMA controller 4 as shown in FIGS.
This also occurs when an operational error occurs.

(Problems to be Solved by the Invention) In the conventional control method in the control device 1 as described above, in the playback mode, the DMA controller 4, E
CC6 and Formatsu Tough registers 4a and 4b;
When setting 6a and 6b and 7a and 7b, the settings for the first and second sectors are performed before starting the processing operation for the first sector, so the formatter 7 or the formatter communication section , when an operation error occurs in the first or second sector, the settings of the registers 4a and 4b are not reset, and as described above, the DMA controller 4 continues to wait for data. There was a point. In this data waiting state, there is a risk that malfunctions may occur due to noise or the like. Furthermore, at the start of the above-mentioned repair operation, the circuit for eliminating this data waiting state becomes complicated.

In addition, in the above case, is it possible to have a configuration in which the operation error notification signal is supplied from the ECC 6 to the DMA controller 4? Such a configuration would require a complicated circuit and increase costs. Become. The reason for this is explained below.

When an operational error as described above occurs, the microcomputer 3 needs to know the type and source of the operational error in order to start the repair operation. How to know and registers 4a, 4b of the DMA controller 4 or register 6a of the ECC 6.

6b or the register 7a of the formatter 7.

There are two possible methods: 7b. In the former case, the generation sources are multiple, so the circuit and software are complicated. Moreover, the latter applies to the operation error notification signal,
Since it is necessary to incorporate information representing the type and origin of the operational error, the circuit and software become complex.

The present invention has been made with attention to the above points, and an object of the present invention is to provide a control method for a control device of an information recording disk device that does not cause a data waiting state to occur in the above-mentioned cases without increasing costs. It is something to do.

(Means for Solving the Problems) A control method in a control device for an information recording disk device of the present invention uses an information recording disk in which a recording track of a recording area is divided into a plurality of sectors, and A control method for a control device for controlling an information recording disk device that records/reproduces information sector by sector, wherein the control device includes at least a DMA controller, an error correction circuit, and a formatter, each of which is controlled by a microcomputer. The error correction circuit includes a formatter communication section, a processing section, and a DMA
It is composed of three parts of the controller communication section, and in the playback mode, the operation timing for the same sector in the three parts is automatically supplied with playback data for one sector or delayed by one sector each. an operation error occurrence signal supplied from an operation error detection circuit within the own element when an operation error occurs within the own element; Alternatively, when an operation error occurs in another element, an operation error handling circuit that stops the operation of the own element at a predetermined timing in response to a device error notification signal constituted by an operation error notification circuit of the other element, and the microcomputer Two systems of registers are provided in which operation instructions for each of the sectors are written, and the two systems of registers are alternately switched and used in each of the three components, and each of these registers is assigned to handle every other sector. In the control method for a control device of an information recording disk device, when setting the registers of the DMA controller, the error correction circuit, and the formatter in the playback mode, the settings for the first and second sectors are set according to the error correction circuit and the formatter. The formatter performs the settings before starting the processing operation for the first sector, and the DMA controller performs the settings at the end of the processing operation for the first and second sectors, respectively, in the formatter, and the settings for the third and subsequent sectors are performed. In the error correction circuit and the formatter, each time the formatter completes the processing operation for one sector, the DMA controller transfers the one sector worth of reproduced data from the DMA controller communication unit to the DMA controller. By performing this at each end, the above-mentioned problem is solved.

(Embodiment) A control method for a control device for an information recording disk device according to the present invention includes the steps of setting the registers of the DMA controller, ECC, and formatter during the playback mode in the control method for the control device as described above. The settings for the first and second sectors are set in the FCC and formatter before the processing operation for the first sector is started, and in the DMA controller, the settings for the processing operation for the first and second sectors in the formatter are set, respectively. The settings for the third and subsequent sectors are performed at the time of completion, and in the ECC and formatter, each time the processing operation for one sector in the formatter is completed, in the DMA controller, the setting for one sector is made from the DMA controller communication unit to the DMA controller. This is performed each time the playback data transfer operation ends.

An embodiment of the present invention will be described under the same conditions as the conventional example described above.

FIG. 1 is an explanatory diagram of an abnormality processing operation showing an example of the control method in the control device of FIG. 2, which is an embodiment of the control method in the control device of the information recording disk device of the present invention; In the case of a data count error in the FCC for sector 3 in the playback mode, (B) shows the case of an uncorrectable error in the FCC for sector 2 in the playback mode, and (C) shows the error in the FCC for sector 3 in the playback mode. In the case of an address error in Formattuta, the same figure (D)
In the case of data count error in FCC for sector 1 in playback mode, (E) in the same figure shows sector 1 in playback mode.
In the case of an uncorrectable error in the ECC for
FIG. 5F shows a case where an address error occurs in the formatter for sector 1 during reproduction.

FIG. 1 (A,
) to (F) correspond to FIGS. 9(A) to (F) in the case of the conventional example described above, and explanations of the same parts as in the conventional example will be omitted.

As shown in FIG. 3A, in the playback mode, sector 1
~ If the data count error occurs in the formatter communication section of the ECC 6 for sector 3 during playback operation for sector 4, an automatic operation stop signal will cause the formatter communication section of the ECC 6 to perform a playback operation for sector 4. Stopping the operation of sector 3 in the processing unit and DMA controller communication unit, and
Since there is enough time to stop the operation of the selector 4 in the formatter 7 by the operation error notification signal and to stop the operation of the DMA controller 4 by software, the operation stop command from the microcomputer 3 causes This is done for sector 3.

As shown in (B) of the same figure, when an uncorrectable error occurs in the processing unit of the ECC 6 for sector 2 during playback operation for sectors 1 to 4 in the playback mode, automatic operation stops. The signal causes sector 4 in the formatter communication section of the ECC 6 to be changed to sector 3 in the processing section and DMA controller communication section of the ECC 6.
At the same time, the operation of sector 3 in the DMA controller 4 and sector 4 in the format tough is stopped by the operation error notification signal.

As shown in (C) of the same figure, in the playback mode, if the address error occurs in the formatter for sector 3 during the playback operation for sectors 1 to 4, an automatic operation stop signal is sent to the formatter 7. At the same time, the operation for sector 4 in the formatter communication section of the ECC 6 is stopped, and the operation for sector 3 in the processing section and DMA controller communication section is stopped by the operation error notification signal.
The operation of the MA controller 4 is stopped for sector 3 in response to an operation stop command from the microcomputer 3, since there is enough time to stop the MA controller 4 by software.

As shown in (D) of the same figure, in playback mode, safe sector 1
If the above-mentioned data count error occurs in the formatter communication section of the ECC 6, an automatic operation stop signal will cause the operation for sector 2 in the formatter communication section of the ECC 6 and for sector 1 in the processing section and DMA controller communication section of the ECC 6 to be stopped. At the same time, the operation of sector 2 in the formatter 7 is stopped by the operation error notification signal, and the operation of the DMA controller 4 is stopped by register (1) 4a.
Since this is before the setting of the register (2) 4b and there is enough time for the software to stop the operation, the operation is performed for sector 1 in accordance with the operation stop command from the microcomputer 3.

As shown in (E) of the same figure, when the uncorrectable error occurs in the processing unit of the ECC 6 for sector 1 in the playback mode, the automatic operation stop signal causes the formatter communication unit of the ECC 6 to perform ECC processing for sector 3.
The operation of sector 2 in the processing unit 6 and the DMA controller communication unit is stopped, and the operation of sector 2 in the DMA controller 4 and sector 3 in the format tough is also stopped by the operation error notification signal.

As shown in (F) in the same figure, in playback mode, safe sector 1
When the address error occurs in the formatter 7, an automatic operation stop signal causes the formatter to stop operation for sector 2, and an operation error notification signal causes the formatter communication section of the ECC 6 to stop the processing section and The operation of sector 1 in the DMA controller communication unit is stopped and the operation of the DMA controller 4 is stopped before the register (1) 4a and register (2) 4b are set, and there is sufficient time to stop the operation by software. Therefore, the operation is performed for sector 1 in accordance with the operation stop command from the microcomputer 3.

In addition, in the control method of one embodiment of the present invention, FIG. 9 (
Although not shown, the data waiting state in the conventional example described above as shown in FIG.
As in the cases shown in and (F), this does not occur.

The control method of the embodiment of the present invention in the control device 1 as described above is different from the case of the conventional example described above, as described above, in the reproduction mode, the control method of the DMA controller 4, the EC
C6 and Formatsu Tough registers 4a, 4b, 6
When setting a and 6b and 7a and 7b, the settings for the first and second sectors are as follows: Since this is carried out at the end of the processing operations for the first and second sectors in the formatter 7 or the formatter communication section,
If an operation error occurs regarding the 1st or 2nd sector, the data waiting state does not occur in the DMA controller 4. Therefore, there is no risk of malfunction due to noise or the like, and no circuit is required to eliminate this data waiting state. Furthermore, since the data waiting state is resolved by software, it can be done without increasing costs.

(Effects of the Invention) The control method for the control device for the information recording disk device of the present invention as described above allows for improvement of functionality without increasing costs, so the function-to-cost ratio of the system using this control method is low. improves.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of an abnormality processing operation showing an example of the control method in the control device of FIG. FIG. 9 is a block diagram showing an example of a control device for a conventional magneto-optical disk drive using the control method shown in FIG. 9, and FIG. 3 is a block diagram of a register control device for two systems of registers included in the control device shown in FIG. , FIG. 4 is an explanatory diagram of the operation of the two systems of registers in the control device shown in FIG. 2, and FIG. 5 is a block diagram of the malfunction treatment circuit in each component of the control device shown in FIG. is a DMA controller, the same figure (B
) is a configuration diagram showing the ECC, (C) is a formatter malfunction treatment circuit, FIG. 6 is a configuration diagram showing an example of a magneto-optical disk used in the disk device shown in FIG. 7, and (A) is a configuration diagram showing the bottom side. FIG. 7 is an explanatory diagram of the recording and reproducing operation of an example of a magneto-optical disk device controlled by the control device shown in FIG. 2, and FIG. 8 is a partially enlarged sectional view of the same figure (B). FIG. 9 is an explanatory diagram of an abnormality handling operation showing an example of a conventional control method in the control device of FIG. 1... Control device, 3... Microcomputer (microcomputer), 4...
DMA controller, 6...Error correction circuit (ECC), 7...Formatter, 4a, 6a, 7a...Register (1) (2 systems of registers), 4b 6b, 7b...Register (2) (2 systems of registers), 4c, 6c, 7c... malfunction processing circuit, 6e, 7e
...Operation error notification circuit, 6f, 7f... Operation error detection circuit, 9 Register control device, 21. Magneto-optical disk device (information recording disk device) 22. Magneto-optical disk (information recording disk) 23.
...recording area.

Claims (1)

[Claims] An information recording disk in which a recording track in a recording area is divided into a plurality of sectors is used, and one
A control method for a control device that controls an information recording disk device that records/reproduces information sector by sector, wherein the control device includes at least a DMA controller, an error correction circuit, and a formatter, each of which is controlled by a microcomputer. The error correction circuit is composed of three parts: a formatter communication section, a processing section, and a DMA controller communication section. In the playback mode, the error correction circuit changes the operation timing for the same sector in the three sections for one sector. The playback data of
By being supplied with a delay of one sector, each
The operation error occurrence signal is configured to be delayed by sectors, and is supplied from an operation error detection circuit in the own element when an operation error occurs in each of the three components, or When an operation error occurs in another element, an operation error handling circuit that stops the operation of its own element at a predetermined timing in response to an operation error notification signal supplied from an operation error notification circuit of the other element, and Two systems of registers are provided in which operation commands for each sector are written, and the two systems of registers are alternately switched and used in each of the three components, and each of these registers is assigned to handle every other sector. In the control method for a control device of an information recording disk device, when setting the registers of the DMA controller, error correction circuit, and formatter in the playback mode, the settings for the first and second sectors are set by the error correction circuit and the registers of the formatter. In the formatter, before starting the processing operation for this first sector, the DMA controller
Settings for the third and subsequent sectors are performed in the error correction circuit and formatter at the end of the processing operation for one sector in the error correction circuit and the formatter, and in the DMA controller each time the processing operation for one sector in the formatter is completed. A control method in a control device for an information recording disk device, characterized in that the following is performed each time the transfer operation of the one sector worth of playback data from the DMA controller communication unit to the DMA controller ends.