JPH03248422A - Implantation of ion - Google Patents
Implantation of ionInfo
- Publication number
- JPH03248422A JPH03248422A JP4655190A JP4655190A JPH03248422A JP H03248422 A JPH03248422 A JP H03248422A JP 4655190 A JP4655190 A JP 4655190A JP 4655190 A JP4655190 A JP 4655190A JP H03248422 A JPH03248422 A JP H03248422A
- Authority
- JP
- Japan
- Prior art keywords
- compound semiconductor
- semiconductor substrate
- approximately
- slanted
- implanted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002513 implantation Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 claims abstract description 50
- 150000001875 compounds Chemical class 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 150000002500 ions Chemical class 0.000 claims abstract description 39
- 239000012535 impurity Substances 0.000 claims abstract description 28
- 239000013078 crystal Substances 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 17
- 238000005468 ion implantation Methods 0.000 claims description 9
- 238000010884 ion-beam technique Methods 0.000 abstract description 12
- 230000005465 channeling Effects 0.000 abstract description 10
- 230000004913 activation Effects 0.000 abstract 1
- 238000007634 remodeling Methods 0.000 abstract 1
- 238000000926 separation method Methods 0.000 abstract 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- WGPCGCOKHWGKJJ-UHFFFAOYSA-N sulfanylidenezinc Chemical group [Zn]=S WGPCGCOKHWGKJJ-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はイオン注入方法に関し、特にＬＳＩなどの半導
体装置の製造において、化合物半導体基板に不純物をイ
オン化して打込んでドーピングする方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an ion implantation method, and particularly to a method of doping by ionizing and implanting impurities into a compound semiconductor substrate in the manufacture of semiconductor devices such as LSIs.
ＧａＡｓ、 ＩｎＰなどの■−Ｖ族化合物半導体を使用
したＬＳＩなどの半導体装置の製造では、化合物半導体
基板にＮ型不純物層を形成する手段としてイオン注入法
が一般的に用いられている。In the manufacture of semiconductor devices such as LSIs using ■-V group compound semiconductors such as GaAs and InP, ion implantation is generally used as a means of forming an N-type impurity layer on a compound semiconductor substrate.
このイオン注入法は、第３図に示すように不純物イオン
を発生させるイオン源（１）に、化合物半導体基板（２
）をその処理面（３）をイオン源（１）に向けてホルダ
（４）で配置する。そして、このイオン源（１）で不純
物原子をイオン化して不純物イオンを発生させ、これに
高電圧を印加する。上記イオン源（１）から発せられた
不純物イオンを′１を量分離し、更に加速させた上で、
第４図に示すようにそのイオンビームａを走査させなが
ら化合物半導体基板（２）の処理面（３）に所定のエネ
ルギーで打込む。尚、上記イオンビームａの走行経路は
高真空雰囲気に設定されている。In this ion implantation method, as shown in Figure 3, an ion source (1) that generates impurity ions is connected to a compound semiconductor substrate (2).
) is placed in a holder (4) with its processing surface (3) facing the ion source (1). Then, impurity atoms are ionized by this ion source (1) to generate impurity ions, and a high voltage is applied to the impurity ions. After separating the impurity ions emitted from the ion source (1) by 1 and further accelerating them,
As shown in FIG. 4, the ion beam a is implanted with a predetermined energy into the processing surface (3) of the compound semiconductor substrate (2) while being scanned. Note that the travel path of the ion beam a is set in a high vacuum atmosphere.
このようにして打込まれた不純物イオンは、化合物半導
体基板（２）中の格子原子と衝突しながらＪネルギーを
失って、処理面（３）から所定の深さまで達して停止す
る。これにより不純物がドーピングされ、さらに熱処理
を行うことにより化合物半導体基板（２）に活性層が形
成される。The impurity ions implanted in this manner lose J energy while colliding with lattice atoms in the compound semiconductor substrate (2), reach a predetermined depth from the processing surface (3), and stop. As a result, impurities are doped, and an active layer is formed in the compound semiconductor substrate (2) by further performing heat treatment.
ところで、ＧａＡｓやＴｎＰなどの■〜Ｖ族化合物半導
体の結晶構造は、二つの面心立方格子が貫入し合った閃
亜鉛鉱構造の空間格子からなり、従来、上記化合物半導
体基板（２）の処理面（３）を上記空間格子の（１００
）面とし、ＯＦを（０１１）方位、ＩＦをＣ０１１）方
位となるように設定している。By the way, the crystal structure of group Ⅰ to V compound semiconductors such as GaAs and TnP consists of a space lattice with a zincblende structure in which two face-centered cubic lattices interpenetrate. Surface (3) is defined as (100
) plane, the OF is set to the (011) direction, and the IF is set to the C011) direction.
このような化合物半導体基板（２）の処理面（３）に不
純物イオンを打込んだ場合、上記不純物イオンが空間格
子の配列間を潜り抜けて所定の深さよりも深く入り込む
現象、いわゆるチャネリングが発生する。このチャネリ
ングは不純物イオンの処理面への入射角度などによって
左右される。ここで、前述したイオン源（１）は固定配
置されており、そのイオン源（１）から発せられるイオ
ンビームａはスポット状であるのに対し、化合物半導体
基板（２）の処理面（３）の面積が大きいので、上記イ
オンビームａを走査させることにより処理面（３）の全
面に亘って不純物イオンを打込むようにしている。とこ
ろが、このようにイオンビームａを走査すると処理面内
でビーム入射角度が異なるため、上述したチャネリング
が発生し易い箇所と発生し難い箇所が存在することにな
り、上記処理面内で不純物イオンの注入量がばらつき、
１つの化合物半導体基板（２）から適正な活性層が形成
された素子を得られる個数が少なくなり歩留まりが大幅
に低下する。When impurity ions are implanted into the treated surface (3) of such a compound semiconductor substrate (2), a phenomenon in which the impurity ions sneak through the space lattice arrangement and penetrate deeper than a predetermined depth, so-called channeling, occurs. do. This channeling is influenced by the angle of incidence of impurity ions on the processing surface. Here, the ion source (1) described above is fixedly arranged, and the ion beam a emitted from the ion source (1) is in the form of a spot, whereas the ion beam a emitted from the ion source (1) is in the form of a spot. Since the area is large, impurity ions are implanted over the entire surface of the processing surface (3) by scanning the ion beam a. However, when the ion beam a is scanned in this way, the beam incidence angle differs within the processing surface, so there are locations where the above-mentioned channeling is likely to occur and locations where it is difficult to occur. The amount of injection varies,
The number of devices with appropriate active layers that can be obtained from one compound semiconductor substrate (2) decreases, resulting in a significant decrease in yield.
そこで、従来では上記化合物半導体基板（２）の処理面
（３）をイオン源（１）に対して略７゜程度傾斜させ、
更にその状態で化合物半導体基板（２）をその処理面内
で略２７°程度回転させることによりチャネリングを抑
制して処理面内での不純物イオンの注入量を均一化して
いるのが現状である。Therefore, conventionally, the processing surface (3) of the compound semiconductor substrate (2) is inclined at about 7 degrees with respect to the ion source (1).
Furthermore, in this state, the compound semiconductor substrate (2) is rotated approximately 27 degrees within the processing surface to suppress channeling and equalize the amount of impurity ions implanted within the processing surface.
ところで、上述したように化合物半導体基板（２）の処
理面（３）を略７°程度傾斜させ、更に処理面内で略２
７°程度回転させた姿勢で上記化合物半導体基板（２）
を配置することによりチャネリングを抑制して処理面内
での不純物イオンの注入量の均一化を図っているが、近
年では、上記化合物半導体基板（２）をさらに略３°程
度傾斜させてその傾斜角を略１０″程度に設定すれば、
従来の場合と比較してより一層チャネリングが可及的に
抑制できることが明らかとなっている。しかしながら、
上記化合物半導体基板（２）の処理面（３）を略ｌＯ°
程度に傾斜させるためには、既存の設備を改造しなけれ
ばならず、設備費が高くついて製品のコストアップを招
く虞もあった。By the way, as mentioned above, the processing surface (3) of the compound semiconductor substrate (2) is tilted by approximately 7 degrees, and the processing surface (3) is tilted approximately 2 degrees within the processing surface.
The above compound semiconductor substrate (2) is rotated by about 7 degrees.
By arranging the compound semiconductor substrate (2), channeling is suppressed and the amount of impurity ions implanted is made uniform within the processing surface. If you set the corner to about 10",
It has become clear that channeling can be suppressed as much as possible compared to the conventional case. however,
The treated surface (3) of the compound semiconductor substrate (2) is approximately 10°
In order to achieve a certain degree of inclination, it is necessary to modify existing equipment, which may increase the cost of the equipment and increase the cost of the product.
そこで、本発明は上記問題点に鑑みて提案されたもので
、その目的とするところは既存の設備を改造することな
く使用でき、而もチャネリングを可及的に抑制して化合
物半導体基板の処理面内でのイオン注入量の均一化を図
り得るイオン注入方法を提供することにある。Therefore, the present invention was proposed in view of the above problems, and its purpose is to process compound semiconductor substrates by being able to use existing equipment without modifying it, and suppressing channeling as much as possible. An object of the present invention is to provide an ion implantation method that can uniformize the amount of ions implanted within a plane.
本発明における上記目的を達成するための技術的手段は
、化合物半導体基板を、その処理面をイオン源に向けて
所定の角度傾斜させて配置し、上記イオン源から発せら
れた不純物イオンを質量分離並びに加速させた上で、そ
のイオンビームを走査させながら化合物半導体基板の処
理面に打込んで不純物をドーピングする方法であって、
上記化合物半導体基板の処理面は、化合物半導体の結晶
構造における空間格子の（１００）面から（０１１〕〔
ｏ’Ｔｒ） （０１１） ［ｏｒｌ〕方位ノイｆレ
カニ略３゜傾斜した面であることを特徴とする。The technical means for achieving the above object of the present invention is to arrange a compound semiconductor substrate with its processing surface inclined at a predetermined angle toward an ion source, and mass-separate impurity ions emitted from the ion source. A method of doping impurities by accelerating the ion beam and implanting it into the processing surface of a compound semiconductor substrate while scanning the ion beam,
The processed surface of the compound semiconductor substrate is from the (100) plane of the space lattice in the crystal structure of the compound semiconductor to the (011) [
o'Tr) (011) [orl] It is characterized by being a surface inclined by approximately 3 degrees.
本発明方法では、化合物半導体基板として、その処理面
が化合物半導体の結晶構造における空間格子の（１００
）面から（０１１） （０１１） （０１１〕〔０
１１）方位のいずれかに略３°傾斜したものを使用する
ので、上記空間格子の（１００）面を、化合物半導体基
板を機構的に傾斜させた角度に上述の略３°程度を加え
た角度傾斜させて上記空間格子に不純物イオンを打込む
ことになる。In the method of the present invention, the treated surface of the compound semiconductor substrate is (100
) from (011) (011) (011] [0
11) Since a substrate tilted by approximately 3° in either direction is used, the (100) plane of the space lattice is set at an angle that is the mechanically tilted angle of the compound semiconductor substrate plus approximately 3° as described above. Impurity ions are implanted into the space lattice at an angle.
本発明に係るイオン注入方法の一実施例を第１図及び第
２図を参照しながら説明する。尚、第３図及び第４図と
同一部分には同一参照符号を付して重複説明は省略する
。An embodiment of the ion implantation method according to the present invention will be described with reference to FIGS. 1 and 2. Note that the same parts as in FIGS. 3 and 4 are given the same reference numerals, and redundant explanation will be omitted.
本発明の特徴は化合物半導体基板（２”）にある、即ち
、上記化合物半導体基板（２′）の処理面（３゛）は、
第２図に示すようにＧａＡｓやＩｎＰなどの■−■族化
合物半導体の結晶構造における空間格子の（１００）面
から（０１１） （ｏ−ｔ１〕（０１了〕〔０１１］
方位のいずれかに略３°傾斜した面である。The feature of the present invention lies in the compound semiconductor substrate (2''), that is, the treated surface (3') of the compound semiconductor substrate (2') is
As shown in Figure 2, from the (100) plane of the space lattice in the crystal structure of ■-■ group compound semiconductors such as GaAs and InP, (011) (o-t1) (01 completed) [011]
It is a surface inclined approximately 3 degrees in either direction.
本発明方法では、上記化合物半導体基板（２”）を使用
して既存の設備でイオン注入を行う。即ち、第１図に示
すように上記化合物半導体基板（２”）をその処理面（
３゛）をイオン源（１）に向けてホルダ（４）で固定配
置する。この時、上記化合物半導体基板（２°）の処理
面（３”）をイオン源（１）に対して略７°程度傾斜さ
せ、更にその状態で化合物半導体基板（２゛）をその処
理面内で略２７°程度回転させて配置する０本発明方法
では、化合物半導体の空間格子の（１００）面から略３
°程度傾斜させた方位を、化合物半導体基板（２”）を
ホルダ（４）で機構的に略７°程度傾斜させた方向と一
致させてセツティングする。これにより上記空間格子の
（１００）面を、化合物半導体基板（２”）を機構的に
傾斜させた角度である略７°程度に略３°程度を加えた
角度である略１０°程度傾斜させたことになる。そして
この状態でイオン源（１）から不純物イオンを発して質
量分離並びに加速させた上で、そのイオンビームａを走
査させながら化合物半導体基板（２゛）の処理面（３°
）に打込む。この時、不純物イオンは空間格子の（１０
０）面を略１０’程度傾斜させた状態で打込まれ、格子
原子と衝突しながらエネルギーを失って、処理面（３′
）から所定の深さまで達して停止し、この不純物のドー
ピングにより活性層が形成される。In the method of the present invention, ion implantation is performed using existing equipment using the compound semiconductor substrate (2"). That is, as shown in FIG.
3) is fixedly placed with a holder (4) facing the ion source (1). At this time, the processing surface (3") of the compound semiconductor substrate (2°) is tilted at approximately 7° with respect to the ion source (1), and in this state, the compound semiconductor substrate (2") is placed within the processing surface. In the method of the present invention, the space lattice of the compound semiconductor is rotated by approximately 27 degrees.
The compound semiconductor substrate (2") is mechanically set in the holder (4) so that the orientation tilted by about 7 degrees coincides with the direction tilted by about 7 degrees. This allows the (100) plane of the above-mentioned space lattice to be aligned. This means that the compound semiconductor substrate (2'') is tilted by approximately 10 degrees, which is an angle obtained by adding approximately 3 degrees to approximately 7 degrees, which is the angle at which the compound semiconductor substrate (2'') is mechanically inclined. In this state, impurity ions are emitted from the ion source (1), mass separated and accelerated, and while the ion beam a is scanned, the processing surface (3 degrees) of the compound semiconductor substrate (2゛) is
). At this time, impurity ions are (10
0) It is implanted with the surface inclined by about 10', and loses energy while colliding with lattice atoms, resulting in the processed surface (3'
) until it reaches a predetermined depth and stops, and an active layer is formed by doping with this impurity.
上記化合物半導体基板（２°）の処理面（３゛）につい
て、空間格子の（１００）面からの傾斜角度は上述した
ように略３°程度に設定され、具体的には２．５−〜３
．５°の範日力゛゛“女ト逼ヱ′遁る。 二二２・、上
記２．５°以下であるとチャネリングを抑制して処理面
内での不純物イオンの注入量の均一化できるという所期
の効果が得られず、逆に３．５゛以上になると、後工程
でのエツチング処理時にそのエツチング特性が変わると
いう不都合が生じる。Regarding the processed surface (3°) of the compound semiconductor substrate (2°), the inclination angle of the space lattice from the (100) plane is set to approximately 3° as described above, and specifically, 2.5- to 3
．． It is said that if the angle is 2.5 degrees or less, channeling can be suppressed and the amount of impurity ions implanted within the processing surface can be made uniform. If the desired effect is not obtained and the thickness exceeds 3.5°, there will be a problem that the etching characteristics will change during the etching process in the subsequent process.
本発明方法によれば、化合物半導体基板の処理面を空間
格子の（１００）面から略３°程度傾斜させて形成した
から、既存の設備を改造することなく使用でき、チャネ
リングを可及的に抑制して化合物半導体基板の処理面内
でのイオン注入量を均一化することが容易となり、製品
のコストアップを招くこともない。According to the method of the present invention, since the processing surface of the compound semiconductor substrate is formed with an inclination of about 3 degrees from the (100) plane of the space lattice, existing equipment can be used without modification, and channeling can be minimized. It becomes easy to control the amount of ions to be implanted within the processing surface of the compound semiconductor substrate, and the cost of the product does not increase.
第１図は本発明に係るイオン注入方法の一実施装置例を
示す概略構成図、第２図は第１図の化合物半導体基板の
処理面を示す正面図である。
第３図はイオン注入方法の従来装置例を示す概略構成図
、第４図は第３図の化合物半導体基板の処理面でのイオ
ンビーム走査状態を示す正面図である。
（１）
イオン源、
（２’）−・−化合物半導体基板、
（３°）−処理面、
ａ−イオンビーム。
特
許
出
願
人
関西日本電気株式会社
代
理
人
江
原
省
吾FIG. 1 is a schematic configuration diagram showing an example of an apparatus for implementing the ion implantation method according to the present invention, and FIG. 2 is a front view showing the processing surface of the compound semiconductor substrate of FIG. 1. FIG. 3 is a schematic configuration diagram showing an example of a conventional apparatus for the ion implantation method, and FIG. 4 is a front view showing the state of ion beam scanning on the processing surface of the compound semiconductor substrate in FIG. 3. (1) Ion source, (2') - Compound semiconductor substrate, (3°) - Processing surface, a - Ion beam. Patent applicant Kansai NEC Co., Ltd. Agent Shogo Ebara
Claims (1)
定の角度傾斜させて配置し、上記イオン源から発せられ
た不純物イオンを質量分離並びに加速させた上で、その
イオンビームを走査させながら化合物半導体基板の処理
面に打込んで不純物をドーピングする方法であって、 上記化合物半導体基板の処理面は、化合物半導体の結晶
構造における空間格子の（１００）面から〔０１０〕〔
０＠１１＠〕〔０１＠１＠〕〔０＠１＠１〕方位のいず
れかに略３゜傾斜した面であることを特徴とするイオン
注入方法。[Claims] A compound semiconductor substrate is arranged with its processing surface inclined at a predetermined angle toward an ion source, and impurity ions emitted from the ion source are mass separated and accelerated, and then the ions are A method of doping an impurity by implanting an impurity into a treated surface of a compound semiconductor substrate while scanning a beam, wherein the treated surface of the compound semiconductor substrate is [010] from the (100) plane of the space lattice in the crystal structure of the compound semiconductor. [
0@11@] [01@1@1] [0@1@1] An ion implantation method characterized in that the surface is inclined by approximately 3° in either direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4655190A JPH03248422A (en) | 1990-02-26 | 1990-02-26 | Implantation of ion |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4655190A JPH03248422A (en) | 1990-02-26 | 1990-02-26 | Implantation of ion |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03248422A true JPH03248422A (en) | 1991-11-06 |
Family
ID=12750459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4655190A Pending JPH03248422A (en) | 1990-02-26 | 1990-02-26 | Implantation of ion |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03248422A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006186204A (en) * | 2004-12-28 | 2006-07-13 | Canon Inc | Photoelectric converting device and its manufacturing method, and image pick-up system |
| KR100790230B1 (en) * | 2001-11-27 | 2008-01-02 | 매그나칩 반도체 유한회사 | Fabricating method of Image sensor |
-
1990
- 1990-02-26 JP JP4655190A patent/JPH03248422A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100790230B1 (en) * | 2001-11-27 | 2008-01-02 | 매그나칩 반도체 유한회사 | Fabricating method of Image sensor |
| JP2006186204A (en) * | 2004-12-28 | 2006-07-13 | Canon Inc | Photoelectric converting device and its manufacturing method, and image pick-up system |
| US7541211B2 (en) | 2004-12-28 | 2009-06-02 | Canon Kabushiki Kaisha | Photoelectric conversion device, its manufacturing method, and image pickup device |
| US7977760B2 (en) | 2004-12-28 | 2011-07-12 | Canon Kabushiki Kaisha | Photoelectric conversion device, its manufacturing method, and image pickup device |
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