JPH03248068A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To test write and read of each memory cell block incorporating a complex IC therein by impressing a pulse signal used for write/read of an EPROM block when performing write/read to an SPAM block. CONSTITUTION:When a test mode setting signal 16 is inputted at H level, a CSROM 14 is turned H level by a decoder circuit 18 irrespective of address inputs A1-A8 during the test mode. Therefore, an EPROM block 1 is never selected. On the other hand, since a CSRAM 15 is L level regardless of the address inputs, an SRAM block 2 is selected. In a test mode generating circuit 19, output conversion is conducted between write/verify control signals PRGROM 7 and RDROM 8 to the EPROM block 1, and write/read control signals WRRAM 9 and RDRAM 10 to the SRAM block 2, so that PRGROM 7 is transmitted to a signal which ought to the WRRAM 9. Likewise, RDROM 8 is transmitted to a signal which oughts to the RDRAM 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an apparatus for improving the efficiency of testing the operational functions of a semiconductor integrated circuit device.

[Conventional technology]

FIG. 2 is a block diagram showing an example of a conventional semiconductor integrated circuit device in which different types of memories are integrated into one chip.
rogras+s+able ROM: electrically writable read-only memory), 2 is S RAM (
3.4 are write/read control circuits for the EFROM block 1 and SRAM block 2, 5 is an input buffer circuit for address signals A1 to A8, and 6 is various control signals [ In this example, it is CE (chip select signal).

OE (data output enable signal), R/W (read/
A control signal generation circuit that generates write/read control signals 7 to 10 from memory blocks 1 and 2 from write signals) etc., 11 is an address signal, and 12 is a decoder for selecting each memory block 1.2. A circuit 13 is a data bus for inputting and outputting data between each memory block 1.2 and the outside. 14.15 is the above decoding circuit 1
In this example, when the signal is at "Low" level, it is a low active signal that selects memory block 1.2.

Furthermore, EPROM is used as a power source for semiconductor integrated circuit devices.
VPF is the high voltage for writing to the memory cells in block 1, V is the power supply to the SRAM block,
c is each peripheral circuit including EPROM block 1 (however,
(assuming that the SRAM block 2 is not included) is vo as a power supply, and GND is a reference potential (ground level).

Next, the operation will be explained.

First, in semiconductor integrated circuit devices (hereinafter referred to as composite ICs) that use such different types of memory blocks, address areas are assigned as operating areas for each block in order to perform write and read operations independently. , an example of this situation will be explained using FIG. 3. As shown in FIG.
), and on the other hand, area 32 is an address area for EPROM block 1 (80H to FF in hexadecimal).
), when the above address is input to A1 to A8, it is decoded by the decoding circuit 12 and a low active select signal is generated for each memory block. Address 20. SRAM for I~3F, +
A select signal 15 for block 2 (hereinafter referred to as C5RAM) is generated, and a select signal 14 for EPROM block 1 (hereinafter referred to as C5ROM) is also generated for 80a-FFH.

On the other hand, write/read control signals for each memory block include external input signals such as CE, OE,
The control signal generation circuit 6 generates the signal based on the R/W and the like. For EPROM block l, write pulse signal 7 (hereinafter referred to as PRGROM) and read signal 8 (
Similarly, for the SRAM block 2, a write pulse signal 9 (hereinafter referred to as WRRA) is generated.
M) and a read signal 10 (hereinafter referred to as RDRAM). Furthermore, data is exchanged between each memory block 1.2 and the outside of the composite IC via a data bus 13.

Next, the operation of the composite IC will be explained.

First, the method of writing to the memory cells of EPROM block 1 is to set addresses A1 to A8 to any address between 808 and FF to make C5ROM 14 low active. At this time, C5RAM 15 is - level, and the SRAM block 2 does not operate.Furthermore, each signal such as CE and OB input from the outside and each power supply (VPP is 12.5V at the time of writing, Vnn=6.
OV), the control signal generation circuit 6 generates PR.
Generate GROM signal 7, set the data you want to write,
A desired EPROM memory cell is written via the data bus 13.

Also, the verification method at the time of writing is to set the Ajeres A1-88 in the same way as at the time of writing, and each power supply (■rr=12.
5V, VEIII-6, OV) Color control signal CE, O
By combining with E and setting it to verify mode, R
A DROM signal 8 is generated, and the data of a desired EPROM memory cell is read out and output via the data bus 13 for confirmation.

Write/read operations to SRAM block 2 are also performed by EP.
As in the case of ROM block 1, first address A1~
A8 is set to one of the corresponding addresses 20.4 to 3FN, and the C5RAM signal 15 is made low active.

Further, the power supply is set to VCC-vilI, approximately -5.0V, so that the SRAM block 2 and the peripheral circuit portion can operate. Furthermore, by inputting control signals CE, OE, R/W, etc., the control signal generation circuit 6 generates the WRRAM signal 9.
is generated and the set data is written into a desired memory cell via the data bus 13.

When reading, the same addresses A1 to A8 as when writing are set, and by setting control signals CE, OB, R/W, etc., the RDRAM signal 10 is generated and the desired SRAM is
The data in the memory cell is read and output via the data bus 13.

Furthermore, in such complex IC devices, the built-in EPROM
In order to easily perform write and read operations in memory cells, the memory capacity of the EFROM memory block, the number of control signals, timing settings, etc., are designed to be equivalent to those of a general-purpose EFROM device having the same memory capacity. Often.

Next, the EPROM block 1 as described above. Considering a test method for a composite IC device equipped with an SRAM block 2, an EPROM block 1 and an S
In a composite IC consisting of a RAM block 2, a large LSI tester with full functionality is considered necessary in order to sufficiently test each memory block and related peripheral circuits. The write and read operations can be verified using a commercially available write device and appropriate pin conversion device.

[Problem to be solved by the invention]

Since the conventional semiconductor integrated circuit device is configured as described above, write and verify operations are performed on the EPROM block side using a commercially available write device to confirm its basic operation and also test each EPROM memory cell. However, since there is no such simple means for the SRAM block side, large LSI test equipment is required to check the basic operation, and especially if you do not own such large test equipment. EPRO for general customers
Although it is possible to check the operation of the M block, there is a problem in that it is not possible to perform any tests on the SRAM blocks, particularly the individual SRAM memory cells, which are particularly important.

This invention has been made in view of the above-mentioned problems, and provides a semiconductor integrated circuit in which writing and continuous testing can be performed using a simple device on each memory cell block in which a composite IC is built. The purpose is to obtain equipment.

[Means to solve the problem]

The semiconductor integrated circuit device according to the present invention includes, for example, an EPR
In a composite IC configured using different types of memory blocks such as OM and SRAM, there is a means for inputting a test mode setting signal and a means for writing and writing to each memory block.
A control signal generation circuit that outputs a control signal for reading, a decode circuit that selects one of the memory blocks mentioned above, and a test mode generation circuit that receives the output of the control signal generation circuit and the test mode setting signal as input. When a test mode setting signal is input, one memory is selected by a predetermined select signal, and a write/read control signal to be output to the EPRROM side is output to the SRAM side. writing/
This signal is output in place of the read control signal.

[Effect]

In this invention, with the above configuration, EPRO
SR pulse signal used for writing/reading M block
Since the voltage is also applied and used for writing and reading of AM blocks, it is possible to perform writing and reading tests on each memory cell block in which a composite IC is built using a simple device.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of a semiconductor integrated circuit device according to an embodiment of the present invention, in which the same reference numerals as in FIG. 2 indicate the same or corresponding parts, 16 is an input terminal for a test mode setting signal 17, and 18 is an address A decoder circuit 19 receives the test mode setting signal 17 and the test mode setting signal 17 and the write/read control signals 7 to 10 of each memory block as inputs. , a test mode generation circuit that generates a test mode signal, and is configured by combining logic circuits.

Next, the operation will be explained.

First, when the test mode setting signal 17 is a "Low" level input, each signal C5ROM14 in the conventional example
．． C5RAM15. Control signal PRG for each memory block
ROM7. RDROM8. WRRAM9. RDRAMI
Since the signal system is the same as O, in this case, the operation is exactly the same as in the conventional example, so detailed explanation thereof will be omitted.

On the other hand, when the test mode setting signal 16 is the "old gh" level input, that is, in the test mode, the decoding circuit 18 selects C3 regardless of the address inputs A1 to A8.
Since ROMI 4 is at “H” level, it is always used as EPROM.
Block 1 is unselected.

On the other hand, C5RAM15 is also “L” regardless of the address input.
The SRAM block 2 is in a selected state because it is at the II level.

Furthermore, the test mode generation circuit 19 generates a write/verify control signal PRG for the EPROM block 1.
Write/read control signals WRRAM9 and RDRAMI for ROM7, RDROMB, and SRAM block
An output conversion is performed between the output signal and the PRGROM7, and the signal that should originally be in the WRRAM9 is transmitted to the PRGROM7 (2 in the figure).
Similarly, RDROMB is transmitted to the signal that should originally be RDRAMIO (this is shown as 2 in Figure 1).
1).

As described above, the signal PRGROM7. RDROMB
is applied to both EPROM block 1 and SRAM block 2, but the above-mentioned C8ROM14 and C5RA
Since the SRAM block 2 side is selected by M15, only the SRAM block 2 is in a state where writing and reading operations are possible.

Therefore, the basic pulse waveforms and timings of the control signals PRGROM7 and RDROM8 during the write/verify operation of the EFROM block 1, and the control signals WRRAM9 and RDRAM during the write/read operation of the SRAM block 2.
If the basic pulse waveforms and timings of the IO are compatible between the corresponding signals, writing to and reading from the SRAM block 2 can be executed by the writing and verifying operations of the EPROM block 1.

Further, in the above embodiment, the ROM is an EPROM.

Although the description has been made using an SRAM as the RAM, similar effects can be achieved even if a storage device having another memory structure is used.

Further, the configuration of the test mode generation circuit and the selection signal generation circuit for each memory may also be configured using logic circuits other than these.

〔Effect of the invention〕

As described above, according to the semiconductor integrated circuit device according to the present invention, a pulse signal used for writing/reading an EFROM block is also applied to writing/reading an SRAM block, and the pulse signal is used for writing/reading an SRAM block. Since it is possible to convert write/read control signals between memory blocks, it is possible to convert large LSIs, which are especially expensive test equipment.
Complex ICs that are difficult to test functionally without using test equipment
The present invention has the advantage that it is possible to easily check the basic operation of writing and reading for various memory cells.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional semiconductor integrated circuit device, and FIG. 3 is a block diagram showing a built-in memory (EFROM) in a conventional semiconductor integrated circuit device. , SRAM). 1...EFROM block, 2...SRAM block, 3...EFROM write/read circuit, 4...
SRAM write/read circuit, 5...input buffer circuit, 6...control signal generation circuit, 7...PRGROM
(ROM write signal), 8...RDROM (RO
M verify signal), 9...WRRAM (RAM write signal), 10...RDRAM (RAM read signal), 11...address signal, 12.18...decode circuit, 13...data bus, 14...C5RO
M (ROM select signal), 15...C5RAM
(RAM select signal), 16... signal input terminal for test mode setting, 17... signal for test mode setting,
19...Test mode generation circuit, 20...PRGROM signal in test mode, 21...R in test mode
DROM signal, 31...SRAM address area, 32
...EPROM address area, VPP...EPRO
M write power supply, VCc-3 RAM independent power supply, V, D
・EPROM2 peripheral circuit power supply, GND...Reference potential (ground level). Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A semiconductor memory device in which a plurality of memory blocks each consisting of independently operable ROM or RAM are arranged on one chip, and includes means for inputting a test mode setting signal and each memory block. a control signal generation circuit that outputs a write/read control signal for writing/reading to each write/read circuit; and a control signal generating circuit that outputs a write/read control signal for writing/reading to each write/read circuit; A decoding circuit that generates a select signal and selects one of the memory blocks mentioned above, and receives the output of the control signal generation circuit and the test mode setting signal as input, and outputs it to the EPRROM side when the test mode setting signal is input. 1. A semiconductor integrated circuit device comprising: a test mode generating circuit that outputs a write/read control signal to be used instead of the write/read control signal output to the SRAM side.