JPH0324781B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a thyristor, and more particularly to a method for manufacturing a thyristor that reduces the surface level of a thyristor device in which a pn junction is exposed on the surface.

In general, in semiconductor devices such as MOS devices and bipolar ICs that have a pn junction on the surface of a semiconductor substrate and operate by controlling the current and electric field near the surface, there is no effect through a channel formed near the surface of the pn junction. Current flows, often resulting in deterioration of device characteristics. This is because an insulating film such as SiO ₂ or Si ₃ N ₄ is generally provided to cover the exposed part of the pn junction, and a charge layer is also formed on the semiconductor surface due to the charge contained in this insulating film. This occurs because the charges in the charge layer move when a bias is applied to the pn junction.
To solve this problem, hydrogen annealing technology has traditionally been used to reduce the effective charge by doping impurity atoms into the insulating film, or to reduce the effective charge by utilizing the reduction effect of hydrogen. .

On the other hand, power devices such as thyristors and gate turn-off thyristors (hereinafter referred to as GTOs) that carry several hundred amperes have an extremely small ratio of reactive current/carrying current, so a channel is formed in the region where control current and voltage are applied. was not a big problem in the past. In other words, it is composed of the n-emitter, p-base, and n-base of a general power thyristor.
The current amplification factor αnpn of an npn transistor is approximately 0.90, while that of a small bipolar transistor
hFE is normally 500 to 1000, and when converted to α, it is 0.998 to 0.999. However, among power thyristors, in a thyristor with a structure in which the cathode electrode is divided into multiple parts, such as the GTO, the circumference of the emitter junction formed by the n-emitter and p-base is several times larger than that of a general thyristor.
Since it increases from 10 times to 100 times, the channel effect cannot be ignored. In other words, the total length of the emitter junction of a general thyristor with a diameter of 5 cm is 15.7 cm, whereas
The total length of the GTO emitter joint is 8000 rectangular emitters with a length of 0.6 mm and a width of 0.15 mm in a diameter of 5 cm.
The length is 12m, and the latter/former ratio is 76.
In other words, assuming that the reactive current per unit length of the emitter junction is constant, the GTO is 76
Double the amount of reactive current will flow through the emitter junction. In other words, holding other conditions constant, GTO
The αnpn of the thyristor is lower than that of the thyristor.

On the other hand, the power thyristor package generally uses a flat pressure contact type, so if it goes through reliability tests such as thermal fatigue testing (TFT), the metal of the cathode electrode that is subjected to pressure contact will sag and the gate Short-circuit accidents due to contact with electrode metal frequently occur. To prevent this, a structure is used in which the gate electrode metal is coated with an insulating material. Insulating materials include polymeric insulating materials such as SiO ₂ , Si ₃ N ₄ , CVD films, glass materials, and solid film polyimide.
A polymer insulating material such as polyimide is suitable because it can form a relatively thick film and does not cause cracks.

FIG. 1 shows a conventional method for manufacturing a semiconductor device having a thyristor structure. Here for power
The conventional technology will be explained using GTO as an example. First, a p-type impurity source such as gallium or boron is diffused from both sides of an n-type Si substrate 1 with an average impurity concentration of 10 ¹² to 10 ¹⁴ cm ^-3 to form three layers, p-layer 2, n-layer 3, and p-layer 4. Form. (FIG. 1b) Next, an n-type impurity source such as phosphorus is diffused from one side to form an n-layer 5, resulting in four npnp layers. (FIG. 1c) Next, a groove 7 for separating the n-layer 5 and the p-layer 2 is formed in the main surface 6, and the n-layer 5, which will become a cathode, is divided into a plurality of pieces. (Fig. 1d) Next, after diffusing a lifetime killer such as gold from the main surface 8 side, an insulating film such as SiO 2 is formed to passivate the pn junction formed between the n layer 5 and the p layer ₂ .
Coat the membrane 9. (Fig. 1 e) Next, to form electrodes, the insulating film 9 of the n layer 5 to become the cathode, the p layer 2 to become the gate, and the p layer 4 to become the anode.
are removed at predetermined locations and metals such as Al, V, Ni, and Av are vapor-deposited or sputtered to form cathode electrodes 1.
0, a gate electrode 11 and an anode electrode 12 are formed. Sintering is performed to make low-resistance contact between these metals and semiconductors. At this time, annealing is frequently performed in a hydrogen atmosphere through the porous insulating film 9 to reduce the surface level at the emitter junction interface. Next, a polymer insulator 13 such as polyimide is applied to the groove 7 of the gate, and then a lead wire 14 is bonded to take out the gate electrode 11 to the outside. Although it is then sealed in a flat envelope, it is not directly related to the present invention and will therefore be omitted.

Using conventional manufacturing technology as explained above,
In GTO, the holding current I _H and on-voltage V _TM characteristics eventually deteriorate. This is because αnpn, which had once increased due to hydrogen annealing, is reduced by baking in nitrogen after coating the polyimide.

The present invention has been made to address the above drawbacks.
It is an object of the present invention to provide a method for manufacturing a thyristor, which increases αnpn of the final thyristor element by performing a hydrogen annealing step after coating polyimide, thereby obtaining favorable thyristor characteristics such as low holding current and low on-voltage.

The present invention involves a step of dividing an n-emitter into a plurality of pieces on one main surface of a semiconductor substrate mainly composed of four pnpn layers formed by diffusion, exposing the n-emitter and the p-base, and the process of exposing the n-emitter and p-base. , selectively covering the p-based junction with an insulator such as _SiO2 ;
A step of bonding metal for making ohmic contact to the n-emitter, p-base, and p-emitter to form the cathode, gate, and anode electrodes, respectively, and then annealing in a hydrogen atmosphere;
It is characterized by sequentially performing a step of covering with a polymer insulator having a thickness of 2 μm or more and a step of annealing at 480° C. in a hydrogen atmosphere.

In order to clearly contrast the present invention with the prior art, FIG. 2a shows the thyristor manufacturing method of the present invention, and FIG. 2b shows the conventional method. The difference between the present invention and the conventional method is whether or not annealing in a hydrogen atmosphere is performed in the final step of the thyristor manufacturing method. According to the present invention, αnpn is high due to the above-described effects, and as a result, holding current I _H is low and on-voltage V _TM is low.

The differences in these properties were clarified by the following examples. Average impurity concentration is 1×10 ¹⁴ cm ^-3 thickness
Gallium is diffused as an impurity source from both sides of a 300 μm n-type substrate to form a PNP. The surface impurity concentration of the p layer was 1×10 ¹⁸ cm ⁻³ and the layer thickness was 50 μm.
Next, phosphorus is diffused onto one side as an impurity source to form pnpn. The surface impurity concentration of the n emitter layer is 4×
10 ²⁰ cm ^-3 , and the thickness of the n-layer was 12 μm. Then n
Using photolithography and etching, a recess is provided on the emitter side at the location where the gate is to be formed, thereby dividing the n emitter into a plurality of parts and exposing the p base.
In this example, the depth of the recess was 20 μm. Next, the exposed n-emitter and p-base junctions are coated with SiO ₂ to a thickness of about 5000 Å using photolithography.

Next, the thickness of the cathode, gate, and anode electrodes is
It was formed by evaporating 10 μm of aluminum. The anode electrode was further eutecticized with a 2 mm thick tungsten plate as a temperature insulating plate. Then about
Annealing was performed for 10 minutes in a hydrogen atmosphere at 500°C. For convenience, this step is referred to as the first hydrogen annealing. Next, polyimide was applied onto the gate electrode, baked in air at 300°C, and then annealed again for 10 minutes in a hydrogen atmosphere at about 500°C. For convenience, this step is referred to as second hydrogen annealing. After that, we sandblast the periphery of the semiconductor substrate, etch that area to create the main breakdown voltage, and encapsulate silicone rubber for passivation.
We made full use of the well-known thyristor technology in which the gate lead wire is bonded and enclosed in a flat envelope.

Figure 3 shows the holding current in the first hydrogen annealing, polyimide baking, and second hydrogen annealing steps.
Shows the characteristics of _IH . As can be seen from the figure, the I _H of the present invention (solid line → a) is 1A, while the conventional method (dotted line →
The I _H of b) is 40A, and the effect of the present invention is clear. As for other characteristics, αnpn is 0.98 according to the present invention.
The conventional method had a V _TM of 0.89, whereas the present invention had a V TM of 1.3 V, whereas the conventional method had a V TM of 2.1 V. The conditions for the second hydrogen annealing are hardly affected by the annealing time, but are strongly affected by the annealing temperature. For annealing temperature with constant annealing time of 10 minutes
Looking at the _IH characteristics, we found that there was almost no change in _IH below 450°C;
It was 40A, but it decreased rapidly above 450℃, and it decreased to 480℃.
With the above, the current was almost constant at 3A to 1A. Therefore, the second hydrogen annealing temperature needs to be 480°C or higher.

Furthermore, when insulating polyimide is heat-treated at temperatures above 400°C, part of it evaporates and the film thickness decreases. Reliability tests on TFTs and other devices revealed that this resulted in poor insulation between the cathode and gate electrodes. When we investigated the thickness of polyimide coating and the frequency of short circuits between electrodes, we found that when the polyimide thickness was 2 μm or more, no short circuits occurred between electrodes, and when the thickness was less than 2 μm, the frequency of short circuits increased as the thickness decreased. Therefore, it is necessary to apply the polyimide to a thickness of 2 μm or more.

Note that the above embodiments have been shown for the case where the cathode electrode is formed in one layer, but when another layer of cathode electrode is wired on top of the polyimide coated on the gate electrode, that is, two layers in total, the cathode electrode is wired. Naturally, the present invention is also applicable to the above. In that case, a feature of the present invention is to perform hydrogen annealing after all electrode metal wiring and polyimide coating.

[Brief explanation of drawings]

Figure 1 is a process diagram of the conventional thyristor manufacturing method.
FIG. 2 is a process flowchart of a thyristor manufacturing method comparing the present invention and the conventional method, and FIG. 3 is a diagram showing the GTO holding current I _H measured in each step. 1: n-type Si substrate, 2, 4: p layer, 3, 5: n
Layer, 9: SiO ₂ film, 10: Cathode electrode, 11:
Gate electrode, 12: anode electrode.

Claims (1)

[Claims] 1. A process of exposing two types of semiconductor layers of different conductivity types, at least one of which is divided into a plurality of pieces, on one main surface of a semiconductor substrate having a main structure of four pnpn layers, and a process of exposing two types of semiconductor layers, at least one of which is divided into a plurality of pieces, on one main surface of a semiconductor substrate having a main structure of four pnpn layers, and a process of exposing a pn junction exposed on the semiconductor surface. a step of selectively providing an insulating material on the two
A step of selectively coating the surfaces of each type of semiconductor with a metal and annealing in a hydrogen atmosphere, and a step of coating the surface of one of the metal layers formed on the surfaces of the two types of semiconductors and the insulating material with a thickness of 2 μm or more. A method for manufacturing a thyristor comprising a step of covering the thyristor with a thick polymeric insulating material, the method comprising: performing heat treatment at 480° C. or higher in an atmosphere containing hydrogen gas after all of the above steps.