JPH0324724A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0324724A JPH0324724A JP15815889A JP15815889A JPH0324724A JP H0324724 A JPH0324724 A JP H0324724A JP 15815889 A JP15815889 A JP 15815889A JP 15815889 A JP15815889 A JP 15815889A JP H0324724 A JPH0324724 A JP H0324724A
- Authority
- JP
- Japan
- Prior art keywords
- conductive material
- substrate
- plasma flow
- etching gas
- connection hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000004020 conductor Substances 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 238000000034 method Methods 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 27
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 abstract description 12
- 239000002184 metal Substances 0.000 abstract description 12
- 239000011229 interlayer Substances 0.000 abstract description 11
- 230000000694 effects Effects 0.000 abstract description 6
- 238000004381 surface treatment Methods 0.000 abstract description 5
- 230000008021 deposition Effects 0.000 abstract description 3
- 230000008030 elimination Effects 0.000 abstract 1
- 238000003379 elimination reaction Methods 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 21
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- 238000002844 melting Methods 0.000 description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 239000012159 carrier gas Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 2
- MCULRUJILOGHCJ-UHFFFAOYSA-N triisobutylaluminium Chemical compound CC(C)C[Al](CC(C)C)CC(C)C MCULRUJILOGHCJ-UHFFFAOYSA-N 0.000 description 2
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 2
- KPZGRMZPZLOPBS-UHFFFAOYSA-N 1,3-dichloro-2,2-bis(chloromethyl)propane Chemical compound ClCC(CCl)(CCl)CCl KPZGRMZPZLOPBS-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910018503 SF6 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 210000002784 stomach Anatomy 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、基板上の眉間絶縁膜に開口した接続孔に導電
材料を埋め込む多層配線構造を有する半導体装置の製造
方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device having a multilayer wiring structure in which a conductive material is embedded in a contact hole opened in a glabellar insulating film on a substrate.
本発明は、層間絶縁膜に開口した接続孔を有する基板に
対し、導電材料を堆積する工程を施しながら、またはこ
の工程と交互に接続孔以外の層間絶縁膜上等に堆積した
不要な導電材料を、エッチングガスの電子サイクロトロ
ン共鳴(ECR)プラズマ流により選択的にエッチング
除去する工程を施すことにより、接続孔に選択的に導電
材料を埋め込むことを特徴とする半導体装置の製造方法
に関する。The present invention deals with the process of depositing a conductive material on a substrate having a contact hole opened in an interlayer insulating film, or alternately with this process, unnecessary conductive material is deposited on an interlayer insulating film other than the contact hole. The present invention relates to a method of manufacturing a semiconductor device, characterized in that a conductive material is selectively buried in a contact hole by performing a step of selectively etching and removing a conductive material using an electron cyclotron resonance (ECR) plasma flow of an etching gas.
LSI等の半導体装置の集積度の進展と共に、多層配線
技術の重要性が高まっている。中でも基板上の層間絶縁
膜に開口した接続孔は、その外径が微細化し、アスペク
ト比が例えば1以上と大きな値が用いられつつある。As the degree of integration of semiconductor devices such as LSIs progresses, the importance of multilayer wiring technology is increasing. Among these, the outer diameter of a contact hole opened in an interlayer insulating film on a substrate is becoming finer, and a larger aspect ratio of, for example, 1 or more is being used.
この接続孔を導電材料で埋め込む方法としては、タング
ステン(一)等高融点金属の選択CVDによる方法が代
表的なものである。これは、例えばソースガスとしての
67フ化タングステン(WFJが、シリコン(Si)や
アルミニウム(AI)等の金属表面上で選択的に還元さ
れ、一が選択的に戒長ずる反応を利用するものである。A typical method for filling this contact hole with a conductive material is selective CVD of a high melting point metal such as tungsten (1). This utilizes a reaction in which, for example, 67 tungsten fluoride (WFJ) as a source gas is selectively reduced on the surface of a metal such as silicon (Si) or aluminum (AI), and 1 is selectively reduced. It is.
高融点金属の選択威長は、実際には金属表面以外にも部
分的に堆積してしまったり、金属表面であってもその材
質や表面状態の差異により選択戒長の難易性がみられた
。すなわち、下地となる金属面にコンタミネーションが
あったり、自然酸化膜が形威されていると、選択威長は
大幅に阻害された。In fact, it is difficult to select high-melting point metals due to the fact that they are deposited on parts other than the metal surface, and even on metal surfaces, due to differences in the material and surface condition. . In other words, if there was contamination or a natural oxide film on the underlying metal surface, the selectivity was significantly inhibited.
従来の方法による接続孔への導電材料の埋め込み状態を
示す断面図である第3図により、この様子を説明する.
同図は、基板1上の層間絶縁膜2に開口した接続孔3に
W等の高融点金属による導電材料4を選択成長した場合
である。This situation will be explained with reference to FIG. 3, which is a cross-sectional view showing a state in which a conductive material is embedded in a contact hole using a conventional method.
This figure shows a case where a conductive material 4 made of a high melting point metal such as W is selectively grown in a contact hole 3 opened in an interlayer insulating film 2 on a substrate 1.
ここで見られるように、従来の選択CVDにおいては、
眉間絶縁膜2等の上にも部分的に導電材料4aが堆積し
、半導体装置の信頼性に歩留りの低下をきたしていた。As seen here, in conventional selective CVD,
The conductive material 4a was partially deposited on the glabella insulating film 2, etc., resulting in a decrease in reliability and yield of the semiconductor device.
そこで、接続孔への一等の高融点金属の選択或長の際の
選択比の向上を意図し、接続孔底部に露出したSt基板
や下層配線の表面、あるいは接続孔内壁の表面処理を行
う検討がなされている(例えば1989年春季第36回
応用物理学関係連合講演会講演予稿集、講演番号3p−
ZF−3等所載)。Therefore, with the intention of improving the selection ratio when selecting and lengthening a first-class high-melting point metal for the connection hole, surface treatment is performed on the surface of the St substrate and lower layer wiring exposed at the bottom of the connection hole, or on the inner wall of the connection hole. (For example, Proceedings of the 36th Spring 1989 Lectures of the Applied Physics Association, Lecture No. 3 p.
ZF-3 etc.).
上述した従来法においては、接続孔の孔径が微細化し、
かつアスペクト比が大きくなってくると、必ずしも充分
な表面処理を行うことができず、信頼性に優れた選択威
長を行うことが困難となってきた。In the conventional method described above, the diameter of the connection hole is reduced,
In addition, as the aspect ratio increases, it is not always possible to perform sufficient surface treatment, making it difficult to perform selective enhancement with excellent reliability.
そこで本発明の課題は、基板上の層間絶縁膜に開口した
接続孔に導電材料を選択的に埋め込む多層配線構造を有
する半導体装置の製造方法において、接続孔底部や側壁
に特別な表面処理を施すことなしに、導電材料を確実に
埋め込む方法を提供することである。Therefore, an object of the present invention is to apply special surface treatment to the bottoms and side walls of the contact holes in a method for manufacturing a semiconductor device having a multilayer wiring structure in which a conductive material is selectively buried in contact holes opened in an interlayer insulating film on a substrate. It is an object of the present invention to provide a method for reliably embedding a conductive material without causing any damage.
本発明による半導体装置の製造方法は、ECRプラズマ
装置のプロセスチャンバ内において、次のイ、ロの2種
類の工程を同時に、または交換に行うことを特徴とする
。The method for manufacturing a semiconductor device according to the present invention is characterized in that the following two steps (a) and (b) are performed simultaneously or alternately in a process chamber of an ECR plasma apparatus.
イ.基板上に導電材料を堆積する工程。stomach. The process of depositing a conductive material onto a substrate.
堆積方法としては、通常の選択CVDまたは非選択的な
プランケッ}CVDのいずれでもよい。The deposition method may be either conventional selective CVD or non-selective Plunket CVD.
本工程は、ECRプラズマ装置のプロセスチャンバを減
圧CVD室として用いるものであり、ECRプラズマ装
置のECRプラズマ発生機能を直接的に用いるものでは
ない。This step uses the process chamber of the ECR plasma device as a reduced pressure CVD chamber, and does not directly use the ECR plasma generation function of the ECR plasma device.
ロ、基板をエッチングガスのECRプラズマ流の主軸に
対して斜めに配置し、該エッチングガスのECRプラズ
マ流により、前記イの工程により基板上に堆積した導電
材料を選択エッチングする工程。B. A step of arranging the substrate obliquely with respect to the main axis of the ECR plasma flow of the etching gas, and selectively etching the conductive material deposited on the substrate in step A above by the ECR plasma flow of the etching gas.
この工程で用いるエッチングガスは、導電材料と眉間絶
縁膜とのエッチングの選択比が充分大きくとれるもので
あればよい。The etching gas used in this step may be any gas that can provide a sufficiently large etching selectivity between the conductive material and the glabellar insulating film.
ECRプラズマ流の主軸に対し基板を斜めに保持する角
度は、ECRプラズマ流そのものが必ずしも平行流とは
限らないので、特に限定を設けるものではないが、本発
明の目的を達成するためには、概ね10″C〜80゜C
の角度が選ばれる。このとき、基板をECRプラズマ流
の主軸に対し斜めに固定して保持してもよく、連続的に
あるいは段階的に保持角度に変化を持たせてもよい。ま
た基板を斜めに保持したまま、基板面内で回動または自
転させてもよい。The angle at which the substrate is held diagonally with respect to the main axis of the ECR plasma flow is not particularly limited since the ECR plasma flow itself is not necessarily a parallel flow, but in order to achieve the purpose of the present invention, Approximately 10″C to 80°C
The angle is selected. At this time, the substrate may be fixed and held obliquely to the main axis of the ECR plasma flow, or the holding angle may be varied continuously or stepwise. Alternatively, the substrate may be rotated or rotated within the plane of the substrate while being held obliquely.
ECRプラズマ装置のプロセスチャンバ中で基板を載置
するサセプタに加熱機構を設けたり、あるいはランプ照
射により基板を加熱して、導電材料の堆積速度の増大を
図ることも可能である。It is also possible to increase the deposition rate of the conductive material by providing a heating mechanism in the susceptor on which the substrate is placed in the process chamber of the ECR plasma apparatus, or by heating the substrate by lamp irradiation.
なお、本発明による前記手段に近似した従来技術として
、ECRプラズマCVD装置による基板上へのステップ
力バレッジのよい絶縁膜の形或方法がある(特開昭62
−133725号公報所載)。本発明はECRプラズマ
装置をエッチング手段として用いるものであり、ECR
プラズマ発生手段とは直接の関連なく別個に減圧CVD
手段を設けたものであり、前記従来例とは目的、手段及
び効果とも異なるものであることは明らかである。As a conventional technique similar to the above-mentioned means according to the present invention, there is a method of forming an insulating film with a good stepping force barrier on a substrate using an ECR plasma CVD apparatus (Japanese Patent Application Laid-Open No. 62-2011).
- Published in Publication No. 133725). The present invention uses an ECR plasma device as an etching means.
Low pressure CVD separately without direct connection with plasma generation means
It is clear that the purpose, means, and effect are different from those of the conventional example.
前記千段イにより、基板上の層間絶縁膜に開口した接続
孔内部には、選択的にまたは非選択的に導電材料が堆積
される。The conductive material is selectively or non-selectively deposited inside the connection hole opened in the interlayer insulating film on the substrate by the 1,000-stage step.
次に前記手段口により、エッチングガスのECRプラズ
マ流に直接さらされる、層間絶縁膜上等に堆積した導電
材料は、選択的にエッチング除去される。一方、接続孔
内部に堆積した導電材料は、眉間絶縁膜のシャドウイン
グ効果により、エッチング除去されることなしに堆積の
みが進行することとなる。Next, the conductive material deposited on the interlayer insulating film and the like, which is directly exposed to the ECR plasma flow of the etching gas, is selectively etched away by the means port. On the other hand, the conductive material deposited inside the contact hole is not etched away due to the shadowing effect of the glabellar insulating film, and only the deposition progresses.
ECRプラズマ流による導電材料と眉間絶縁膜とのエッ
チングの選択比が充分に大きいエッチングガスを用いる
ので、眉間絶縁膜がエッチングされて膜厚が減少したり
、接続孔のプロファイルが悪化することはほどんどない
。Since we use an etching gas that has a sufficiently high etching selectivity between the conductive material and the glabellar insulating film by the ECR plasma flow, it is unlikely that the glabellar insulating film will be etched and its thickness will be reduced or the profile of the connection hole will deteriorate. Not many.
以上の作用により、選択CVDはもとより、非選択的な
ブランケットCVDによっても、接続孔内部のみに導電
材料を確実に埋め込むことか可能となる。Due to the above-described effects, it becomes possible to reliably embed the conductive material only inside the connection hole not only by selective CVD but also by non-selective blanket CVD.
また従来、同一基板上の深さの異なる接続孔を導電材料
で埋め込むにあたっては、深い接続孔を充分に埋め込む
と、浅い接続孔では導電材料がオーバーグロースする現
象が見られた。しかし本発明によれば、このような現象
を生ずることなく、深さの異なる接続孔を同時に、しか
も均一に埋め込むことが可能となる。Conventionally, when connecting holes with different depths on the same substrate are filled with a conductive material, a phenomenon has been observed in which when the deep connecting holes are sufficiently filled, the conductive material overgrows in the shallow connecting holes. However, according to the present invention, connection holes of different depths can be filled simultaneously and uniformly without causing such a phenomenon.
以下、本発明の実施例について図面を参照しながら説明
する。Embodiments of the present invention will be described below with reference to the drawings.
第1図は、本発明の実施例による半導体装置の製造方法
に供する装置の概略断面図である。同図において2.4
5GHzのマイクロ波がマイクロ波導波管14によりE
CRプラズマ室l6に導入され、マグネットコイル15
により発生する略900Gauss磁場とともに、エッ
チングガス導入孔12からのエッチングガスをプラズマ
化する。プラズマはECRプラズマ流11となり、プロ
セスチャンバ17へ導入される。プロセスチャンバl7
は、CVDガス導入孔l3と、図示せざる真空ポンプに
連結された排気孔l9を備えている。FIG. 1 is a schematic cross-sectional view of an apparatus used in a method of manufacturing a semiconductor device according to an embodiment of the present invention. In the same figure, 2.4
The 5 GHz microwave is transmitted to E by the microwave waveguide 14.
Introduced into CR plasma chamber l6, magnet coil 15
Together with the approximately 900 Gauss magnetic field generated by this, the etching gas from the etching gas introduction hole 12 is turned into plasma. The plasma becomes an ECR plasma stream 11 and is introduced into the process chamber 17. Process chamber l7
is equipped with a CVD gas introduction hole l3 and an exhaust hole l9 connected to a vacuum pump (not shown).
シリコンウエハ等の基板lは、ECRプラズマ流の主軸
11aに対し、略10゜C〜80゜Cの間の可変角度で
斜めに配置されたサセプタ18に[置保持される。サセ
ブタ18は、基板1を載置したまま基板lの面内で回動
または自転可能に構戒する。またこのサセプタl8には
、例えば抵抗加熱ヒータが内蔵されており、基板1を所
望の温度に加熱することが可能である。A substrate 1, such as a silicon wafer, is held on a susceptor 18 that is disposed obliquely at a variable angle between approximately 10° C. and 80° C. with respect to the main axis 11a of the ECR plasma flow. The susceptor 18 is rotatable or rotatable within the plane of the substrate 1 with the substrate 1 placed thereon. Further, the susceptor l8 has a built-in resistance heater, for example, and can heat the substrate 1 to a desired temperature.
以上のように構成されたECRプラズマ装置において、
本実施例では接続孔を一等の高融点金属で選択的に埋め
込む方法につき説明する。In the ECR plasma device configured as above,
In this embodiment, a method of selectively filling connection holes with a high-melting point metal of first grade will be explained.
第2図(a)〜(C)は、本発明の実施例による半導体
装置の製造方法の概略工程図である。同図(a)におい
て、基板1上の酸化シリコン(Sift)等による層間
絶縁膜2には、アスペクト比の大きな接続孔3が開口し
ている。この基板1をECRプラズマ流の主軸11aに
対し、略45゜の角度で斜めに配置したサセブタ18に
載置し、例えば260゜Cに加熱する。FIGS. 2(a) to 2(C) are schematic process diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention. In FIG. 1A, a contact hole 3 having a large aspect ratio is opened in an interlayer insulating film 2 made of silicon oxide (Sift) or the like on a substrate 1. As shown in FIG. This substrate 1 is placed on a susceptor 18 disposed obliquely at an angle of approximately 45 degrees with respect to the main axis 11a of the ECR plasma flow, and heated to, for example, 260 degrees Celsius.
エッチングガス導入孔12から、6フッ化硫黄(SF&
)を50secm導入し、マイクロ波導波管l4から導
入する2.45GHzのマイクロ波およびマグネットコ
イルl5からの略900Gaussの磁場によりプラズ
マ化する。プラズマ化したエッチングガスは、ECRプ
ラズマ流11となってプロセスチャンバ17内へ導電さ
れ、基板lに照射される。同時にCVDガス導入孔l3
よりソースガスとして例えば6フッ化タングステン(W
F &)を10secm,シラン(Sill4)を6s
ecm,キャリアガスとして水素(L)1000scc
a+の混合ガスを導入し、排気孔9より真空ポンプで排
気して、プロセスチャンバl7内を例えば0.5Tor
rの減圧雰囲気とし、選択CVD法により基板lの接続
孔3中に一を選沢或長させる。堆積したHは、ECRプ
ラズマ流1lに直接さらされる部分については、SFb
プラズマにより直ちにエッチング除去されているので、
結果として第2図(b)のように層間絶縁膜2のシャド
ウとなる接続孔部分にのみ導電材料4となり堆積し、接
続孔の埋め込みが行なわれるのである。From the etching gas introduction hole 12, sulfur hexafluoride (SF&
) is introduced for 50 seconds and turned into plasma by a 2.45 GHz microwave introduced from the microwave waveguide l4 and a magnetic field of about 900 Gauss from the magnet coil l5. The etching gas turned into plasma becomes an ECR plasma flow 11, is conducted into the process chamber 17, and is irradiated onto the substrate l. At the same time, CVD gas introduction hole l3
For example, tungsten hexafluoride (W
F&) for 10sec, silane (Sill4) for 6s
ecm, hydrogen (L) 1000scc as carrier gas
A mixed gas of a+ is introduced and evacuated from the exhaust hole 9 with a vacuum pump to set the inside of the process chamber 17 to, for example, 0.5 Torr.
Under a reduced pressure atmosphere of r, a selective length is formed in the connection hole 3 of the substrate l by selective CVD. The deposited H is SFb for the part directly exposed to the ECR plasma flow 1l.
Because it is immediately etched away by plasma,
As a result, as shown in FIG. 2(b), the conductive material 4 is deposited only in the shadow of the interlayer insulating film 2, filling the contact hole.
本実施例において、基板1をその面内で回動または自転
させながらHの選択戒長およびECRプラズマエッチン
グを同時に行えば、第2図(C)に示すごとく均一性よ
く導電材料4を埋め込むことが可能となる。In this embodiment, if selective etching of H and ECR plasma etching are performed simultaneously while rotating or rotating the substrate 1 within its plane, the conductive material 4 can be embedded with good uniformity as shown in FIG. 2(C). becomes possible.
本発明においては選択CVDに限らず、非選択的なブラ
ンケットCVDにおいても接続孔3内に導電材料4を埋
め込むことが可能である.この場合は前記した選択CV
Dによる埋め込み法に準拠し、基板温度を例えば450
゜Cと高温に保持することにより達威される。In the present invention, it is possible to embed the conductive material 4 in the connection hole 3 not only by selective CVD but also by non-selective blanket CVD. In this case, the selection CV mentioned above
According to the embedding method according to D, the substrate temperature is set to 450℃, for example.
It is achieved by maintaining the temperature at a high temperature of °C.
勿論、選択CVD法においても、選択成長比が不充分で
前記従来例で述べたように眉間絶縁膜2?に部分的に配
線材料4aが堆積する場合であっても、これはECRプ
ラズマ流11によりエッチング除去され、接続孔3への
選択的な埋め込みが確実に行なわれる。Of course, even in the selective CVD method, the selective growth ratio is insufficient and as described in the conventional example, the glabella insulating film 2? Even if the wiring material 4a is partially deposited on the contact hole 3, it is etched away by the ECR plasma flow 11, and selective filling into the contact hole 3 is ensured.
本実施例においては導電材料4として匈を用いたが、ア
ルミニウム(AI)やポリシリコン(p−Si)等を用
いることも可能である。AIの場合はソースガスとして
トリ・イソブチルアルミニウム(TIBA)やトリメチ
ルアルミニウム(TM^〉を、キャリアガスとしてアル
ゴン(Ar)を、そしてエッチングガスとして3塩化ホ
ウ素(BC13)や塩素(CI■)を用いればよい.ま
たp−Stの場合は、ソースガスとしてSiH4やジシ
ラン(SiJb)を、キャリアガスとしては同じく^r
を用い、エッチングガスとしては4塩化シラン(SiC
la)やCI.を用いればよい.〔発明の効果〕
以上詳述したように、本発明によれば基板上の眉間絶縁
膜に開口したアスペクト比の大きい微細な接続孔内を、
W 、AIまたはp−Si等の導電材料により、確実に
信頼性高く埋め込むことが可能となった。In the present embodiment, metal was used as the conductive material 4, but it is also possible to use aluminum (AI), polysilicon (p-Si), or the like. In the case of AI, triisobutylaluminum (TIBA) or trimethylaluminum (TM^) is used as a source gas, argon (Ar) is used as a carrier gas, and boron trichloride (BC13) or chlorine (CI■) is used as an etching gas. In the case of p-St, use SiH4 or disilane (SiJb) as the source gas and the same as the carrier gas.
silane tetrachloride (SiC) was used as the etching gas.
la) and CI. You can use [Effects of the Invention] As detailed above, according to the present invention, the inside of the fine connection hole with a large aspect ratio opened in the glabella insulating film on the substrate,
Conductive materials such as W 2 , AI or p-Si allow reliable and reliable implantation.
導電材料の埋め込み方法は選沢CVD、非選択的なプラ
ンケッ}CVDの別を問わず、接続孔内のみに堆積させ
ることができる。Regardless of the method of embedding the conductive material, selective CVD or non-selective Plunket CVD, the conductive material can be deposited only in the connection hole.
これにより、従来の選沢CVDによる埋め込みにおいて
、選択比向上のために配慮が必要であった、接続孔底部
に露出した金属面の自然酸化膜の除去や、側壁を含めた
表面処理等が不要となり、再現性よく導電材料を埋め込
むことが可能となり、本発明が半導体装置製造工程に及
ぼす寄与は大きなものがある。This eliminates the need to remove the natural oxide film on the metal surface exposed at the bottom of the connection hole and to treat the surface including the sidewalls, which were necessary to improve the selectivity when filling with conventional CVD. Therefore, it becomes possible to embed a conductive material with good reproducibility, and the present invention makes a significant contribution to the semiconductor device manufacturing process.
2・一・一・一・・・・一層間絶縁膜
3・−・−・−・・一接続孔
4 −−−−−・・・一−−−一導電材料11−−−−
−−−−−−−−−−−E C Rプラズマ流11a−
・・一・・・一ECRプラズマ流の主軸12−・・−一
−−−・・一 エッチングガス導入孔l3・一・−・・
−・−C V Dガス導入孔14−・一−一一−−・・
一・・−マイクロ波導波管1 6−−−−−−・−−−
−−−−−E C Rプラズマ室17−・−−−−−−
・−・−プロセスチャンバ18−−−−−−・−−一−
一・−サセプタ2.1.1.1...1 interlayer insulating film 3...1 connection hole 4 -------...1---1 conductive material 11----
-----------E CR plasma flow 11a-
...1...1 ECR plasma flow main axis 12--1--1 Etching gas introduction hole l3-1...
-・-C V D gas introduction hole 14-・1-11--・
1...-Microwave waveguide 1 6-------------
------E CR plasma chamber 17-----
・−・−Process chamber 18−−−−−・−−1−
-Susceptor
第1図は本発明の実施例による半導体装置の製造方法に
供する装置の概略断面図、第2図は本発明の実施例によ
る半導体装置の製造方法の概略工程図、そして第3図は
従来の方法による接続孔への導電材料の埋め込み状態を
示す断面図である。
i 一−一・−−−・−−−−・・・基1反第1図
(a)
(b)
(C)
馬2図FIG. 1 is a schematic cross-sectional view of an apparatus used in a method of manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a schematic process diagram of a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. FIG. 3 is a cross-sectional view showing a state in which a conductive material is embedded into a contact hole by a method. i 1-1・---・----...Group 1 anti-Figure 1 (a) (b) (C) Horse 2 figure
Claims (1)
置の製造方法であって、 イ、基板上に導電材料を堆積する工程、 ロ、基板をエッチングガスの電子サイクロトロン共鳴プ
ラズマ流の主軸に対して斜めに配置し、該エッチングガ
スの電子サイクロトロン共鳴プラズマ流により、前記導
電材料の選択エッチングを施す工程、 前記イ、ロの2種類の工程を同時に、または交互に施す
ことを特徴とする半導体装置の製造方法。[Claims] A method for manufacturing a semiconductor device in which a conductive material is selectively buried in a contact hole on a substrate, comprising: (a) depositing the conductive material on the substrate; (b) electron cyclotron resonance of an etching gas on the substrate; A step of performing selective etching of the conductive material by an electron cyclotron resonance plasma flow of the etching gas arranged obliquely with respect to the main axis of the plasma flow, and performing the two types of steps A and B above simultaneously or alternately. A method for manufacturing a semiconductor device, characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15815889A JPH0324724A (en) | 1989-06-22 | 1989-06-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15815889A JPH0324724A (en) | 1989-06-22 | 1989-06-22 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0324724A true JPH0324724A (en) | 1991-02-01 |
Family
ID=15665538
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15815889A Pending JPH0324724A (en) | 1989-06-22 | 1989-06-22 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0324724A (en) |
-
1989
- 1989-06-22 JP JP15815889A patent/JPH0324724A/en active Pending
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