JPH03246727A - Processor - Google Patents

Abstract

PURPOSE:To accelerate processing while suppressing the increment of hardware by comprising a device in such a way that an instruction is executed when an operand is not less than a prescribed value, but executing plural instructions in parallel when the operand is less than the prescribed value. CONSTITUTION:This processor is comprised of an instruction control part 10, an arithmetic control part 20, a universal register 30, a storage 40, an operand buffer 45, and selectors 50, 55, 80, etc. It is discriminated whether or not first and second arithmetic operations requested by first and second instructions are executed in parallel based on whether the length of first and second operands are less than the prescribed value or whether the first and second operands exceeds the prescribed value. Following that, the first and second arithmetic operations are executed in parallel on supplied first and second operands based on whether or not the first and second arithmetic operations are executed in parallel. In such a way, it is possible to accelerate the processing by parallel execution while suppressing the increment of the hardware.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a processing device that executes instructions sequentially or in parallel, and particularly to a processing device that executes a plurality of instructions in parallel using a vibline processing method (advance control method). The present invention relates to a processing device suitable for.

[Prior Art] There is a processing device described in Japanese Patent Application Laid-Open No. 176751/1983 as a device that aims to speed up processing by executing a plurality of instructions in parallel.

Further, the processing device described in Japanese Patent Application No. 1-194031 includes a plurality of arithmetic unit groups, a plurality of data paths that supply operands to these arithmetic unit groups, and a predetermined operand to a predetermined arithmetic unit. and a switching circuit for switching the data path for supplying the data.

[Problems to be Solved by the Invention] In the conventional processing device described above, a switching circuit switches between a plurality of data paths to supply operands to a predetermined group of arithmetic units.

However, as the degree of parallelism increases, the number of data paths and arithmetic units increases, the switching circuit becomes more complex, and the amount of hardware becomes enormous.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a processing device that can suppress an increase in the amount of hardware due to an increase in the degree of parallelism.

[Means for Solving the Problems] The processing device of the present invention includes (a) first. The first command requires each of the second commands. The lengths of the second operands are both smaller than the predetermined value, or the first . Depending on whether at least one of the second operands is greater than the predetermined value, the first .
The first command required by the second command. (b) operation determination means for determining whether or not to execute the second operation in parallel; Depending on whether or not the second operation is executed in parallel, the first... (c) operand supply means for supplying the second operand in parallel or sequentially; Depending on whether or not the second operation is executed in parallel, the first... A second operation is performed on the supplied first . (d) operation result storage means for storing the operation results executed in parallel or sequentially by the operation means for the second operand; This is a structural feature.

In the above configuration, it is preferable that the operand supply means supplies the operands smaller than a predetermined value in parallel using an operand supply circuit that sequentially supplies the operands to the calculation means.

Preferably, the calculation storage means stores the calculation results executed in parallel by the calculation means using a calculation result writing circuit for storing calculation results sequentially executed by the calculation means.

Further, the arithmetic means includes a first arithmetic unit group consisting of one or more arithmetic units that can perform operations on operands that are smaller than a predetermined value as well as operands that are not smaller than a predetermined value; a second arithmetic unit group consisting of one or more arithmetic units that can perform
The parallel execution is performed by the first arithmetic unit group and the second arithmetic unit group, and the sequential execution is performed by the first arithmetic unit group. Preferably, the computer has two or more arithmetic units capable of performing only the calculation of , the parallel execution is performed by each arithmetic unit, and the sequential execution is performed by connecting the arithmetic units in series.

[Operation] In the processing device of the present invention, instructions are executed sequentially when the operand is not smaller than a predetermined value, but a plurality of instructions are executed in parallel when the operand is smaller than the predetermined value.

Therefore, it is possible to increase the processing speed while suppressing the increase in hardware such as arithmetic units, operand supply circuits, and calculation result storage circuits.

[Examples] Examples of the present invention will be described below. Note that the present invention is not limited thereby.

FIG. 1 is a block diagram showing the overall configuration of an information processing device 1 according to an embodiment of the present invention.

Storage 40 holds instruction sequences and operands.

The instruction control unit 10 stores the instructions to be executed in the storage 40.
The decoding information is sequentially read out and decoded via the line 41A. The decoding information is then supplied to the arithmetic control section 20 via the line 12A.

The arithmetic control unit 20 temporarily holds the supplied decoding information. Based on the held decoding information, it controls the supply of operands to the arithmetic units 75 and 76 and the long word length arithmetic unit 70, and the execution of operations.

The general-purpose registers 30 are a group of registers that hold address modifiers and operands called base and index. The address qualifier is connected to the instruction control unit 1 via line 31A.
Sent to 0. Operands are sent to selectors 50.55 via lines 35A-35D.

Operand buffer 45 is connected to line 44 from storage 40.
Operands sent through A and 44B are temporarily held. Then, set the operand it is holding to line 45
It is sent to selector 50.55 via A to 45D.

Selectors 50 and 55 select either the operand sent from general-purpose register 30 or the operand sent from operand buffer 45, and select one of the operands sent from general-purpose register 30 and the operand sent from operand buffer 45, and
and 56B, input register 6 via lines 56C and 56D.
Send to 0.65.

Input registers 60.65 hold operands sent from selectors 50, 55, and are sent to long word length calculators 70.65 via lines 67A and 67B and lines 67G and 67D. Arithmetic unit 7
5 and 76.

The long word length calculator 70 performs an operation on a long word length operand (operand longer than a predetermined word length, for example, an 8-byte operand) held in the input register 60.65.

The arithmetic unit 75 performs an operation on short word length operands (operands shorter than a predetermined word length, for example, 4-byte operands) held in the first half of the input registers 60 and 65.

The arithmetic unit 76 performs arithmetic operations on the short word length operands held in the latter half of the input registers 60 and 65.

The selector 80 selects either the calculation result sent from the long word length calculator 70 or the calculation results sent from the calculation units 75 and 76, and outputs the result to the output register via lines 89A and 89B. Send to 90.

The output register 90 temporarily holds the calculation result sent from the selector 80. Then, the held calculation results are transferred to the storage 4 via lines 93A and 93B.
0 or to general purpose register 30.

FIG. 2 is an example of a command sequence stored in the storage 40 of the information processing device 1.

The instruction rL 2,100(8,12)J is obtained by using the contents of the 12th register in the general-purpose register 30 as a base, using the contents of the 8th register as an index, and adding the displacement value ``100'' ( The content held at the address (of the storage 40) is read out as the second operand (short word length), and the contents are stored in the general-purpose register 30.
This is an instruction to transfer data to the second register in the memory.

Instructions “AR4, 5J read the contents of the fourth register in the general-purpose register 30 as the first operand, read the contents of the fifth register as the second operand (short word length), add the two, and store the addition result in the general-purpose register. This is an instruction to write to the fourth register in 30.

The instruction rD 6,300(9,12)J is obtained by using the contents of the 12th register in the general-purpose register 30 as a base, using the contents of the 9th register as an index, and adding the displacement value '300'. The content held at the address (of storage 40) is read out as the second operand (short word length), and
An instruction to divide the first operand (long word length), which is a pair of the contents of the sixth register and the contents of the seventh register in 0, and write the remainder and quotient to the sixth and seventh registers in the general-purpose register 30, respectively. It is.

The instruction rST 3,400(10,12)J converts the contents of the third register in the general-purpose register 30 to the first operand (
(Short word length), the content of the 12th register in the general-purpose register 30 is used as the base, the content of the 10th register is used as the index, and stored at the address (in the storage 40) determined by adding the displacement value ``400''. This is an order to do so.

The instruction control unit 10 includes an instruction register that holds instructions read from the storage 40, an instruction decoder that decodes the instructions held in the instruction register and generates decoding information, and generates an address from the address part of the instruction. and an address generation circuit.

The decoding information generated by the instruction decoder includes the following information.

- OPE (operation type information): Specifies the type of operation to be executed in the long word length calculator 70 and the calculators 75 and 76.

- RRI (register number information): Specifies the register number in the general-purpose register 30 where the first operand is to be read and the operation result is to be written.

- RR2 (register number information): Specifies the register number in the general-purpose register 30 from which the second operand is to be read.

0B1 (entry number information): Specifies the entry in the operand buffer 45 from which the first operand is to be read.

- OH2 (entry number information): Specifies the entry in the operand buffer 45 from which the second operand is to be read.

(General-purpose register read specification information)...General-purpose register 3
Indicates that the first operand is read from the register in 0.

(General-purpose register read designation information)...Indicates that the second operand is to be read from a register in the general-purpose register 30.

(Storage read specification information): Indicates that the first operand is to be read from the specified address of the storage 40.

(Storage read specification information)...Storage 40
indicates that the second operand is to be read from the specified address.

- CHG (general-purpose register write designation information): Indicates that the calculation result is to be written to a register in the general-purpose register 30.

(Storage write specification information)...Storage 40
Indicates that the calculation result will be written to the specified address.

・NRI ・NR2 ・FE2 ・FEI ・STO ・STA (Write address information) Specifies the address of the storage 40 to which the calculation result is to be written.

LNG (Long word length calculation designation information): Indicates that the long word length calculation unit 70 should perform calculations.

The above decoding information 0PE-LNG is transmitted via line 12A,
It is sent to the calculation control unit 2o.

・FEA (read address specification information)...Storage 4 from which the first or second operand should be read
Specify address 0.

OBP (holding entry specification information): Specifies the entry in the operand buffer 45 that should hold the first or second operand read from the storage 40.

The above decoding information FEA and OBP are sent via the line 14A,
It is sent to the storage 40.

For example, upon decoding the instruction rL 2,100(8,12)J, the instruction control unit 10 sends the pace register number "12" and the index register number "8' to the general-purpose register 30 via the line 13A.

The general-purpose register 30 returns the specified contents of the twelfth register and the contents of the eighth register to the instruction control unit 10 via the line 31A.

The instruction control unit 10 adds the obtained base and index values and the displacement value '100' to generate an address. Then write that address to line 1
4A to the storage 40 to start reading the operand.

Further, when the decoding of one instruction is completed, the instruction control unit 10 transmits a decoding completion signal to the arithmetic control unit 20 via the line 12A.
Send to.

Next, FIG. 3 is a block diagram showing the internal configuration of the calculation control section 20. As shown in FIG.

As shown in FIG. 3A, the instruction queue 21 has a plurality of entries E1 to En, and temporarily holds decoding information sent from the instruction control unit 10 in one of the entries E1 to En. Then, the entries E1 to En are selected by the selectors Sl and S2, and the held decoding information is output. Each entry E1-En can hold a long word length operand.

Now, returning to FIG. 3, the in pointer 22 is incremented when it receives a decoding completion signal sent from the instruction control unit 10, and is incremented by an entry in the instruction queue 21 that holds the decoding information sent next. E1-En are indicated via line 221A.

The out pointer 23 connects the entries E1 to En of the instruction queue 21 holding the decoding information to be sent next to the long word length calculator 70 or the calculators 75 and 76 through the line 231A. Instruct selector S1.

The incrementer 24 increments the contents of the out pointer 23 and outputs a value. That is, the entries E1 to En of the instruction queue 21 holding the decoding information of the next instruction to be sent to the long word length calculator 70 or the calculators 75 and 76 are instructed to the selector S2 via the line 241A. do.

As a result, the decoding information of the next instruction to be computed in the long word length arithmetic unit 70 or the arithmetic units 75, 76 is output on the line 210A, and the decoding information of the next instruction to be computed next is output. will be output on line 210B.

In addition, in the following, when it is necessary to distinguish between the code related to the decoding information of the instruction whose operation is started next and the code related to the decoding information of the instruction whose operation is started next to the primary one, the former is replaced with a code. The latter is distinguished by adding P to the end of the code, and S to the end of the code to distinguish the latter.

The decoding information output on lines 21OA and 210B is distributed to each section shown in FIG. 1 via control lines 23A, 23B, . . . , 28A.

That is, the line 23A supplies the register number information RR1 and RR2 to the general-purpose register 30 for reading. The line 24A supplies the entry number information OBI and OB2 to the operand buffer 45.

The line 25A supplies the general register read designation information NRI or the storage read designation information FE1 to the selector 50. Line 25B supplies general register read designation information NR2 or storage read designation information FE2 to selector 51.

Lines 27A, 27B, and 27C indicate long word length calculator 70° calculator 75. The calculation type information OPE is supplied to the calculation unit 76. Line 28A sends long word length calculation designation information LNG to selector 80.

The line 23B sends the register number information RRI and general register write designation information CHG to the general register 30 for writing.

The line 24B provides write address information STA and storage write designation information STO to the storage 40.
Send out.

Registers 271, 272 and registers 281゜282
is a pipeline register for adjusting the timing of distributing the decoding information outputted to the lines 21OA and 210B to each section via the control lines 23A, 23B, . . . , 28A.

The decoding information on lines 21OA, 210B is sent to the instruction queue 21
A flag VLD is added to each entry E1 to En to indicate that it holds valid decoding information.

As shown in FIG. 4, the setup control circuit 25 outputs flags VLDP and VLDS and long word length calculation designation information LNGP from lines 21OA and 210B.

LNGS is input, and based on them, a hold signal 'Ho1d' or an increment signal '+1' is generated.
Or double increment signal “+2” to line 231.
It is output to the out pointer 25 via A.

That is, in FIG. 4, #1 is a state in which valid decoding information is not held in entries E1 to En, and the out pointer 23 is held at its current value.
A hold signal “Ho1d” is output. In #2, the entry holds the decoding information for the next instruction to start the operation, but the decoding information for the next instruction to start the next operation is not held in the entry yet. In order to select an entry for extracting the decoding information of the next instruction whose operation is to be started, an increment signal "+1" for incrementing the out pointer 23 is output. #3 is a state in which the decoding information of the next instruction to start an operation and the decoding information of the next instruction to start the next operation are both held in the entry, and the long word length operation specification information LNGP and LNGS
is 0, so instead of the long word length calculator 70, the calculator 7
5 and 76 can perform the operation. In other words, since the operations of two instructions can be executed in parallel, the out pointer 23 is incremented by two in order to select the entry for extracting the decoding information of the instruction whose operation will start next. Outputs signal "+2". #4~
#5 is a state in which the decoding information of the next instruction to start an operation and the decoding information of the next instruction to start the next operation are both held in the entry, and the long word length operation specification information LNG
Since at least one of P or LNGS is 1',
It is necessary to use the long word length calculator 70 to perform the calculation.

That is, selector 50.55 and input register 60.6
5, the selector 80, the output register 90, and the data path connected to these are occupied by only one long instruction, and two instructions cannot be executed in parallel.
In order to select an entry for extracting the decoding information of the instruction whose operation is to be started next, an increment signal "+1" is outputted to increment the out pointer 23.

The set-up inhibit circuit 26 connects lines 72A, 72B, 72
C, the long word length calculator 70. Arithmetic unit 75, arithmetic unit 7
The setup control circuit 25 monitors the states of the circuits 6 and 261A and indicates that one of them is in operation.
Report to.

Upon receiving this report, the setup control circuit 25
Incrementing the out pointer 23 is suppressed.

FIG. 5 shows the operation of general-purpose register 30.

When long word length calculation specification information■ and NGP are 0゛,
1135A and 35C, respectively, register number information R for reading the instruction to be started next.
The contents of the register specified by RIP and RR2P are output, and the contents of the register specified by register number information RRISRR2S for reading for the next instruction whose operation is to be started are sent to lines 35B and 35D, respectively. Output.

On the other hand, when the long word length calculation specification information LNGP is 1', the contents of the registers specified by the register number information RRIP and RR2P are output to the lines 35A and 35C, respectively, but the lines 35B and 35D, the contents of the register next to the register designated by the register number information RRIP and RR2P are output, respectively. in the end,
The contents of the long word length register pairs indicated by the register number information RRIP and RR2P are output to lines 35A and 35B, 35C and 35D, respectively.

FIG. 6 shows the operation of the operand buffer 45.

When the long word length operation specification information LNGP is 0°, the first half of the content of the entry specified by the entry number information 0BIP and 0B2P (short word long), and entry number information 0BIS, 0B2S for the next instruction whose operation is to be started is output on lines 45B and 45D, respectively.
Outputs the first half (short word length) of the entry specified by .

On the other hand, when the long word length calculation designation information LNGP is 1', entry number information 0BIP is provided on lines 35A and 35B1 and lines 35C and 35D, respectively.

Outputs the first and second half (long word length) of the contents of the entry specified by 0B2P.

FIG. 7 shows the operation of selectors 50 and 55.

When the long word length operation designation information LNGP is 0°, the general-purpose register read designation information NRIP.

By storage read specification information FEIP, line 35
The contents of A and 45A are selected and outputted to line 56A, and the contents of lines 35B and 45 are selected and outputted to line 56A.
The contents of B are selected and output on line 56B.

On the other hand, when the long word length calculation specification information LNGP is "1°," the lines 35A, 4
The contents of line 5A are selected and output to line 56A, and the contents of lines 35B and 45B are also selected and output to line 56B.

The same applies to the operation of the selector 55.

As described above, by the long word length calculation specification information LNGP,
General purpose register 30. Operand buffer 45. Controls the selectors 50 and 55, sets up the first operand necessary for the long word length arithmetic unit 70 or the arithmetic units 75, 76 to perform the operation in the input register 60, and sets the second operand in the input register 65. It can be raised.

FIG. 8 shows the contents set up in the input registers 60 and 65.

When the long word length operation designation information LNGP is 0°, the first and second operands of the instruction whose operation is to be started next are set up in the first half of the input registers 60.65, respectively, and the input registers 60. In the second half of step 65, the first and second operands of the next instruction whose operation is to be started are set up.

On the other hand, when the long word length operation specification information LNGP is "1°," the first and second operands of the long word length of the instruction whose operation is to be started next are set up in the entire input register 60.65. Ru.

As a result, when the long word length operation specification information LNGP is 0°, the short word length operation of the next instruction to be started is performed in the calculator 75 according to the operation type information 0PEP, and the next operation is started. It becomes possible to simultaneously perform operations on the short word length of the instructions in the arithmetic unit 76 according to the operation type information 0PES.

On the other hand, when the long word length operation designation information LNGP is 1°, it becomes possible for the arithmetic unit 70 to perform the long word length operation of the next instruction to be started in accordance with the operation type information 0PEP.

When the long word length calculation designation information LNGP is 0°, the selector 80 selects the calculation results of the calculation units 75 and 76 and outputs them to lines 89A and 89B.

On the other hand, when the long word length calculation designation information LNGP is °1, the calculation result of the long word length calculator 70 is selected and the lines 89A, 89
Output to 9B.

The output register 90 holds the above calculation result and sends it to the general-purpose register 30 or the storage 40.

Next, the operation of each part will be specifically explained using the instruction sequence shown in FIG.

The four instructions AR, D, and ST shown in FIG. 2 are retrieved from the storage 40 by the instruction control unit 10 and decoded.

The decoding information is sent to the arithmetic control unit 20 and held in each entry of the instruction queue 21.

The out pointer 23 points to the entry that holds the decoding information for the next instruction to start operation, and the incrementer 24 points to the entry that holds the decoding information for the next instruction A to start the operation next.
It indicates the entry that holds the decoding information of R.

As mentioned above, since all instructions other than the instruction are short word length instructions, the long word length operation designation information LNGP for the instruction is 0.

Therefore, the general-purpose register 30, as shown in FIG.
As the first operand of the instruction, register number information RR is
The contents of the second register specified by IP are sent out on line 35A. Further, as the first operand of the instruction AR, the contents of the fourth register designated by the register number information RRIS are sent to the line 35B. Furthermore, the second instruction AR
As an operand, the contents of the fifth register specified by register number information RR2S are sent to line 35D. Note that since the second operand of the instruction is not in general-purpose register 30, line 35C has no meaning.

As shown in FIG. 6, the operand buffer 45 stores the data of the entry specified by the read entry number information 0BIP on the line 45 as the second operand of the instruction.
Output to C. This data is data read from the address (in the storage 40) generated by the instruction control unit 10 from the address field for the second operand of the instruction and held. Note that the first operand of instruction A
Since the first operand of R and the second operand of instruction AR are not in the operand buffer 45, the line 45A.

45B and 45D have no meaning.

As shown in FIG. 7, the selector 50 selects the lines 35A and 35A according to the general register read designation information NRIP and NRIS.
35B is selected and output to lines 56A and 56B.

As shown in FIG. 7, the selector 55 selects lines 45C and 35D based on storage readout designation information FE2P and general-purpose register readout designation information NR25, and selects line 56C.
, 56D.

Therefore, as shown in FIG. 8, the first operand of the instruction is set up in the first half of the input register 60, and the first operand of the instruction AR is set up in the second half.

Further, the second operand of the instruction is set up in the first half of the input register 65, and the second operand of the instruction AR is set up in the second half.

The command is subjected to an operation in the arithmetic unit 75, and the instruction AR is subjected to an operation in the arithmetic unit 76.

Selector 80 selects lines 78C and 78D on which the calculation results of calculation units 75 and 76 are output, outputs the calculation results to lines 89A and 89B, and sets them up in output register 90.

The setup control circuit 25 operates according to #3 in FIG.
Increase the out pointer 23 by two.

As a result, the out pointer 23 points to the entry in the instruction queue 21 holding the decoding information for the instruction as the next instruction to start the operation, and the incrementer 24 points to the entry in the instruction queue 21 holding the decoding information for the next instruction. As the instruction to be executed, the entry that holds the decoding information of the instruction ST is designated.

When the instruction AR and the instruction AR are processed in parallel, the next process is started, and the long word length calculation designation information LNGP of the next instruction to be started is 1°.

Therefore, the general-purpose register 30, as shown in FIG.
As the first operand of the instruction, register number information RR is
The contents of the sixth register specified by IP and the contents of the next seventh register are sent to lines 35A and 35B. Note that since the second operand of the instruction is not in the general-purpose register 30, line 35C935D has no meaning.

As shown in FIG. 6, the operand buffer 45 outputs the data held in the entry designated by the read entry number information 0BIP to the pair of lines 45C and 45D as the second operand of the instruction. This data is data read from the address (in the storage 40) generated by the instruction control unit 10 from the address field for the second operand of the instruction and held. Note that since the first operand of the instruction is not in the operand buffer 45, lines 45A and 45B have no meaning.

As shown in FIG. 7, the selector 50 selects a pair of lines 35A and 35B based on general-purpose register read designation information NRIP and outputs the selected pair to lines 56A and 56B.

As shown in FIG. 7, the selector 55 selects the pair of lines 45C and 145D based on the storage read designation information FE2P and outputs the selected pair to lines 56C and 56D.

Therefore, as shown in FIG. 8, the first operand of the instruction is set up in the input register 60, and the second operand of the instruction is set up in the input register 65.

The command is operated on by a long word length calculator 70.

The selector 80 selects the lines 78A and 78B to which the calculation results of the long word length calculator 70 are output, outputs the calculation results to the lines 89A and 89B, and sets them up in the output register 90.

The setup control circuit 25 operates according to #5 in FIG.
Increment the out pointer 23 by one. As a result, the out pointer 23 again points to the entry in the instruction queue 21 holding the decoding information of the instruction ST as the instruction on which the next operation is to be started.

Thereafter, the instruction ST is executed in the same manner.

Next, FIG. 9 is a block diagram showing the overall configuration of another embodiment of the information processing apparatus of the present invention.

The information processing device 101 in FIG. 9 integrates the arithmetic unit 75 in the information processing device 1 in FIG. It is applied in a container 70. The selector 82 is
Long word length operation specification information LNG for the next instruction to start operation
When P is 0, select the line 78D on which the calculation result of the calculator 76 is output, and transfer the calculation result to the line 89.
Output to B.

On the other hand, when the long word length calculation specification information LNGP is "1', the line 78B to which the second half of the calculation result of the long word length calculation unit 70 is output is selected, and the second half of the calculation result is output to the line 89B.
Output to B.

Other operations are similar to the information processing device 1 shown in FIG.

This information processing device 101 has the advantage that the amount of hardware related to the arithmetic unit 75 can be reduced compared to the information processing device 1 of FIG.

Next, FIG. 10 is a block diagram showing the overall configuration of still another embodiment of the information processing apparatus of the present invention.

The information processing device 201 in FIG. 10 deletes the long word length calculator 70 in the information processing device 1 in FIG. 1, and performs long word length calculations by connecting two calculators 75 and 76. This is what I did.

In this information processing device 201, a line 27B supplying operation type information 0PEP is connected to two arithmetic units 75 and 76. Also, long word length calculation designation information LNGP is supplied at the same time.

When the long word length calculation designation information LNGP is 1°, the calculation unit 76 uses the calculation type information 0P supplied by the line 27B.
It executes the calculation indicated by EP, and outputs a signal necessary for calculation of upper digits such as carry to line 77A.

On the other hand, when the long word length calculation specification information LNGP is °O゛,
The calculation type information 0PES is obtained from the line 27C and the calculation is performed.

The arithmetic unit 75 always executes the arithmetic operation instructed by the arithmetic type information 0PEP obtained via the line 27B, but when the long word length operation designation information LNGP is "1 degree", the arithmetic unit 75 executes the arithmetic operation instructed by the operation type information 0PEP obtained via the line 27B. Calculations are performed by inputting a signal from the line 77A. When the long word length calculation designation information LNGP is °O°, a fixed value determined depending on the type of calculation is used as a signal such as a carry.

This information processing device 201 has the advantage that the amount of hardware related to the long word length calculator 70 and the selector 80 can be reduced compared to the information processing device 1 of FIG.

[Effects of the Invention] According to the processing device of the present invention, it is possible to realize faster processing through parallel execution while suppressing the increase in hardware such as arithmetic units, operand supply circuits, and calculation result storage circuits.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of an information processing device according to an embodiment of the present invention, FIG. 2 is a diagram illustrating an instruction sequence, FIG. 3 is a block diagram showing the internal configuration of an arithmetic control section, and FIG. 3A 4 is a block diagram showing the internal structure of the instruction queue, FIG. 4 is a chart showing the operation of the setup control circuit, FIG. 5 is a chart showing the operation of the general-purpose register, and FIG. 6 is a chart showing the operation of the operand buffer 45. FIG. 7 is a diagram showing the operation of the selectors 50 and 55, FIG. 8 is a diagram showing the setup contents of the input registers 60 and 65, and FIG. 9 is the overall configuration of an information processing device according to another embodiment of the present invention. FIG. 10 is a block diagram showing the overall configuration of an information processing apparatus according to still another embodiment of the present invention. (Explanation of symbols) 1.101, 201... Information processing device 10... Instruction control unit, 20... Arithmetic control unit, 30... General purpose register, 40... Storage, 45... Operand・Buffer, 50.55.82...Selector, 60.65...Input register, 70...Long word length arithmetic unit, 75.76...(Short word length) arithmetic unit, 90... Output register.

Claims (1)

[Claims] 1. (a) The first and second commands requesting each of the first and second commands.
Depending on whether the lengths of the second operands are both smaller than the predetermined value, or whether at least one of the first and second operands is larger than the predetermined value, the first , an operation determining means for determining whether or not to execute the second operation in parallel; (b) the first and second operations depending on whether or not to execute the first and second operations in parallel (c) operand supply means for supplying the operands of the supplied operands in parallel or sequentially; (d) operation result storage means for storing the operation results executed in parallel or sequentially by the operation means; A processing device having: 2. The processing device according to claim 1, wherein the operand supply means supplies the operands smaller than a predetermined value in parallel using an operand supply circuit when sequentially supplying the operands to the calculation means. 3. The processing device according to claim 1, wherein said calculation storage means stores calculation results executed in parallel by said calculation means using a calculation result writing circuit for storing calculation results sequentially executed by said calculation means. 4. The calculation means can perform calculations on operands that are smaller than a predetermined value and on operands that are not smaller.
a first arithmetic unit group consisting of the above arithmetic units; and a second arithmetic unit group consisting of one or more arithmetic units capable of performing only operations on operands smaller than a predetermined value; Execution is performed by the first arithmetic unit group and the second arithmetic unit group, respectively, and the sequential execution is performed by the first arithmetic unit group. 3 processing device. 5. The arithmetic means has two or more arithmetic units capable of performing only operations on operands smaller than a predetermined value, the parallel execution is performed in each arithmetic unit, and the sequential execution is performed by connecting the arithmetic units in series. 4. The information processing apparatus according to claim 1, 2 or 3, wherein the information processing apparatus is operated in a connected manner.