JPH0324654A - Memory protection circuit - Google Patents

Abstract

PURPOSE:To prevent the writing of error data into a memory by providing the memory protection circuit with a gate circuit for invalidating a chip select signal in the memory at the time of generating an error. CONSTITUTION:Addresses 3a, 3b, data 4a, 4b and a write signal 5 are respectively outputted from CPUs 1a, 1b. A comparator 7 is synchronized by a synchronism control circuit 2 to respectively compare the addresses 3a, 3b and the data 4a, 4b at a prescribed timing. When an error is generated as the result of comparison, an error signal 8 is generated, the gate circuit 13 is closed and a chip selection signal 12 is interrupted prior to the output of the write signal 5 to the memory 6 and outputted to the memory 6 as a chip selection signal 14.

Description

[Detailed Description of the Invention] [Field of Application of Santo] This invention provides a memory protection circuit that prevents erroneous data from being written to memory even when a temporary error occurs in the operation of IPσ. It is related to.

[Conventional technology]

Figure 3 is a diagram showing a conventional memory protection circuit (1a).
is the main system CP-U, (lb)Fi is the slave system CP [T,
<<2} is a synchronous control circuit that operates the OPU (1a) and CPU (1b) in clock synchronization. (3a) (
5b) is the address output from CPU (1a) (1tl), (4a) (4b) is OPσ (1 a)
Data output from (1 b). (5) is CPσ(1
A write signal to the memory is output from a), and (6) is a writable memory. C71 has addresses (3a) and (3
b) and the values of data (4a) and (4b) as the write signal 《
5) is a comparison circuit that compares at the timing of 71. (8) is a comparison circuit (an error signal indicating the result of 71. (9) is a failure detection circuit that detects the error signal (8). α● is an OFσ stop signal, am is Address decoder.a3 is a chip select signal for selecting one of the memories (t1).

FIG. 4 is a diagram showing the operation timing of the main signals in FIG. 3.

Next, the operation will be explained.

o P [T (1a) and c P U (1b) perform parallel processing in synchronization with a control signal such as a clock output from the synchronous control circuit <<2+.

O when data write processing to memory (6) occurs.
P U (1a) (1b) is. Address (3a) (3b) and data (4a) are sent at the timing shown in Figure 4, respectively.
) (4b), a write signal (5) and a chip select signal 0 are output.

Address (3a) and (lb) #Data (4a) and (4b
) are compared by the comparison circuit (71) in the time width T1 to see if they are the same value, and the result is output as an error signal (8) at the timings to and t1.The error signal (8) in Fig. 4 is When to, no error occurs, and when t1, the 0 error signal (8) indicating that an error occurs, indicates that there is no error, that is, when tO, data (4a) is stored in the memory (6) as a write signal ( 5), and the processing continues. When the error signal (8) indicates an error, that is, t1, the data (4a) is written to the memory (6) by the write signal (5), and the failure is detected at the same time. Circuit (9
)teeth. Generates an OPU stop signal. Synchronous control circuit《2
>> works better than immediately stopping OPσ(Ia) (1b).

[Problems that the invention helps solve]

Since the conventional memory protection circuit was configured as described above, the error signal (
8) When an error occurs, the processing of OPU (1a) (1b) is stopped by the CPU stop signal a, but the wrong data (4a) is already stored in the memory (6).
There was an issue where only one was written.

This invention was made to solve the above problems. The purpose is to be able to stop the processing of cpσ(ja) (1b) without writing incorrect data (4a) to memory (6) even if an error occurs in the main OPU (Ia). .

[Means to solve the problem]

The memory protection circuit according to the present invention is a main system cp? (1a
) and the slave system ■ P U (11)) are processed in parallel, and when data is written to the memory (6), the values of addresses (3a) and (3b) and data (4a) and (4b) from both systems are processed in parallel. A comparison circuit that compares +71 and . An address decoder determines which memory <<6>> is to be accessed based on address (5a), and a gate circuit inhibits generation of a chip select signal output from the address decoder. If in the comparison circuit cpσ(1a) and cpσ(1b)
If a mismatch is detected in the output information, the gate circuit prohibits the output of the chip select signal.

[Effect]

The memory protection circuit according to the present invention is c P [T (I
Even if an error occurs due to the configuration of a gate circuit that opens and closes the chip select signal to memory <<6>> generated based on the address (3a) output from a), the incorrect data (4a) will not be stored in the memory. (6) can be prevented from being written to.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In Fig. 1, a3 is a comparison circuit (71 to error signal {
8} is output, the gate circuit stops supplying the chip select signal az to the memory (6), and a4 is the chip select signal after being controlled by the gate circuit 0.

The memory to which the chip select signal α● finally corresponds (6
》

FIG. 2 shows a timing chart of the main signals.

Next, the operation will be explained.

Addresses (5a) and (3b) output from aPU (11!L) and OPU (1b)
4a) The operations of (4b) and write signal (5) are the same as in the conventional example.

In this invention, the comparison circuit (71 is the synchronous control circuit (2)
The addresses (3a) and (3b) and the data (4a
) and (4b).

In Fig. 2, the time to is an example where an error occurred due to the comparison and the results were successful.b. No error signal (8) is generated, and the chip select signal 0 is supplied to the memory <<6) as the chip select signal α♦ through the 11 gate circuit αj. t1
At point b, an error signal (8) is generated and the gate circuit a3-if is closed. Chip select signal a3 is write signal (5) and memory (6)
It is interrupted before being output to the chip select signal a4l.
It is output to the memory (6) as .

By the above method, even if opσ(1a) executes an incorrect process, writing of incorrect data (4a) to memory (6) can be prevented.

At the same time as the error signal (8) is generated, the failure detection circuit
91 operates, and the CP
The processing of U (1a) and (1b) is stopped.

In the above example, from ○Pσ (1a) to memory (6)
We have shown an example of writing data (4a) to
The same effect can be achieved even when applied to an external output circuit, etc., instead of writing to memory 《6》〇 [Effect of the invention] Based on the above. According to this invention. Write signal to memory (6)《At the stage before powder generation, (3P [I (1a) and O
The output information from Fσ (1b) is compared, and if an error occurs, the chip select signal (1
If an error occurs in opσ(1a) by configuring the gate circuit aS with
However, writing of incorrect data (4a) to memory {6} can be prevented.

[Brief explanation of drawings]

FIGS. 1 and 2 are diagrams showing an embodiment of the present invention,
Figures f$3 and 4 are diagrams showing conventional examples. (1a) (1b) is OPσ, (2) is synchronous control circuit,
(3a) (5b) are addresses, (4a) (4b
) is data, (5) is write signal, (6) is memo IJ,
i71 is a comparison circuit, +81Fi error signal, (9) is a failure detection circuit, α● is a CPU stop signal, αD is an address decoder, a'aaa is a chip select signal, aS
is a gate circuit. In the figures, the same reference numerals are the same or indicate the sum part.

Claims (1)

[Claims] Main CPU, slave CPU, synchronization control circuit that synchronizes the operation of the master and slave CPUs, comparison circuit that compares the addresses and data values output from the master and slave CPUs, the master CPU an address decoder that generates a chip select signal for the memory to be accessed based on the address of the address decoder;
It consists of a gate circuit that inhibits the output of the address decoder when an error occurs in the output of the comparison circuit, and a failure detection circuit that detects the error signal of the comparison circuit. If the value is output, this value is written to the memory, and if the value is not the same, the chip select signal to the memory is prohibited by the error signal of the comparison circuit, and writing of incorrect data to the memory can be prevented. A memory protection circuit featuring: