JPH03245790A - Motor controller - Google Patents

Abstract

PURPOSE:To minimize a control lag time, and to improve response by controlling a servo system having high reference frequency while being prior to a servo system having low reference frequency. CONSTITUTION:Frequency signals 3a, 3b corresponding to the rotational speed of motors 1a, 1b are detected by detecting means 2a, 2b, and the frequency difference of the rotational frequency and reference frequency of the corresponding motors 1a, 1b and phase difference are arithmetically operated by arithmetic means 60a, 60b by the frequency signals 3a, 3b. Supply power to the motors 1a, 1b is controlled by feed-controls 63a, 63b in response to the frequency difference and phase difference. When the frequency signal 3b to the motor 1b having a fast detecting period by the detecting means 2b is output from the detecting means 2b under the state in which supply power to the motos 1a is controlled by the feed control means 63a, control is changed over from the control of supply power to the motor 1a by the feed control means 63a to the control of supply power to the motor 1b by the feed control means 63b.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) This invention compares a reference frequency with the rotational frequency of a motor, and controls the phase of the motor so that it is synchronized with the reference frequency. , relates to a motor control device that controls rotation of a motor.

(Conventional technology) To keep the rotational speed stable despite fluctuations in load torque, power supply voltage, and ambient temperature, a crystal oscillator is used as a reference oscillator to create a stable reference frequency, and synchronization is performed to this reference frequency. In addition to phase control, frequency control is performed by comparing the rotational frequency of the motor with a reference frequency. Therefore, in order to obtain the phase difference and frequency difference between the rotational frequency of the motor and the reference frequency, calculate the power supplied to the motor in response to each, and control the rotation stably, Central Processing
Software servo control using υQit (CPU) is being considered.

In such a device, the frequency is detected as a rotational frequency signal of different frequencies detected from multiple motors.
Generator (FC) In a software servo control system that controls multiple motors by detecting the motor rotation speed in synchronization with the pulse and comparing it with a reference frequency using an interrupt processing program, it is usually a generator that responds to a certain frequency signal. Even if another frequency signal with a higher reference frequency occurs while interrupt processing is being executed, the CPU cannot execute the next interrupt processing until the currently executing interrupt processing is completed, so the FG multiplied signal with a higher reference frequency is generated. The software servo control system used has the disadvantage that the ratio of control delay time due to processing wait is large relative to the rotation speed sampling period, making it impossible to perform servo control with good responsiveness.

(Problems to be Solved by the Invention) The present invention eliminates the disadvantage that servo control with good response cannot be performed due to a large control delay time, and replaces a servo system with a high reference frequency with a servo system with a low reference frequency. It is an object of the present invention to provide a motor control device that can minimize control delay time and perform stable software servo control of a motor with good responsiveness.

[Structure of the Invention] (Means for Solving the Problems) A motor control device of the present invention controls the rotational speed of a first and second motor in synchronization with a plurality of reference frequencies. first and second detection means for detecting a frequency signal according to the rotational speed of the second motor;
First and second calculation means for calculating the frequency difference and phase difference between the rotational frequency of the corresponding motor and the reference frequency based on the frequency signals from these detection means; and the frequency difference and phase difference calculated by these calculation means. In a state where the power supplied to the first motor is controlled by the first and second power supply control means that control the power supplied to the corresponding motor according to the above, and the first power supply control means, When the frequency signal for the second motor whose detection cycle is fast by the second detection means is output from the second detection means, the first power supply control means controls the power supplied to the first motor. It is comprised of processing means for switching to control of the power supplied to the second motor by the second power supply control means.

The motor control device of the present invention controls the rotational speed of a motor in synchronization with a reference frequency, and includes a detection means for detecting a frequency signal corresponding to the rotational speed of the motor; A calculation means for calculating a frequency difference and a phase difference between the rotational frequency of the motor and a reference frequency, and a power supply control means for controlling power supplied to the motor according to the frequency difference and phase difference calculated by the calculation means. , and inhibiting means for inhibiting output of the frequency signal from the detecting means when the rotation of the motor is not controlled.

The motor control device of the present invention controls the rotational speed of a motor in synchronization with a reference frequency, and includes a detection means for detecting a frequency signal corresponding to the rotational speed of the motor; A calculation means for calculating a frequency difference and a phase difference between the rotational frequency of the motor and a reference frequency, and a power supply control means for controlling power supplied to the motor according to the frequency difference and phase difference calculated by the calculation means. , a detection means that detects an abnormality when the frequency signal from the detection means is not detected within a predetermined time; and a prohibition that prohibits the power supply control means from feeding power to the motor when the detection means detects an abnormality. It consists of means.

(Function) The present invention controls the rotational speeds of the first and second motors in synchronization with a plurality of reference frequencies, and provides a plurality of frequency signals corresponding to the rotational speeds of the first and second motors. is detected by the detection means, and based on the frequency signal from the detection means, the frequency difference and phase difference between the corresponding rotational frequency of the motor and the reference frequency are calculated by the first and second calculation means, and the calculation means According to the calculated frequency difference and phase difference, first and second power supply control means control the power supplied to the corresponding motor, and the first power supply control means supplies power to the first motor. is being controlled, and when a frequency signal for a second motor whose detection cycle is fast by the second detection means is output from the second detection means, the first power supply control means
The control of the power supplied to the second motor is switched from the control of the power supplied to the second motor to the control of the power supplied to the second motor by the second power supply control means.

In the present invention, in which the rotational speed of a motor is controlled in synchronization with a reference frequency, a frequency signal corresponding to the rotational speed of the motor is detected by a detection means, and the detected frequency signal is used to determine the rotational frequency of the motor. calculating a frequency difference and a phase difference from a reference frequency, and controlling power supplied to the motor according to the calculated frequency difference and phase difference;
The output of the frequency signal from the detection means is prohibited when the rotation of the motor is not controlled.

In the present invention, in which the rotational speed of a motor is controlled in synchronization with a reference frequency, a frequency signal corresponding to the rotational speed of the motor is detected by a detection means, and the detected frequency signal is used to determine the rotational frequency of the motor. The frequency difference and phase difference from the reference frequency are calculated, and the power supply control means controls the power supplied to the motor according to the calculated frequency difference and phase difference, so that the frequency signal from the detection means is An abnormality is detected when the abnormality is not detected within a predetermined time, and when the abnormality is detected, the power supply control means prohibits the power supply to the motor.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

In FIG. 1, 1a11b is a motor, and motor 1a
Frequency signals proportional to the rotational speed of s1b are respectively FG (Frequency Generator
) Circuit 2a.

2b. FG circuit 2 a
%2b is a frequency signal generated by shaping a signal generated by, for example, a tacho generator consisting of a detection coil or a magnetic sensor and a magnet, a shaft encoder consisting of a photointerrupter and a slit disk, etc.
It is output as G pulse 3a s 3b. The motors la and lb each have a motor control circuit 60
They are driven by drivers 63a and 63b under the control of drivers 63a and 60b. Motor control circuit 60a
160b outputs power supply signals 618161b corresponding to FG pulses 3g and 3b from FG circuits 2a and 2b to drivers 63a and 63b, thereby powering the motor l.
This is to stably control the rotation of a and lb.

For example, the motor 1a is 2. The rotation is controlled at 100 rpm, and after one rotation, the FC pulse 3a from the FC circuit 2a is
4 pulses are generated. Therefore, the frequency of the FG pulse 3a when the motor 1a is stably rotating at 2.1100 rpm is (2,100/Go)
X 24-840Hz. On the other hand, motor 1b has 8
．． The rotation is controlled by ioOrpm, and one rotation generates one FG pulse 3b from the FG circuit 2b. Therefore, the frequency of the FG pulse 3b when the motor 1b is stably rotating at 8,100 rpm is (8,100/60) X 1 = 135 Hz.

The motor control circuits 60a and 60b are connected to the CPU 41 via a data bus 40. This CPU 41 controls the entire system, and receives an interrupt request signal 62a1 supplied from the motor control circuit 60a or 60b.
Alternatively, in accordance with 62b, the interrupt processing program is branched during execution of the main program, and a counter value of a counter latch air, which will be described later, in the motor control circuit 60a5 or 60b is read in the interrupt processing program. The data bus 40 has RO
M42 and RAM43 are connected.

The ROM 42 stores control programs such as a main program and an interrupt program, and the CPU 41 operates according to these programs. R
AM43 is used as a work buffer for CPU41.

The motor control circuit 60a (60b) includes a D type flip-flop (FF circuit) 1, as shown in FIG.
0, 11.12, timer 13.22, synchronous circuit 14.2
3, data latch 24, oscillation circuit 15, counter 16,
It is composed of a counter latch 17, a D/A converter 18, an AND circuit 19, a boat 20, and an OR circuit 21. That is, the FG signal 3a from the FG circuit 2a is input to the data terminal of the FF circuit 10, and
The set output Q of the FF circuit 10 is input to the data terminal of the FF circuit 11 at the next stage.

A clock signal 15a from an oscillation circuit 15 is input to the clock terminal CK of the FF circuits 10 and 11, and each of them operates in synchronization with the clock signal 15a. The frequency of the oscillation signal from the oscillation circuit 15 is determined by a crystal oscillator (not shown), and the oscillation frequency is, for example, 55.050240 MHz.
is set to . This allows the reference period, i.e.
The period of the FG pulse 3a when the motor 1a is rotating at the target rotation speed is (8553B155.050240 x
to6)-1,190x 10-'(see).

Further, the clock signal 15a from the oscillation circuit 15 is output to the synchronization circuit 14.23.

The set output Q of the FF circuit 10 and the reset output Q of the FF circuit 11 are outputted by an OR circuit 21, as shown in FIG.
Output 1a.

Pulse 21a is a D type flip-flop (FF circuit)
The set output Q of the FF circuit 12 is input to the preset terminal PR of the FF circuit 12 as a trigger signal 12a to the timer 13.2.
2, and is output to the synchronization circuit 14. The timer signal 7 of the timer 13 is output to the clock terminal CK of the FF circuit 12. Here, the timer 13 outputs the timer signal 7 (0) for a predetermined period of time in synchronization with the rise of the trigger signal 12g, as shown in FIG. 3(a), and the timer 13 resets the signal 12a (0). It is something that performs an action.

The synchronization circuit 14 receives the clock signal 15 from the trigger signal 12a.
It generates a pulse signal 14a of a predetermined pulse width synchronized with a.

Further, the timer signal 22a of the timer 22 is output to the synchronization circuit 23. Here, the timer 22 is set as shown in FIG. 3(a).
As shown in , the timer signal 22a is output (0) for a predetermined period of time in synchronization with the rise of the trigger signal 12a, and the synchronization circuit 23
generates a pulse signal 23a having a predetermined pulse width synchronized with the clock signal 15a at the rising edge of the timer signal 22a.

The counter 16 is a 20-bit free running counter that operates using the clock signal 15a as a count clock. The counter value 16a of the counter 16 is latched by the counter latch 17 using the pulse signal 14a as a latch signal, and is read into the CPU 41 via the data bus 40.

The pulse signal 14g from the synchronization circuit 14 is transmitted to the boat 20.
AND circuit 19 along with interrupt control signal 20a from
The output of the AND circuit 19 is supplied to the CPU 41 as the interrupt request signal 62a. That is, when data is sent from the CPU 41 to the boat 20 and the interrupt control signal 20a is 0, the interrupt request signal 62a is always 0, so the CPU 41 does not perform interrupt processing.

On the other hand, when the interrupt control signal 20a is 1, the interrupt request signal 62a is equal to the pulse signal 14a, and in synchronization with the generation of the pulse signal 14a, the CPU 41 branches to the interrupt processing program during execution of the main program. The counter value of the power run clutch 17 is read in the interrupt processing program.

The data latch 24 is supplied with digital power supply data from the CPU 41 via the bus 40, which is calculated in interrupt processing to be described later, that is, calculated from the frequency difference and the phase difference. This data latch 24
The power supply data is the pulse signal 2 from the synchronization circuit 23.
3a, it is taken into the D/A converter 18. The D/A converter 18 converts the supplied digital power supply data into a voltage and outputs the voltage, and for example, an 8-bit D/A converter using an R-2R ladder-resistance network is used. The control voltage output of the D/A converter 18 is supplied as a power supply control signal 18a to the next stage driver 63a, and the driver 63a supplies electric power to the motor 1a according to the voltage value of the control voltage output.

The motor control circuit 60a (60b) is composed of a single semiconductor integrated circuit integrated into one chip. As a result, it can be easily integrated into a circuit using semiconductor integration technology such as a gate array, and costs can be sufficiently reduced.

In the above configuration, even if the rotational speed of the motor 1a increases extremely or the waveform of the FG pulse 3a breaks, the timer 13 remains in operation as shown in FIG. 3(b). 13 trigger signals 12a are not affected. Therefore, since the input of the FC pulse 3a with a cycle shorter than the timer time is prohibited by the action of the timer 13, the pulse signal 14a will not be generated with a cycle shorter than the timer time, and interrupt requests will occur frequently, causing the CPU 41 to prevent it from getting out of control. The timer time of the timer 13 is set to a value slightly smaller than the period of the FG pulse 3a generated when the motor 1a rotates at the target rotation speed. Also, the timer 13 is of a counter type that operates by counting the clock signal 15a, and the CPU 41
If the counter value can be set by , the timer time can be flexibly set according to the number of rotations of the motor 1a.

FIG. 4 is a time chart showing the relationship between the counter value 16a of the 20-bit free running counter 16, the pulse signal 14a1, and the data 17a latched in the counter latch 17. Counter 16 receives clock signal 1
5a is counted up from O to FFFFF, . . . When it reaches the terminal value FFFFFH, it returns to 0 again and continues the counting operation. Here, for example, when the motor 1a is started from a stopped state, an FC pulse 3a is generated by the FG circuit 2, and a pulse signal 14a is generated in synchronization with this. The pulse signal 14a increases in frequency in proportion to the increase in the rotational speed of the motor 1a, and this pulse signal 14a causes the counter value 16a of the counter 16 to change.
is latched as data 17a. Now motor 1a
The target rotation speed is set to the time T during which the counter 16 counts 1.00008. That is, the frequency of the clock signal 15a is now 55.050240MHz.
Therefore, the pulse signal 1 when the target rotation speed is reached is
The period of 4a is (6553B155.050240 x 106)-1
, 190X 10-' (see).

Therefore, each time the pulse signal 14a is generated, the counter value 16a is latched in the counter latch 17, and at the same time an interrupt request is generated to the CPU 41.
1 reads the data 17a in the interrupt processing program, reads the previous data stored in the RAM 43 in the previous interrupt processing, and calculates the difference between the two.
The period of the pulse signal 14a can be determined. That is, the rotation speed of the motor 1a can be determined.

Furthermore, by comparing the reference value 10000)1 with the period of the pulse signal 14a, it can be determined whether the rotation speed is overspeed or underspeed with respect to the target rotation speed.

When the motor 1a is stably rotating at the target rotation speed, the pulse signal 14a is generated 16 times while the counter 16 performs a counting operation from 0 to FFFFFH, for example. Now, the counter 16 is a 16-bit free running counter, and the target rotation speed of the motor 1a is set to the counter 16 or 10000)1.
When the time T for counting is set, as shown in FIG. 5, data D n-2 of data 17a and data D n-
1, the number of revolutions of the motor 1a can be determined in the same manner as above by determining the difference between the two.

However, in the case of data D n-1 and data Dn, it is unclear whether the difference between them is ΔD or ΔD-.

In other words, if at least one cycle in which the counter 16 counts 0 to 0FFFF)l occurs between two pieces of data 17a, it is impossible to accurately determine the rotation speed, and the motor If the rotation speed of motor 1a is slightly changing around the target rotation speed, or in the process of reaching the target rotation speed after motor 1a starts,
Such cases will occur frequently.

Therefore, the maximum count number of the counter 16 is the number of counts counted during a period corresponding to the target rotation speed (in this invention, it is necessary to provide at least twice the number of counts (10100O0), and if it is set even larger, the rotation from a lower speed It also becomes possible to perform accurate counting.In this invention, the maximum count number of the counter 16 is 0 to FFFFF,
Therefore, the count number 10000H for time T is 16
The number of revolutions is twice that of the target number of revolutions, so that the above-mentioned problems do not occur, and the number of revolutions can be determined accurately even when the number of revolutions is a fraction of the target number of revolutions.

Next, the phase difference will be explained. As shown in FIG. 6, when the time period during which the counter 16 counts 10000H (0 to 0FFFFH), that is, the period T, is the reference period of the pulse signal 14H, the reference clock CK can be assumed. For example, if we assume that the reference clock CK is a square wave with a duty of 50%, the counter 16 will be 8000H (1000H).
It is reversed every time half of OH is counted.

Therefore, by paying attention to the lower 16 bits of the counter 16, the reference clock CK can be virtually set. Therefore,
As shown in FIG. 7, by finding the difference ΔPn between the maximum value FFFF1l of the lower 16 bits of the counter 16 and the data 17b of the lower 16 bits of the counter latch 17 latched by the pulse signal 14a, It is possible to know the phase difference φn between the reference clock CK and the pulse signal 14a.

The amount of control to be applied to the motor 1a with respect to the period difference (frequency difference) and phase difference determined by the above method will be explained. Fig. 8 is a diagram showing the frequency control amount VF with respect to the period ΔFn. In the figure, -△f to △f represents the allowable period difference range (lock range), which is obtained by subtracting the period Dn from the reference period 10000H. The digital amount for the period difference △Fn is 8
It is given by bits (0 to FF) I).

For example, if Δf-mφFFH (m≧1 integer),
When the period ΔFn is in the range from −Δf to 0, the frequency control amount v2 is given by VP-7F, −ΔF n /2·m.

On the other hand, when the period ΔFn is in the range of 0 to Δf, the frequency control amount ■F is given by Vp=7Fn+ΔFn/2·m.

If the period △Fn does not fall within the lock range 1△f to △f, the frequency control amount vF is fixed to 0 when △Fn≦−△f, and the frequency control amount VP is set to the maximum value FFH when △Fn≧△f.
Fixed.

FIG. 9 shows the lower 16 bits of data Dn (
This is a diagram showing the phase control amount ■P for data Dn
The phase control amount ■P is given as a digital amount in 8 bits (0 to FFM) for 0 to FFFF)l of (L). Multiply the frequency control amount ■P obtained as above by the gain ratio GP to obtain the phase control amount VP.
is multiplied by the gain ratio cyp and added to each of them to obtain the control amount V
, ·G, +vP-GP are determined and output to the data latch 24.

Then, the voltage output proportional to this control amount is the pulse signal 2.
3a is latched by the D/A converter 18, and the D
The /A converter 18 supplies the power supply signal 61a to the driver 63a.

An example of the main program in the CPU 41 will be explained with reference to the flowchart shown in FIG. If the interrupt control signal 20a is now in the state of 0 and the -motor 1a is stopped, it is first checked whether or not control is to be started (step 530). Judgment to start control is as follows:
For example, this can be done by checking whether a motor start signal or command has been input from the outside.

When these are input, the D/A converter 1
8, starting data for starting the motor 1a is output (step 531), and at the same time, the motor 1a gradually starts rotating from the stopped state.

Next, the data is output to the boat 20, the interrupt control signal 20a is set to 1 (step 532), and the interrupt request signal 62a is generated while gradually increasing the frequency in synchronization with the increase in the rotational speed of the motor 1a. . Therefore, after the process of step S32 is completed, the interrupt processing program to be described later is executed in synchronization with the generation of the interrupt request signal 62a. Next, it is checked whether the control is to be stopped (step 833). The determination to stop the control can be made, for example, by checking whether a motor stop signal or command has been input from the outside.

When the motor 1a does not stop, it enters a standby state in step 833, and the motor 1a is controlled by the interrupt processing program to stably rotate. On the other hand, when stopping control, data is output to the boat 20 and the interrupt control signal 20 is output to the board 20.
a is set to 0 (step 534), and interrupt request signal 6
2a becomes 0. Therefore, after step S34 is executed, the interrupt processing program is no longer executed, and then stop data for stopping the motor 1a is output to the D/A converter 18 (step S53).
5) The driver 63a is turned off, and the motor 1a gradually slows down and stops. Then, the process returns to step S30 again and the same process is repeated. As described above, the interrupt request signal 62a is generated only when rotation control is performed.

Based on the above settings, Figure 11(a)(b)(c
) The interrupt processing program will be explained with reference to the flowchart shown in FIG. The interrupt processing program executes the main program (
(not shown). First, CPU4
The contents of the general-purpose register 1 are saved in the RAM 43 (step S1), the data Dn latched in the counter latch 17 is read (step S2), and then the
The data read in the previous interrupt processing stored in AM4B is read out as Dn-1 (step S
3).

Then, by determining the absolute value of the difference between data Dn and data Dn-1, the period of the pulse signal 14a is calculated as ΔDn (step S4). Furthermore, pulse signal 1
Period △Dn from 10000) 1, which is the reference period of 4a
The value △Fn obtained by subtracting is obtained as the period difference (step S5).
It is checked whether the period difference ΔFn is greater than or equal to 0 (
Step S6). When the cycle difference ΔFn is 0 or more, the process branches to step S7, and in step S7, it is determined whether the cycle difference ΔFn is smaller than the allowable cycle difference Δf, that is, whether it is within the lock range from 0 to Δf. You can check whether or not. When the period difference ΔFn is in the range of 0 to △f, the frequency control amount V is given by v, -7F, , + △F n / 2-m (step S8), and the period difference △Fn is allowed. When the period difference is greater than △f, that is, underspeed, the frequency control amount vF
is set to the maximum value FFH.

Further, in step S6, when the period difference ΔFn is smaller than 0, the process branches to step S10, and it is determined whether or not the absolute value 1ΔFnl of the period difference ΔFn is smaller than the allowable period difference Δf.
That is, it is checked whether the period difference ΔFn is within the lock range of 1 Δf to 0. Then, when 1△Fn1 is smaller than the allowable period difference △f (-△f × △Fn<O), the frequency control amount VF is v p = 7 F Hl△F n l
It is given by / 2 ・m. On the other hand, when 1ΔFnl is the allowable period difference of 61 or more (ΔFn<-Δf), that is,
At overspeed, the frequency control amount vp is fixed to 0. Then, the process proceeds to step 512, where FFFFHD
A phase difference ΔPn given by n(L) is calculated.

Next, in step 913, in order to set the relationship between the phase control it V p and the data Dn (L) as shown in FIG.
P-FFH-ΔPn/FF)l is calculated.

As described above, the frequency control ji v p and the phase control amount V are obtained, and the frequency control i v p is multiplied by the gain ratio GF, the phase control amount vP is multiplied by the gain ratio GP, and these are added for control. The amount Vo is calculated (step 516), and it is checked whether the controlled amount Vo exceeds the maximum value FF (step 517) Vo>F
When FH, the control amount vo is fixed at the maximum value FFH (step 618), and the control amount ■. is output to the D/A converter 18 (step 519).

Then, data Dn is stored in RAM for the next interrupt processing.
43 (Step 520), RA in Step S1
The contents of the register saved in M43 are returned to the register again (step 521), and the interrupt processing ends. After interrupt processing is completed, return to the main program.

Therefore, the maximum processing time required for the above interrupt processing program is that the instructions from steps 81 to S21 are
41 can be calculated in advance from the maximum instruction time to be executed by the timer 22. By setting a value larger than this maximum interrupt processing time as the timer value of the timer 22,
Regardless of variations in the processing time of repeatedly executed interrupt processing, the power supply data output to the data latch 23 in step S19 is always output to the D/A after a certain period of time has elapsed from the start of the interrupt processing by the pulse signal 23a. The signal is latched into the converter 18 and output.

In the above embodiment, the frequency control amount V P and the phase control amount V
Although P is programmed to be given linearly, it is also possible to set and use an arbitrary value in the data table depending on the characteristics of the control system. Further, the maximum value of the frequency control amount V4 and the phase control amount VP is the driver 63.
It can also be set according to the variable range of a.

The above describes software servo control that controls the rotational speed of the motor 1a to be synchronized with the reference frequency. On the other hand, the software servo control of the motor 1b is also similar to the software servo 2 control of the motor 1a, so a description thereof will be omitted. However, in the motor control circuit 60a of the motor 1a, the oscillation frequency of the oscillation circuit 15 is set to 55.050240 M)lz, and the reference period, that is, the FC when the motor 1a is rotating at the target rotation speed. The period of pulse 3a is (65536155,050240X 106) 1.1
90 x 1O-3 (see). On the other hand, motor 1
In the motor control circuit 60b of FIG. (85536 no 8.8473B x 106) -
7,407810-'(see).

In the above method, the motor 1a-motor control circuit 60g-"
In the software servo system A that controls the CPU 41 - motor control circuit 60a - motor 1a in a closed loop, and the software servo system B that controls the motor 1b -> motor control circuit 60b - CPU 41 - motor control circuit 60b - motor 1b in a closed loop. As shown in Figure 12, interrupt processing program I in servo system A
PI is branched from the main program MP and executed in response to an interrupt request signal 62a generated by the FG pulse 3a. Further, the interrupt processing program IP2 in the servo system B is branched from the main program MP and executed in response to the interrupt request signal 62b generated by the FG pulse 3b. Here, the interrupt request signal 62b
If another interrupt request signal 62g is generated while the interrupt processing program IP2 is being executed due to the occurrence of the interrupt processing program IP2, the execution of the interrupt processing program IP2 is interrupted as shown in A in the figure, and the interrupt processing for the interrupt request signal 62a is performed. The program IPI is executed with priority. After the execution of the interrupt processing program IPI is completed, the interrupted interrupt processing program IP2 is executed and terminated, and the processing is returned to the previous main program MP. Also, as shown in B in the figure, the interrupt processing program I
Even if an interrupt request signal 62b is generated during execution of PI, the interrupt processing program IP2 corresponding to the interrupt request signal 62b is not executed until execution of the interrupt processing program IP1 is completed. That is, software processing in servo system A is executed with priority over software processing in servo system B.

Therefore, within the interrupt processing program IP2, means are implemented to permit execution of the interrupt processing program IPI. Typically, this is done by using interrupt enable (EI).
A method may be used in which the instruction is executed or the interrupt processing program IPI is set as a non-maskable interrupt. On the other hand, other interrupts are not permitted within the interrupt processing program IPI.

As described above, priority is given to the processing of the servo system A whose reference frequency is higher than one of the reference frequencies, so the control from the generation of the FG pulse 3a to the output of the power supply control signal 61a to the motor 1a is The delay is only the time required for the interrupt processing program IPI, and this delay can be quantified. Therefore, by setting the gain ratios G, , G, etc. to appropriate values while taking this control delay into consideration,
Stable servo control with good responsiveness can be performed.

On the other hand, in servo system B, the interrupt time of servo system A, that is, the execution time of the interrupt processing program IPI, and its own interrupt processing program IP2
The maximum delay time is the sum of the execution time of Delays can be quantified.

As mentioned above, when an FG pulse that is another interrupt request occurs during a certain interrupt process, the FC pulse that occurs later than the reference frequency of the FC pulse that is the interrupt request of the currently executing interrupt process. When the reference frequency is high, priority is given to the interrupt processing currently being executed, and the interrupt processing for a later interrupt request is executed. In other words, in order to stably control the motor's rotational frequency at the reference frequency, which servo control system has a higher reference frequency?In other words, the closer the rotational frequency is to the reference frequency, and the higher the reference frequency, the shorter the sampling period. , it is possible to give priority to interrupt processing, reduce the ratio of control delay time to the sampling period, and improve responsiveness.

As a result, the servo system with a high reference frequency is controlled with priority over the servo system with a low reference frequency, which minimizes control delay time and provides stable software servo control of the motor with good responsiveness. It is designed so that it can be done.

In addition, only when controlling the rotation of the motor, an interrupt request signal is generated along with the FG pulse, and the interrupt processing is performed. Even if a pulse occurs, the output of the associated interrupt request signal is prohibited and no interrupt processing is performed, so malfunctions can be prevented, stable control can be performed, and reliability can be improved.

In addition, a timer is operated for a predetermined period of time in synchronization with the FG pulse, and at the end of the operation, the power supply data of the data latch is output to the D/A converter. In other words, the power supply is changed at a fixed time in synchronization with the FG pulse. Therefore, regardless of variations in interrupt processing time, power supply data can be output after a predetermined time has elapsed, and stable software servo control can be performed.

In addition, as another example, F according to the rotational speed of the motor
It is also possible to detect that the G-multiple signal does not occur within a predetermined time and stop the motor in response to this detection.

That is, as shown in FIG. 13, this can be implemented by adding a register 31 and a timer 32 to the motor control circuit shown in FIG. The register 31 is supplied with data for controlling the operation of the timer 32 from the CPU 41, and the output of the register 31 is supplied to the timer 32 as a trigger signal 31a. The timer 32 is supplied with the clock signal 15a from the oscillation circuit 15 and the pulse signal 14a from the synchronization circuit 14, and the output 32a of the timer 32 is C
It is output to PU41.

As a result, the timer 32 starts operating upon the rise of the trigger signal 31a, and the timer 32 is initialized every time the pulse signal 14a becomes high level. motor 1 normally
When a is rotating, the pulse signal 14a generates pulses at a constant period matching the rotation speed, and therefore the timer 3
2 repeats initialization and does not reach the predetermined time (Tel),
The timer signal always remains at high level.

Here, as shown in FIG. 14, if the FG signal 3a is not generated from the FG circuit 2a, the pulse signal 14a becomes low level, and the timer 32 outputs the timer signal 32a (0) after a predetermined time (Tel) has elapsed. Here, the timer signal 32a acts as an interrupt request for the CPU 41, and
While the PU 41 is running the main program, it branches to the interrupt processing program when an error is detected.
This is to detect abnormalities. Furthermore, the trigger signal 12a may be used as the signal for initializing the timer 32 instead of the pulse signal 14a. A time chart of each signal at this time is shown in FIG. When the motor is rotating normally, the signal 12a is output at a constant speed that matches the rotation speed, and the timer 32 repeats initialization. Here, if the FG signal 3a is not generated from the FG circuit 2a, the signal 12a becomes low level and the timer 32 outputs the timer signal 32 after a predetermined time (Te2) has elapsed.
It outputs (0) a, acts as an interrupt request for the CPU 41, and detects an abnormality in the motor 1a.

The interrupt processing program upon error detection is branched from the main program (not shown) or the interrupt processing program and executed if the pulse signal 14a is not generated within a certain predetermined time. FIG. 16 shows the flowchart of the interrupt processing program when this error is detected.

That is, first, the contents of the general-purpose register in the CPU 41 are
AM4 is evacuated into B (step 101), and motor 1
Step 102) to output stop data to the D/A converter 18 in order to stop the motor 1a, step 103) to turn off the motor operation flag, step 104 to turn on the motor error flag which means that the motor 1a is in an error state. ), the contents of the register saved in the RAM 43 in step S1 are returned to the register again (step 105), and the interrupt processing ends.

In this manner, in a device in which the rotational speed of the motor is controlled by software, abnormalities in the motor can be detected and safer and more stable control can be performed.

[Effects of the Invention] As explained above, according to the present invention, since the servo system with a higher reference frequency is controlled with priority over the servo system with a lower reference frequency, the control delay time can be minimized. It is possible to provide a motor control device that can perform stable software servo control of a motor with good responsiveness.

[Brief explanation of drawings]

1 to 12 show an embodiment of the present invention. FIG. 1 is a block diagram showing the overall configuration, FIG. 2 is a block diagram showing the configuration of the motor control circuit, and FIG. 3 is a block diagram showing each part. 4 to 7 are timing charts to explain the operation of the counter, FIG. 8 is a characteristic diagram of the frequency control amount, and FIG. 9 is a characteristic diagram of the phase control amount. , FIG. 10 is a flowchart for explaining main program processing, FIG. 11 is a flowchart for explaining interrupt processing, FIG. 12 is a timing chart for multiple interrupt processing, and FIGS. 13 to 16 are Fig. 13 is a block diagram showing the configuration of the motor control circuit, Fig. 14 and Fig. 1 show other embodiments.
FIG. 5 is a timing chart for explaining error detection, and FIG. 16 is a flow chart for explaining interrupt processing when an error is detected. la, lb--motor, 2a, 2b=-FG circuit (detection means), 3a, 3b=-FG pulse, 10.1
1.12...FF circuit, 10...Oscillation circuit (generating means), 12...Counter (counting means), 13.22.
32...Timer, 14.23...Synchronous circuit, 15.
...Oscillation circuit, 16...Counter ≠, 18...
D/A converter, 19...AND circuit, 20...
Port, 21... OR circuit, 24... Data latch, 31... Register, 40... Data bus, 41...
・CPU, 42-ROM, 43-RAM, 60a, 60
b--Motor control circuit, 61a, 61b--Power supply signal, 62a162b--Interrupt request signal, 63a,
63b... Driver, A, B... Software servo system, IPI, IF5... Interrupt processing program, MP... Main program.

Claims (3)

[Claims] (1) In a motor control device that controls the rotational speed of a first and second motor in synchronization with a plurality of reference frequencies, a first motor that detects a frequency signal corresponding to the rotational speed of the first and second motors. and a second detection means; first and second calculation means for calculating a frequency difference and a phase difference between the rotational frequency of the corresponding motor and a reference frequency based on the frequency signals from these detection means; first and second power supply control means that control the power supplied to the corresponding motors according to the frequency difference and phase difference calculated by the first and second power supply control means, and supply to the first motor by the first power supply control means; While controlling the power,
When the frequency signal for the second motor whose detection cycle is fast by the second detection means is output from the second detection means, the first power supply control means controls the power supplied to the first motor. A motor control device comprising: processing means for switching to control of the power supplied to the second motor by the second power supply control means. (2) In a motor control device that controls the rotational speed of a motor in synchronization with a reference frequency, there is provided a detection means for detecting a frequency signal corresponding to the rotational speed of the motor; a calculation means for calculating a frequency difference and a phase difference between the rotational frequency and a reference frequency; and a power supply control means for controlling power supplied to the motor according to the frequency difference and phase difference calculated by the calculation means. A motor control device comprising: a prohibiting means for prohibiting output of a frequency signal from the detecting means when the rotation of the motor is not controlled. (3) In a motor control device that controls the rotational speed of a motor in synchronization with a reference frequency, there is provided a detection means for detecting a frequency signal corresponding to the rotational speed of the motor; a calculation means for calculating a frequency difference and a phase difference between the rotational frequency and a reference frequency; and a power supply control means for controlling power supplied to the motor according to the frequency difference and phase difference calculated by the calculation means. , a detection means for detecting an abnormality when a frequency signal from the detection means is not detected within a predetermined time; and a prohibition for prohibiting the power supply control means from supplying power to the motor when the detection means detects an abnormality. A motor control device characterized by comprising means and.