JPH03243039A - Data order identifying circuit - Google Patents

Abstract

PURPOSE:To speed up the error detection of data order by verifying the propriety of order of received packets based upon information relating to the packet order read out from a data order storing means. CONSTITUTION:The order numbers of packets to be received are housed in a control memory part 221, and at the time of receiving a packet, a data order forming part 231 reads out the stored data and a data order checking part 241 checks whether the reception order of the packet is correct or not. Thereby, the propriety of the order of the reception packet can be immediately confirmed at the time of receiving the packet.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a data order identification circuit that identifies and verifies the order of transmitted and received packets in a communication system that transmits and receives data in the form of packets. The purpose of this is to detect the source address of a received packet based on the received packet, and the source address detection means detects information regarding the order of the received packets. A data order storage means stores data corresponding to a source address, and when a packet is received, reads out information regarding the order of the packet stored in the data order storage means corresponding to the source address of this packet, and and a data order verification means that verifies the validity of the order of the received packets based on the information regarding the order of the packets read from the data order storage means. do.

[Industrial application field]

The present invention relates to a data order identification circuit that identifies and verifies the order of transmitted and received packets in a communication system that transmits and receives data in the form of packets.

[Conventional technology]

Packet communication occupies a line only when sending and receiving packets, so it is a communication technology that allows efficient use of lines, and is widely used in fields where immediacy is not required. In this type of packet communication, one or more packets are created from predetermined data and sent and received between devices, and after receiving the packets, the receiving side identifies the order of the packets. It is necessary to identify data omissions and discrepancies.

Conventionally, when such data order identification is performed on the receiving side device, after the packet is captured, the upper protocol (for example, the protocol at the data link layer or higher in the open system interconnection (O3I) reference model) is used.
Alternatively, upper-level devices analyze information regarding the data order within a packet to monitor the validity of the data order. As a result, when a data dropout (packet dropout) is detected, the higher-level protocol or higher-level device issues a packet retransmission request to the data source.

[Problem to be solved by the invention]

By the way, in the conventional method described above, omissions and deviations in data sent and received in the form of packets are monitored by a higher-level protocol, so there is a problem in that it takes time to detect errors in the data order. In particular, when one communication device receives packets from n communication devices in parallel, the load required to monitor the data order cannot be ignored. There has been a desire for a method that can detect errors in data order in a short time.

The present invention was created in view of these points, and an object of the present invention is to provide a data order identification circuit that can detect errors in data order in a short time.

[Means to solve the problem]

FIG. 1 is a principle block diagram of a data order identification circuit according to the present invention.

In the figure, source address detection means 111 detects the source address of a received packet based on the received packet.

The data order storage means 121 stores information regarding the order of received packets in correspondence with the source address detected by the source address detection means 111.

When the data order reading means 131 receives a packet, it reads out the information regarding the order of the packet stored in the data order storage means 121 corresponding to the source address of this packet, and also reads the information regarding the order of this packet. Update.

The data order verification means 141 verifies the validity of the order of the received packets based on the information regarding the order of the packets read from the data order storage means 121.

Therefore, as a whole, information regarding the order of packets is stored in the data order storage means 121, and when a packet is received, the validity of the order is verified based on this stored information.

[For production]

Information regarding the order of received packets is stored in the data order storage means 121, and this information is read every time a packet is received, and updated when the read is completed. The data order verification means 141 verifies the order of received packets based on this read information, and detects an error in the data order when a packet different from the packet expected to be received is received. It has become.

In the present invention, by storing information regarding the order of received packets and updating this information each time a packet is received, the validity of the order of received packets is verified based on this information. This makes it possible to detect errors in data order in a short time.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of a communication system in an embodiment to which the data order identification circuit of the present invention is applied.

In the figure, 201, 203, 205, and 207 are communication control devices, 281, 283, 285, and 287 are terminal devices, and 291 is a transmission path, respectively.

The communication control devices 201 to 207 assemble packets and then send them to the transmission path 291.
It disassembles packets received via 1,
The reception order of packets is verified before disassembling the received packets.

The communication control devices 201 to 207 are connected in a ring shape by a transmission path 291, so that packets can be sent and received between any communication control devices.

FIG. 3 shows the configuration of the data order identification circuit in the communication control device 201 shown in FIG. 2. Note that the other communication control devices 203 to 207 have the same configuration, and the communication control device 211 will be explained as a representative.

In FIG. 3, 201 indicates a source address detection unit;
Reference numeral 21 indicates a management memory section, 231 a data order generation section, 241 a data order check section, 251 a source address identification section, 261 a control section, and 271 a connection section.

The source address detection means 111 shown in FIG.
is the data order generation means 231, the data order verification means 1
41 correspond to the data order checking section 241, respectively.

The connection unit 271 physically connects the communication control device 201 and the transmission path 291, and performs mutual conversion between an optical signal and an electrical signal when the communication medium of the transmission path 291 is light, for example. This connection section 271 is connected to the packet data bus within the communication control device 201, and the transmission path 291
Packets received via the packet data bus are sent out to this packet data bus.

The source address detection unit 211 detects the source address of a received packet, and performs detection by reading the source address stored at a predetermined position within the packet.

The management memory unit 221 includes the source address detection unit 211
The data sequence number and the identification result of the source address (to be described later) are stored in correspondence with the source address detected in . In the management memory unit 221, one storage area is allocated for one source address, and each area has a total of 8 bits, for example, a data sequence number of 7 bits and a source address identification result of 1 bit. Bit data is stored. When a new source address is detected by the source address detection unit 211, a new storage area of the management memory unit 221 is secured, and the data sequence number and all bits of the packet identification result are stored in this storage area. 0"
An initial value of ° is set.

The data order generation unit 231 reads out the data order numbers stored in the management memory unit 221 and updates the data order numbers that have been read out. When the first packet corresponding to each source address is received, the initial value "0" (all bits of the data order number are "0") is read from the management memory unit 221, and this value is read every time a packet is received thereafter. The values are updated as ``rl'', ``r2'', and so on.

The source address identification unit 251 identifies whether the received packet corresponds to a new source address or not, and the identification result is stored in the management memory unit 221. When the first packet corresponding to each source address is received, bit data "0" is read out from the management memory unit 221 as the packet identification result.

At this time, the source address identification unit 251 identifies the reception of a packet corresponding to the new source address, and updates the bit data “'0” stored in the management memory unit 221 to “1pa. When the original address identifying section 251 receives a packet, it sends a check instruction to the data order checking section 241.

The data order check unit 241 checks the validity of the order of received packets input via the packet data bus, and when a check instruction is input from the source address identification unit 251, the data order check unit 241 checks the validity of the order of received packets input via the packet data bus. The included data sequence number is compared with the data sequence number input from the data sequence generation unit 231 to perform a validity check. If an error in the data order is detected as a result of the validity check, an error signal is output. Each component operates in synchronization with various timing signals input from the control section 261.

After establishing frame synchronization based on the received packet, the control unit 261 sends a detection timing signal to the source address detection unit 211, a read/write timing signal to the management memory unit 221, and a data order generation unit 231.
and creation of a control timing signal for the source address identification unit 251.

It is used for input.

Next, the operation of the embodiment of the present invention described above will be explained.

Hereinafter, reference will be made to FIGS. 2 and 3.

When a packet is received from any of the communication control devices 203 to 207 via the connection unit 271 and this packet corresponds to a new source address, a new storage area of the management memory unit 221 is saved. is ensured, and
The initial values of the storage area (data sequence number "0" and packet identification result "0°') are read out.

The data order generation unit 231 generates this data order number “0”.
is sent to the data order check unit 241, and the packet order number when this sender sends the next data is "2" (the value obtained by adding 1 to the read value "1").
is written into the management memory section 221.

Further, the source address identification unit 251 determines that the source address is new according to the packet identification result “0”, and sends a logic “1” signal indicating a check instruction to the data order checking unit 241. At the same time, an identification result "1" indicating that this source address has been registered is written in the management memory section 221.

The data order check section 241 checks the data order number output from the data order generation section 231 and the packets on the packet data bus only when the logic of the check instruction output from the source address identification section 251 becomes "1". Compares the data order number in the data order number, and outputs an error signal only if there is a difference. This error signal is input, for example, to a higher-level device (not shown) that controls a higher-level protocol, and error recovery processing such as packet retransmission processing is performed.

Similarly, when packets corresponding to the same source address are received, the data order number in the management memory section 221 is read out and updated, and the data order check section 241 checks the validity of the packet order. is checked. In this case, the source address identification unit 251
In this case, a check instruction is sent to the data order checking section 241 without updating the identification result in the management memory section 221.

In this way, the order number of the next packet to be received is stored in the management memory section 221, and when a packet is received, the data order generation section 231 reads out this stored data, and the data order check section 241 reads out the stored data. Checks whether the order of reception is correct.

Therefore, when a packet is received, the validity of the order can be immediately confirmed, and the time required to detect an error in the data order can be shortened.

In particular, reading data from the management memory section 221,
Data comparison by the update and data order check unit 241 can be realized with simple hardware, and data order errors can be detected at the previous stage without putting a burden on the upper protocol, thereby improving communication efficiency. can.

In addition, since an area corresponding to the sender address is prepared in the management memory section 221 and data is read and updated, it is possible to support multiple senders, and even when the number of senders increases, the management memory Since it is only necessary to increase the capacity of the memory section 221, a versatile data order identification circuit can be realized, and it becomes possible to flexibly respond to the addition of lines, etc.

In addition, in the embodiment of the present invention described above, a communication system in which a plurality of communication control devices 201 to 207 are connected in a ring type is considered, but there is no particular limitation on the form of the network. Any format that sends and receives data will suffice.

[Effects of the Invention] As described above, according to the present invention, information regarding the order of received packets is stored, and this information is updated every time a packet is received, so that the received packets can be adjusted based on this information. This method is extremely useful in practical terms because it verifies the correctness of the order of data and can detect errors in the data order in a short time.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of a data order identification circuit of the present invention. FIG. 2 is a block diagram of a communication system in an embodiment of the invention. FIG. 3 is a block diagram of a data order identification circuit in an embodiment of the invention. It is. In the figure, 111 is a source address detection means, 121 is a data order storage means, 3 4 1 2 3 4 5 6 7 is a data order reading means, is a data order verification means, is a source address detection unit, and is a management memory , is a data order generation section, is a data order check section, is a source address identification section, is a control section, and is a connection section. +'y:"R447"ot7a Fig. 1 Isseonghyo-eup 13J (・, l'ilj 瑞fB:/I of the stem
^〜ωFigure 2

Claims (1)

[Claims] (1) Source address detection means (11
1); data order storage means (121) for storing information regarding the order of the received packets in correspondence with the source address detected by the source address detection means (111); data order reading means (131) for reading out information on the order of packets stored in the data order storage means (121) corresponding to the source address of the packets, and updating the information on the order of the packets; data order verification means (141) for verifying the validity of the packet order based on information regarding the packet order read from the data order storage means (121);
), and a data order identification circuit.