JPH03242093A - Data erasing device for memory card - Google Patents

Abstract

PURPOSE:To effectively use a memory area by preliminarily saving picture data which is not the erase object and erasing only picture data of the erase object with respect to two picture data stored in the memory area in the same block where data is erased with one block as a unit. CONSTITUTION:This device consists of a memory card 2, which has a picture memory 203 consisting of an EEPROM (electrically erasable memory) where the memory area can be erased with one block as a unit, and a picture data reproducing/erasing device 1 which can control erase of picture data stored in the memory card 2. At the time of erasing picture data stored in the picture memory 203, picture data which is not the erase object in blocks where picture data to be erased are stored is temporarily saved in a buffer memory 104, and picture data is erased with one block as a unit, and saved picture data is stored in original addresses again. Thus, picture data is stored independently of block units to effectively use the memory area.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a memory with a built-in solid-state memory used in a digital still image storage/reproduction device that mainly stores still images in a solid-state memory, such as a digital electronic still camera. Related to a card data erasing device.

[Conventional technology]

Conventionally, in digital electronic still cameras, solid-state imaging has been used to ensure portability and reliability, prevent deterioration in the quality of recorded images, and make stable, high-quality captured images instantly replayable on a regenerator. Image signals captured by the device are A/D converted, and the resulting digital image data is stored in a removable memory cart containing a rewritable semiconductor memory such as SRAM.

Furthermore, conventionally, a method of erasing data in a storage means has been proposed in which a memory area can be erased block by block. For example, Japanese Patent Application Laid-Open No. 1185078 discloses that it is possible to erase any image data stored in a memory cart by specifying an address, and to erase the remaining image data stored in the memory cart to create an empty memory area. A still video camera is shown that has been sequentially retracted.

In addition, Japanese Patent Application Laid-open No. 243686 (Hei)-243686 discloses that in an electronic camera that stores image data in a memory card such as an SRAM, when erasing variable length image data stored over multiple blocks, the image to be erased is Memory erasure that erases the image data by rewriting only the management data of the image data to be erased and storing new image data overlapping the memory area of the image data to be erased without erasing the data. A method is shown. That is, image data is stored in multiple blocks in a memory area divided into blocks of a certain capacity in a memory card, and the number of used blocks of the image data and the first block number or block name of the used blocks are also stored. Management data is stored in a predetermined memory area, and when image data to be deleted is specified, only the management data for that image data is deleted, and the image data is overlaid with new image data. It is designed to be erased by memorizing it.

Furthermore, Japanese Patent Application Laid-Open No. 1-165267 discloses a method in which, before storing image data after shooting in a memory card, the image data is first stored in a volatile memory, and the image data is displayed on a viewfinder so that the captured image can be confirmed. An electronic still camera is shown.

[Problem to be solved by the invention]

Conventionally, since the memory card does not have sufficient memory capacity, the digital image data is compressed and stored in order to effectively utilize the memory area.

On the other hand, in recent years, non-volatile flash EEPROMs (Nikkei Electronics, April 4, 1988 issue), which can realize relatively large-capacity memory chips and do not require a backup power source to retain data, have been introduced into the SRA.
It has been proposed to use it for memory cards instead of M etc.

By the way, it is known that while the above-mentioned flash EEPROM is capable of increasing the memory capacity, stored data can only be erased in units of devices or in units of several kilobytes. Therefore, depending on the compression ratio, the memory area of compressed digital image data may not be in erasable byte units. Therefore, when the rear part of one image data and the front part of the other image data of two photographed images stored adjacently are stored in the same block,
It becomes difficult to erase only one of the image data. On the other hand, if digital image data is always stored in erasable memory area units for convenience in erasing data, regardless of the number of data, the memory area cannot be used effectively.

Therefore, the EEPR, which can only be erased in blocks,
In memory means such as OM, there is a need for a data erasing method that erases stored data without impairing the effective use of the memory area.

The method for erasing image data of a still video camera disclosed in JP-A-1-185078 is effective for memory means that can erase image data in an arbitrary memory area by specifying an address; In the case of a memory means that can only be erased in blocks, the problem of data erasure cannot be solved, and it is difficult to erase image data in units of still images.

Furthermore, the data erasing method disclosed in Japanese Patent Application Laid-open No. 1-243686 erases only the management data when erasing data;
In flash EEP, image data that should be erased is not erased, and new image data cannot be stored at the same address until the image data is erased.
This data erasing method is difficult to apply to memory cards using ROM. Therefore, even with this data erasing method, the problem of data erasing described above cannot be solved, but it becomes difficult to erase image data in units of still images.

Furthermore, the electronic still camera disclosed in Japanese Patent Application Laid-Open No. 1-165267 monitors the images taken by the photographer and records only the images he/she wishes to record on the memory card, and does not use the already recorded image data. It is not intended to erase the data to make effective use of the memory area.

The present invention has been made in view of the above-mentioned problems, and for two pieces of image data stored in the memory area of the same block whose data is erased in block units, by saving in advance the image data that is not to be erased. It is an object of the present invention to provide a data erasing device for a memory card that erases only image data to be erased.

[Means to solve the problem]

In order to solve the above problems, the present invention includes a first memory means for storing digital image data whose memory area can be erased in blocks, and a second memory means for storing a storage address of the digital image data. In a memory card data erasing device for erasing digital image data stored in a removable memory card, erasure instruction means for instructing digital image data to be erased;
a buffer memory for temporarily storing digital image data; a block detecting means for detecting a memory block in which digital image data is stored from a specified storage address of the digital image data to be erased; data extraction means for extracting digital image data other than the digital image data to be erased stored in the buffer memory; and data extraction means for transferring the extracted digital image data to the buffer memory and erasing the digital image data in the detected block. After that, the data is stored again in the original address area.

Note that the buffer memory may also serve as a buffer memory for reproducing digital image data and outputting signals. Further, when an independent buffer memory is provided, the buffer memory may be provided on the memory card side, and its memory capacity is the same as the memory capacity in erasable block units of the first memory means. It's a good idea to leave it there.

[Effect]

In the memory card data erasing device configured as described above, when digital image data to be erased is specified, a block in the memory area stored in the digital image data is detected from the storage address, and further detected. Digital image data that is not to be erased within the block that has been erased is extracted. Then, the extracted image data is temporarily saved in a buffer memory, and after the data in the detection block is erased, the image data saved in the buffer memory is stored again at the original address.

In a case where the buffer memory for image data reproduction processing and signal output is also used as a backup buffer memory, in the image data erasing operation, digital image data that is not subject to erasing is transferred to the camera body, and the digital image data that is not to be erased is transferred to the camera body. Once the data has been erased, it is transferred to the memory card again and stored at the original address.

Furthermore, if a buffer memory with the same capacity as the erasable block memory capacity is set independently, the memory capacity becomes the minimum memory capacity required to save the digital image data that is not subject to erasing, and the buffer memory Enables downsizing.

Further, in the case where the buffer memory is provided on the memory card side, the digital image data not to be erased can be quickly transferred to the buffer memory and re-stored from the buffer memory.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS A memory card data erasing device according to the present invention will be described below with reference to the drawings.

FIG. 1 is a system configuration diagram of an embodiment of a data erasing device for a memory card installed in a digital still video camera or the like. The memory card data erasing device shown in the figure is an EEFR that can erase memory areas in blocks.
It is composed of a memory cart 2 having an OM (electrically erasable memory) and an image data reproducing/erasing device 1 capable of controlling erasing of image data stored in the memory card 2.

The image data reproducing/erasing device ff1l includes a system controller 101 (hereinafter referred to as CPU10I), an address generator 102, a timing generator 103,
It is composed of a buffer memory 104, a D/A converter 105, a low-pass filter 106, a digital signal processing section 107, and pass line changeover switches 108 and 109. The CPU 10] controls a reproduction operation of reading image data from the memory card 2 during reproduction and generating an image signal for reproduction from the image data, and an operation of erasing image data in the memory card 2.

The address generator 102 also provides management data such as the start address and end address of the memory area of the image memory 202 and the block number of the memory in order to store the image data in the memory card 2 and read it from the memory card 2. It is something that generates. These start address, end address, and memory block number are set in the address generator 102 by the CPU 10I during recording or playback. Further, the timing generator 103 generates a predetermined clock for timing each processing operation of the address generator 102, buffer memory 104, D/A converter 105, digital signal processing section 107, memory controller 201, etc. The buffer 7 memory 104 is a memory that temporarily stores image data read from the memory card 2 and image data for reproduction after digital signal processing, which will be described later. In addition, the D/
The A converter 105 is a signal converter that converts the reproduction image data (digital signal) output from the buffer memory 104 into an analog signal, and the low-pass filter 106 converts the image data converted into analog from the D/A converter 105 into an analog signal. This is a filter for limiting the frequency band of data (video signal). Further, the digital signal processing section 107 decompresses the compressed image data read from the memory card 2 using the decompression circuit 107a and restores it to the original image data.
7b is a circuit block that performs NTSC encoding processing for TV display and generates a digital video signal for playback. Further, the pass line changeover switch 108 is a changeover switch for selectively connecting the memory controller 201 to either the CPUl0I or the address generator 102 connected via an address bus line, and the passline changeover switch 109 connects the memory controller 201 to the data This is a changeover switch that connects either the CPU 10I or the buffer memory 104 connected via the bus line.

Further, switches SW1 and SW2 are a reproduction forward switch and an erase switch, respectively, and are arranged on an operation panel (not shown) of the camera body. Playback forward switch SWI
is a switch for changing the still image to be played back to another still image that you want to play back, and when this switch SWI is turned on, the still images recorded in the image memory 203 are sequentially updated as described later. is played. switch SW2
is a switch for instructing erasure of image data in the image memory 203.

The memory card 2 includes a memory controller 201, a management memory 202 that stores management data, and an image memory 203 that stores image data. The memory controller 201 is a controller that controls writing, erasing, and continuing the management data to the management memory 202 and writing, erasing, and continuing the image data to the image memory 203. The management memory 202 is a memory that stores management data such as block numbers, start addresses, and end addresses of memory areas storing image data.
The image memory 203 is an EEPRO that stores image data.
This is a memory consisting of M. The memory area of this image memory 203 is composed of N erasable blocks.

As shown in FIG. 2, image data is stored in order from the top address, regardless of erasable blocks. In the same figure, blocks O to 10 are image memory 203
is an erasable memory area corresponding to the memory area of
Image memory 203 consists of ten erasable memory areas. Further, image data A to D are image data of still images stored in a memory area of the image memory 203, and 203a is an empty memory area. Since the data compression rate differs depending on the image data, the data capacity of each image data differs. Furthermore, since the data capacity of each image data is usually not an integral multiple of the block's memory capacity, parts of each of the two image data are stored in the same block as shown in Figure 2. Become. For example, image data A is transferred from the first block to the third block,
Image data B is stored from the third block to the fifth block, and the rear part of image data A and the front part of image data B coexist in the memory area of the third block. .

Next, the operation of the data erasing device will be explained.

First, a case in which image data stored in the memory card 2 is reproduced will be described.

When the playback switch SWI is turned on by the user,
CPUI O1 is a pass line changeover switch 108 and 1
After switching the CPU 09 to the CPU 01 side, the management data regarding the image data to be reproduced should be read out (the management data in the management memory 202 is accessed via the memory controller 201).

Then, the management data such as the read block number, start address, and end address are set in the address generator 102. Next, the CPU 101 switches the pass line changeover switches 108 and 109 to the address generator 102 side and the buffer memory 104 side, respectively, and then sends a data transfer start signal to the timing generator 103. timing generator 103
receives this data transfer start signal and sends predetermined clocks for data transfer to the address generator 102, buffer memory 104, and memory controller 201, respectively. Next, the CPU 01 sends a control signal for successive image data to the memory controller 201, and the memory controller 201 receives this control signal and inputs the block number and addresses from the start address to the end address input from the address generator 102. Based on this, predetermined image data is read out and transferred to the buffer 7 memory 104. When the end address is output and reading of the image data to be reproduced is completed, a data transfer end signal is output from the address generator 102 to the timing generator 103, and the timing generator 103
01 is stopped, and the transfer of the image data from the memory controller 201 to the buffer memory 104 is stopped.

Next, the timing generator 103 sends a transfer clock, a control clock, and a processing clock to the address generator 102, digital signal processing section 107, and buffer memory 104, respectively. The address generator 102 sends the transfer address to the buffer memory 104 based on the transfer clock, and the buffer memory 104 sends the temporarily stored image data based on the transfer address and the control clock. The data is transferred to the decompression circuit 107a in the digital signal processing section 107. The compressed image data is subjected to predetermined decompression processing in the decompression circuit 107a based on the processing clock, and then
NTSC for TV display with TSC encoder circuit 107b
After the encoding process is performed, the buffer memory 10
4 and stored in a predetermined memory area. When the processing of image data for one screen is completed and a signal processing end signal is sent from the digital signal processing unit 107 to the timing generator 103, the timing generator 10
3 receives the end signal and outputs the address generator 102.
, buffer memory 104 and D/A converter 105
transfer clock, control clock and D/' respectively.
Sends the A conversion clock. Buffer memory 104
The image data stored in the D/'A converter 105 is transferred to the D/'A converter 105 based on the transfer address and control clock input from the address generator 102.
After being subjected to D/'A conversion by an A converter 105, the signal is output as a band-limited video signal to a display device (not shown) by a low-pass filter 106.

The above operation is repeated every time the playback switch SWI is turned on, and the video signals are sequentially played back and displayed.

Next, a data erasing operation of the memory card 2 according to the present invention will be explained.

The data erasing operation when erasing the image data B in FIG. 2 will be described below.

The data erasing operation is performed as follows.

First, as shown in FIG. 3, among the blocks of the image memory 203, the blocks (third to
The fifth block) is extracted, and this block is set as the block to be erased. Next, as shown in FIGS. 3 and 4, the rear part A3 of the image data A stored in the third block is temporarily saved in the buffer memory 104, and the image data of the third and fourth blocks are saved. After erasing, the image data A3 is stored again in the original address area of the third block.

Next, the front part C5 of the image data C stored in the fifth block is temporarily saved in the buffer memory 104, and after erasing the image data of the fifth block, the image data C5 is saved again in the fifth block. Restore to the original address area.

FIG. 5 shows the storage state of the image data in the image memory 203 after the image data B has been erased by the method described above. As shown in the figure, only the memory area where image data B of the image memory 203 was stored is erased and becomes an empty memory area, and the memory areas of other image data A, C, and D are not affected by the data erasing operation. I won't receive it.

Note that in the data erasing operation described above, the image data may be rewritten so that image data C and D are stored consecutively after image data A.

In this way, the empty memory area created by erasing image data B can be collected at the rear of the image memory 203, and compressed variable-length image data can be stored efficiently and in the order in which they were written. .

Next, the above data erasing operation will be explained using the system configuration diagram shown in FIG.

When image data B is being played back, the image data B
When the erase switch SW2 is turned on to erase the CP
UI O1 is the pass line changeover switch 108 and 109
is switched to the CPU10I side, the block number in the image memory 203 used by the currently reproduced image data B is checked in the contents of the management memory 202, and the block number is set as the data erase block. Next, block numbers used by image data A and C stored before and after image data B are checked, and block numbers that overlap with image data B are extracted. In Figure 2, the block numbers used by image data A, B, and C, and among these block numbers,
The block numbers that overlap with the block numbers used by image data B are as follows.

Image data A: 0th to 3rd blocks Image data B: 3rd to 5th blocks Image data C, 5th to 7th blocks Overlapping blocks, 3rd and 5th blocks Subsequently, the CPU 101 starts the third block. The address and the end address of the image data A in the third block are extracted, and the start address and end address are set in the address generator 102. Next, the CPU 10I switches the pass line changeover switches 108 and 109 to the address generator 102 side and the buffer memory 104 side, respectively.
After switching to side 7, a data transfer start signal is sent to timing generator 103. Timing generator 103 receives this data transfer start signal and sends an address and clock for data transfer to address generator 102, buffer memory 104, and memory controller 201, respectively. Subsequently, the CPU 101 sends an image data read control signal to the memory controller 201, and upon receiving this control signal, the memory controller 201 reads the block number (third block), the start address, and the end address input from the address generator 102. Based on the address, the rear part A3 of the image data A in the third block is read out, and the rear part image data A3 is transferred to the memory area in the buffer memory 104 used during the reproduction. Then, the end address data is transferred from the address generator 102 to the timing generator 1.
When the data transfer end signal is input to 03, the timing generator 103 stops sending the clock for data transfer to the memory controller 201, and transfers the rear image data A3 from the memory controller 201 to the buffer memory 104. to stop. Next, CPU1
01 sends an instruction signal to erase the data of the third and fourth blocks to the memory controller 201, and the memory controller 201 receives the erase signal and erases the image data of the third and fourth blocks in the image memory 203. .

After that, the CPU 101 sets the start address of the third block and the end address of the rear image data A3 in the address generator 102, sends a data transfer start signal to the timing generator 103, and sends a write control signal to the memory controller 2018. Send out. The memory controller 201 receives the write control signal and writes the rear image data A3 transferred from the buffer memory 104.
is again stored in the third block in the image memory 203.

The front part C5 of the image data C stored in the fifth block is also stored at the original address of the fifth block by the same operation as the rear part image data A3.

That is, the front image data C5 is once transferred from the fifth block to the buffer memory 104, and after the image data in the fifth block is erased, it is stored again at the original address in the fifth block. Here, image data A3. C
5 are transferred separately and the same operation is repeated twice, but image data A3. Evacuate C5 at the same time, and
After erasing the fifth block, image data A3. C5 may also be stored at the original address at the same time.

Note that in the data erasing operation described above, image data CD may be re-stored so that an empty memory area is not created by erasing image data B. In this case, the front image data C saved in the buffer memory
5, after the image data in the 5th block is erased, it is stored from the address next to the end address of the image data A in the 3rd block, and then stored from the 6th block to the 10th block. The rear part of the image data C and the image data D are successively re-stored in the front part image data C5. Alternatively, when storing the next image data in the empty memory area, if the amount of image data is larger than the memory area, the image data may be divided and stored in another empty memory area. good. In this case, the management memory 202 stores the start address, end address, block number, etc. of each divided image data. By doing this, it is not necessary to fill in and re-storage the subsequent image data every time image data is deleted.

Note that the present invention is not limited to EEPROM, and may be applied to other solid-state memories as long as they can be erased in blocks for convenience of erasing.

Further, in the above embodiment, the buffer memory 104 for image data reproduction processing and signal output is also used as a buffer memory for saving image data that is not to be erased, but an independent buffer memory for saving is provided. It's okay. In this case, the memory capacity of this save buffer memory is preferably the same as the memory capacity of the erasable block. Further, a buffer memory for saving may be provided in the memory card 2. In this way, it contributes to the miniaturization of the camera body side, and
Transfer processing of save image data can be performed quickly.

〔Effect of the invention〕

As explained above, according to the present invention, when erasing image data stored in a memory means that can erase a memory area on a block-by-block basis, erasing targets within a block in which image data to be erased are stored. After saving the external image data to the buffer memory and erasing the image data in block units, the saved image data is stored again in the original address area, so that the image data cannot be related to the block unit. Therefore, the memory area can be used effectively.

Furthermore, since the buffer memory for image data reproduction processing is also used as the save buffer memory, it is possible to simplify the circuit configuration and reduce costs.

Further, since the save buffer memory is provided on the memory card side, the increase in the number of memory circuits in the data erasing device can be suppressed, and the transfer process of save image data can be performed quickly.

Further, since the memory capacity of the save buffer memory is made equal to the memory capacity of the erasable block, the data erasing device according to the present invention can be realized by relatively simple circuit changes.

[Brief explanation of drawings]

Fig. 1 is a system configuration diagram of a memory card data erasing device according to the present invention, Fig. 2 is a diagram showing the storage state of image data in the image memory in the memory card, and Figs. 3 to 5 are data erasing diagrams. FIG. 3 is a diagram showing reading, writing, and erasing operations of image data in an image memory for explaining operations. DESCRIPTION OF SYMBOLS 1... Image data reproducing/erasing device, 2... Memory card, 101... CPU, 102... Address generator, 103... Timing generator, 10
4... Buffer memory, 105... D/A converter, 106... Low pass filter, 107... Digital signal processing circuit, 1.07 a... Expansion circuit, 1
07b...NTSC encoder circuit, 108, 109
...Pass line changeover switch, 201...Memory controller, 202...Management memory, 203...Image memory, SWI, SW2...Switch.

Claims (1)

[Scope of Claims] 1. A removable device having a first memory means for storing digital image data whose memory area can be erased in blocks, and a second memory means for storing a storage address of the digital image data. A memory card data erasing device for erasing digital image data stored in a memory card includes an erasing instruction means for instructing digital image data to be erased, a buffer memory for temporarily storing the digital image data, and a buffer memory for temporarily storing the digital image data. block detection means for detecting a memory block storing digital image data to be erased from a storage address of the digital image data; and digital image data other than the digital image data to be erased stored in the detected block. a data extraction means for extracting the data; and after transferring the extracted digital image data to the buffer memory and erasing the digital image data in the detected block,
A data erasing device for a memory card, comprising erasing control means for re-memorizing data in the original address area. 2. The memory card data erasing device according to claim 1, wherein the buffer memory is a buffer memory for reproducing digital image data and outputting a signal. 3. A memory card data erasing device, characterized in that the buffer memory of the memory card data erasing device according to claim 1 is provided within the memory card. 4. The memory card data erasing device according to any one of claims 1 to 3, wherein the buffer memory has the same memory capacity in blocks as the first memory means. .