JPH0324091B2 - - Google Patents
Info
- Publication number
- JPH0324091B2 JPH0324091B2 JP56145374A JP14537481A JPH0324091B2 JP H0324091 B2 JPH0324091 B2 JP H0324091B2 JP 56145374 A JP56145374 A JP 56145374A JP 14537481 A JP14537481 A JP 14537481A JP H0324091 B2 JPH0324091 B2 JP H0324091B2
- Authority
- JP
- Japan
- Prior art keywords
- clock pulse
- voltage
- rectifier
- terminals
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000003990 capacitor Substances 0.000 claims description 3
- 238000009499 grossing Methods 0.000 claims description 3
- 230000001360 synchronised effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000000470 constituent Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
Description
【発明の詳細な説明】
本発明はクロツクパルス発生回路に係り、特に
電源周波数に同期したパルスを発生するクロツク
パルス発生回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock pulse generation circuit, and more particularly to a clock pulse generation circuit that generates pulses synchronized with a power supply frequency.
一般に、進行時間の長いシーケンス制御回路で
は、電源周波数に同期したパルスをクロツクパル
スとして使用することが多い。このような場合、
クロツクパルスを得るのに従来は第１図に示すよ
うな回路を用いていた。すなわち、分圧抵抗器
R1，R2における消費電力を小さくし、また負荷
RLの変動に起因してクロツクパルスのデユーテ
イー比が変化するのを防止する観点から、整流回
路に接続する変成器T1とは別個に、変成器T2を
用いて、電源電圧Eiを変圧し、これをR1，R2で
分圧した後スイツチング回路に入力し、この出力
より電源周波数に同期したクロツクパルスを得る
ものである。 Generally, in sequence control circuits with long running times, pulses synchronized with the power supply frequency are often used as clock pulses. In such a case,
Conventionally, a circuit as shown in FIG. 1 has been used to obtain clock pulses. i.e. voltage divider resistor
Reduce power consumption in R 1 and R 2 and reduce load
In order to prevent the duty ratio of the clock pulse from changing due to fluctuations in R L , a transformer T 2 is used to transform the power supply voltage E i separately from the transformer T 1 connected to the rectifier circuit. However, this voltage is divided by R 1 and R 2 and then input to a switching circuit, from which a clock pulse synchronized with the power supply frequency is obtained from the output.
しかしながら、上記従来例では変成器を２個用
いることから、制御装置が大きくかつ重くなり、
さらに高価になるという欠点を有していた。 However, since the above conventional example uses two transformers, the control device becomes large and heavy.
It also has the disadvantage of being more expensive.
本発明はかゝる欠点を除去するためになされた
もので、上記の如きクロツクパルス発生回路用の
変成器T2を個別に用いることなく、電源周波数
に同期したクロツクパルスを発生するクロツクパ
ルス発生回路を提供することを目的としている。 The present invention has been made to eliminate such drawbacks, and provides a clock pulse generation circuit that generates clock pulses synchronized with the power supply frequency without using a separate transformer T2 for the clock pulse generation circuit as described above. It is intended to.
以下、本発明の実施例について図面とともに説
明する。 Embodiments of the present invention will be described below with reference to the drawings.
第２図は、１実施例の回路構成を示す。第３図
は、第２図の回路の動作説明図である。 FIG. 2 shows the circuit configuration of one embodiment. FIG. 3 is an explanatory diagram of the operation of the circuit of FIG. 2.
第２図において、変成器T1の１次側端子１，
２は交流電源電圧Eiに、T1の２次側端子は整流
ダイオードD1〜D4よりなる全波整流ブリツジ回
路に、そしてブリツジ回路の出力端子３，４には
平滑コンデンサＣ及び負荷RLをそれぞれ接続す
る。また、整流ダイオードD1の両端には分圧抵
抗R1及び負荷RLより抵抗値が充分大きいR2が直
列に、さらにR1の両端にはフオトカプラPCの発
光ダイオードDOの端子をそれぞれ接続する。フ
オトカプラPCのフオトトランジスタQ2のコレク
タは抵抗ROを介して定電圧ラインVccに接続さ
れ、エミツタは接地する。また、Q2のコレクタ
及びエミツタにそれぞれ接続する端子５，６はク
ロツクパルス出力端子である。 In FIG. 2, primary terminals 1 of transformer T 1 ,
2 is connected to the AC power supply voltage E i , the secondary side terminal of T 1 is connected to a full-wave rectifier bridge circuit consisting of rectifier diodes D 1 to D 4 , and output terminals 3 and 4 of the bridge circuit are connected to a smoothing capacitor C and a load R. Connect each L. In addition, a voltage dividing resistor R 1 and R 2 whose resistance value is sufficiently larger than the load R L are connected in series to both ends of the rectifier diode D 1, and the terminals of the light emitting diode D O of the photocoupler PC are connected to both ends of R 1 . do. The collector of the phototransistor Q2 of the photocoupler PC is connected to the constant voltage line Vcc via the resistor R O , and the emitter is grounded. Further, terminals 5 and 6 connected to the collector and emitter of Q2 , respectively, are clock pulse output terminals.
次に、本実施例の動作を説明すると、第２図Ａ
点には第３図イに示すように交流電圧EAが出力
し、Ｂ点にはEAが整流ダイオードD1〜D4によつ
て全波整流され、さらに平滑コンデンサＣにより
平滑されることにより、電圧EBが出力し、EBは
端子３，４に接続されている負荷RL（例えば定電
圧発生回路）に入力する。一方、AB間の電圧
EBAはEBA＝EB−EAであるから、EBAは同図斜線部
であらわされる。従つて、発光ダイオードDOに
は電圧EBA及び分圧抵抗R1，R2に基づいた電流が
流れる。ここで抵抗R1が接続されていない場合
（R1の抵抗値が無限大の場合）は、EBA＞Ef（Ef：
発光ダイオードDOの順方向電圧降下）の期間中、
発光ダイオードDOに順方向電流が流れることに
より、DOは発光し、これによりフオトトランジ
スタQ2はオン状態になるから、端子５，６間の
電圧は「Ｌ」になる。 Next, to explain the operation of this embodiment, FIG.
As shown in Figure 3 A, AC voltage E A is output at point B, and E A is full-wave rectified by rectifier diodes D 1 to D 4 and further smoothed by smoothing capacitor C. As a result, a voltage E B is output, and E B is input to a load R L (for example, a constant voltage generation circuit) connected to terminals 3 and 4. On the other hand, the voltage between AB
Since E BA is E BA =E B -E A , E BA is represented by the shaded area in the figure. Therefore, a current based on the voltage E BA and the voltage dividing resistors R 1 and R 2 flows through the light emitting diode D O. If resistor R 1 is not connected here (if the resistance value of R 1 is infinite), E BA > E f (E f :
During the forward voltage drop of the light emitting diode D O ),
When a forward current flows through the light emitting diode D O , the light emitting diode D O emits light, which turns the phototransistor Q 2 on, so that the voltage between the terminals 5 and 6 becomes "L".
次に分圧抵抗R1を接続すれば、発光ダイオー
ドDOが接続していないときのR1の両端の電圧は
EBA・R1／（R1＋R2）であるから、EBA・R1／
（R1＋R2）＞Efの期間中、端子５，６間の電圧は
「Ｌ」になる。従つてR1を適当に選ぶことによ
り、クロツクパルスのデユーテイー比を希望の値
することができる。例えば、EBAがEBAO（交流電圧
EAが正（負）から負（正）移る時点のEBAの値）
のとき、EBAO・R1／（R1＋R2）＝Efとなるように
R1を選べば、端子５，６間には第３図ハに示す
ようなデユーテイー比50％のクロツクパルスが出
力する。 Next, if we connect the voltage dividing resistor R 1 , the voltage across R 1 when the light emitting diode D O is not connected is
Since E BA・R 1 / (R 1 + R 2 ), E BA・R 1 /
During the period (R 1 +R 2 )>E f , the voltage between terminals 5 and 6 becomes "L". Therefore, by choosing R1 appropriately, the duty ratio of the clock pulse can be set to a desired value. For example, E BA is E BAO (AC voltage
The value of E BA when E A changes from positive (negative) to negative (positive))
Then, E BAO・R 1 / (R 1 + R 2 )=E f .
If R1 is selected, a clock pulse with a duty ratio of 50% as shown in FIG. 3C is output between terminals 5 and 6.
こゝで発光ダイオードDOの順方向電流は負荷
RLより充分高い抵抗値を有するR1によつて制限
されており、また整流ダイオードD1は発光ダイ
オードDOの逆方向過電圧防止用ダイオードとし
ても作用する。 Here, the forward current of the light emitting diode D O is the load
The rectifier diode D 1 is limited by R 1 having a sufficiently higher resistance value than R L , and the rectifier diode D 1 also acts as a reverse overvoltage prevention diode for the light emitting diode D O.
なお、前記実施例では交流電圧は整流ダイオー
ドD1〜D4によつて全波整流されるとして説明し
たが、これは整流ダイオード２個を使用して得ら
れる半波整流であつてもよい。 In the above embodiment, the alternating current voltage was described as being full-wave rectified by the rectifier diodes D 1 to D 4 , but this may be half-wave rectification obtained by using two rectifier diodes.
以上の実施例の説明より明らかなように、本発
明に係るクロツクパルス発生回路は、整流回路を
構成する整流ダイオードの両端の電圧差に基づい
て、電源周波数に同期したクロツクパルスを発生
するため、回路を構成する部品点数を増加させる
ことなくクロツクパルス発生回路用に使用してい
た個別の変成器を省くことができるので、制御装
置の小型化、軽量化を図ることができ有利であ
る。また制御装置の製造コストの低減化にもな
る。 As is clear from the description of the embodiments above, the clock pulse generation circuit according to the present invention generates clock pulses synchronized with the power supply frequency based on the voltage difference across the rectifier diodes constituting the rectifier circuit. Since the separate transformer used for the clock pulse generation circuit can be omitted without increasing the number of constituent parts, it is advantageous that the control device can be made smaller and lighter. Furthermore, the manufacturing cost of the control device can be reduced.
さらに、本発明に係るクロツクパルス発生回路
は発光ダイオードに並列接続される抵抗の値を変
えることにより、クロツクパルスのデユーテイー
比を広範囲に変化させることができる。 Furthermore, the clock pulse generating circuit according to the present invention can vary the duty ratio of the clock pulse over a wide range by changing the value of the resistor connected in parallel to the light emitting diode.
第１図は従来のクロツクパルス発生回路の実施
例を示す接続図、第２図は本発明に係るクロツク
パルス発生回路の１実施例を示す接続図、第３図
は第２図の動作説明用波形図である。
T1，T2……変成器、D1〜D4……整流ダイオー
ド、R1，R2……分圧抵抗、PC……フオトカプ
ラ、DO……発光ダイオード、Q2……フオトトラ
ンジスタ、RL……負荷。
FIG. 1 is a connection diagram showing an embodiment of a conventional clock pulse generation circuit, FIG. 2 is a connection diagram showing an embodiment of a clock pulse generation circuit according to the present invention, and FIG. 3 is a waveform diagram for explaining the operation of FIG. 2. It is. T 1 , T 2 ... Transformer, D 1 to D 4 ... Rectifier diode, R 1 , R 2 ... Voltage dividing resistor, PC ... Photo coupler, D O ... Light emitting diode, Q 2 ... Photo transistor, R L ...Load.
Claims (1)
なり、正弦波交流電源を整流して負荷に直流電力
を供給する全波整流回路と、 前記複数の整流ダイオードのうち１個の整流ダ
イオードの両端に並列に接続され、該ダイオード
の端子間電圧を分圧してクロツクパルスのＬ（ロ
ー）となつている期間が50％以上100％未満であ
るように前記パルスのデユーテイー比を変化せし
めるための複数の抵抗の直列接続回路からなるク
ロツクパルスデユーテイー比調整用抵抗回路と、 前記抵抗回路によつて得られた前記１個の整流
ダイオードの端子間電圧の分圧電圧が印加された
発光素子と、 定電圧電源の端子間に抵抗を介して接続され、
前記発光素子の発光を検知してオンオフ動作する
受光素子と、で構成されたクロツクパルス発生回
路。[Scope of Claims] 1. A full-wave rectifier circuit comprising a plurality of rectifier diodes and a smoothing capacitor, which rectifies a sine wave AC power source and supplies DC power to a load; and one rectifier diode among the plurality of rectifier diodes. connected in parallel across both ends of the diode, for dividing the voltage between the terminals of the diode and changing the duty ratio of the clock pulse so that the period during which the clock pulse is L (low) is 50% or more and less than 100%. A clock pulse duty ratio adjusting resistor circuit consisting of a series connection circuit of a plurality of resistors; and a light emitting device to which a divided voltage of the voltage across the terminals of the one rectifier diode obtained by the resistor circuit is applied. It is connected between the element and the terminals of the constant voltage power supply through a resistor.
A clock pulse generation circuit comprising a light receiving element that detects light emission from the light emitting element and turns on and off.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56145374A JPS5846719A (en) | 1981-09-14 | 1981-09-14 | Generating circuit of clock pulse |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56145374A JPS5846719A (en) | 1981-09-14 | 1981-09-14 | Generating circuit of clock pulse |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5846719A JPS5846719A (en) | 1983-03-18 |
| JPH0324091B2 true JPH0324091B2 (en) | 1991-04-02 |
Family
ID=15383743
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56145374A Granted JPS5846719A (en) | 1981-09-14 | 1981-09-14 | Generating circuit of clock pulse |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5846719A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59169143U (en) * | 1983-04-26 | 1984-11-12 | 菊水電子工業株式会社 | Line signal extraction circuit |
| WO2007056365A1 (en) * | 2005-11-08 | 2007-05-18 | Graphic Packaging International, Inc. | Carton with reinforced handle |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5181170A (en) * | 1975-01-13 | 1976-07-15 | Mitsubishi Electric Corp | ISOKENSHUTSUSOCHI |
-
1981
- 1981-09-14 JP JP56145374A patent/JPS5846719A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5181170A (en) * | 1975-01-13 | 1976-07-15 | Mitsubishi Electric Corp | ISOKENSHUTSUSOCHI |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5846719A (en) | 1983-03-18 |
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