JPH03238371A - Semiconductor integrated circuit and test method - Google Patents

Abstract

PURPOSE:To lower production costs with a simplification of a burn-in board of the apparatus by arranging a burn-in mode generation circuit, a clock mode generation circuit and a mode selection circuit. CONSTITUTION:For example, a mode setting voltage TV higher than a normal operation voltage Vcc is applied to internal input terminal IN1. First, test signals SA and SB are generated from a mode generation circuit 22. The test signals SA and SB are outputted to a clock mode generation circuit 23 and a mode selection circuit 24 through control lines S11, S12 and S2. With the circuit 23, a clock supply pC is separated from an external clock CL based on the test signals SA and SB and a terminal CL is connected to the circuit 24 separately to alter destinations of supply of a clock signal CLK. On the other hands, in the circuit 24, likewise, external input terminals IN2-IN50 are separated from other input sections p2-p50 of an internal logic circuit 21 based on the signals SA and SB and a signal CLK supply line S2 is connected to the other input sections p2-p50 of the circuit 21 thereby selecting a test mode from normal mode.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Prior Art (Figure 8) Problem to be Solved by the Invention (Figure 9) Means for Solving the Problem (Figures 1 and 2) ) Functional Examples (i) Description of the first embodiment (Figs. 3 to 5) (11) Description of the second embodiment (Fig. 6) (m) 1. Explanation of the test method according to the second embodiment (Fig. 7) Effects of the invention [Summary] The initial failure mode of a semiconductor integrated circuit device, especially a pancage-sold LSI under test (semiconductor integrated circuit device W) is eliminated. Regarding device functions related to burn-in tests (high-temperature running tests) to stabilize its characteristics, the LS under test can be used without connecting pull-up resistors to each input/output pin of the socket adapter for the burn-in test.
The first device has multiple external input terminals connected to the internal circuit. , an external output terminal, an external clock terminal, and other external terminals, at least an external A clock mode in which a test mode generation circuit that generates a test signal based on an applied voltage is provided between a clock supply point of the internal circuit and an external clock terminal, and a destination of the clock signal is changed based on the test signal. a mode selection mode for selecting between a normal operation mode and a test mode based on the test signal, wherein a generation circuit is provided between another input section of the internal circuit and an external input terminal extending from the other input section; The circuits are individually provided, and the control lines from the test mode generation circuit and the clock mode generation circuit are respectively connected to each mode selection circuit, and the second device is different from the first device. The mode selection circuit is individually provided between an output section of the internal circuit and an external output terminal extending from the output section.

[Industrial application field]

The present invention relates to a semiconductor integrated circuit device and a testing method thereof, and more specifically, to stabilize the characteristics of a packaged LSI (semiconductor integrated circuit device) by eliminating its initial failure mode. Burn-in test (
This article relates to device functions and test methods related to high-temperature running tests.

In recent years, in semiconductor integrated circuit devices such as CMOS gate arrays, there are hundreds to hundreds of
Internal logic circuits with hundreds of thousands of gates are built into a single LSI package, and proportionally more than several hundred pins of external terminals are manufactured.

Incidentally, a burn-in test (high temperature running test) is performed on a packaged LSI device in order to stabilize its transistor characteristics and eliminate its initial failure mode.

According to this, it is necessary to apply a level voltage to all pins in order to prevent problems such as latch-up.

The level voltage is obtained by connecting a pull-up resistor to each terminal of a socket adapter provided on the burn-in board and applying power to it.

However, as the number of external terminals increases, the number of resistors becomes enormous.

Therefore, we have developed a device that can simplify the burn-in test of LSI devices with a large number of pins by devising the internal circuit of the LSI device without connecting pull-up resistors to each terminal of the adapter. A method is desired.

[Conventional technology]

FIG. 8.9 is an explanatory diagram of a conventional example.

FIG. 8 shows a configuration diagram of a burn-in test for a semiconductor integrated circuit device according to a conventional example.

In the figure, in the burn-in test (high temperature running test) of the LSI under test 5 which is packaged with a CMOS gate array, etc., first, the LSI under test 5 is
3, and set it in the high-temperature running test device 1.

Next, a test voltage TE is applied to the burn-in board 2 by the test control circuit 4. At this time, a leher voltage is applied to all pins in order to prevent problems such as the launch amplifier of the LSI 5 under test. As shown in FIG. 9, the cough voltage is applied to the input/output bin of the socket adapter 3 provided on the burn-in board 2, that is, each input terminal IN of the LSI under test 5.
Pull-up resistors Ril-R4n are connected to 1-INn, n, and pull-up resistors RO are connected to each output terminal OTI-OTn.
This is obtained by connecting I to ROn and applying a power supply vCC thereto.

Next, the test apparatus l is placed in a high temperature atmosphere, and the LSI under test is
5 is operated for a predetermined period of time.

As a result, the initial failure mode of the LSI under test 5 is eliminated, and the transistor characteristics thereof can be stabilized.

[Problem to be solved by the invention]

By the way, according to the conventional example, there is a tendency for an internal logic circuit having a configuration of tens of thousands to hundreds of thousands of gates to be incorporated into one LSI package due to the functional requirements of user B. However, even with this LSI under test 5 with a large number of pins,
It must be attached to the socket adapter 3 and a burn-in test (high temperature running test) must be performed.

Therefore, as shown in FIG. 9, pull-up resistors Ril to Rin, R are used to prevent problems such as latch-up.
O1=ROn is the external terminal (INI) of the LSI5 under test.
~INn, OTI ~0Tn), it is necessary to connect to each input/output bin of the socket adapter 3 in proportion to the number.

This increases the number of resistors, increasing the manufacturing cost of the socket adapter 3 and complicating the design of the burn-in board 2. As a result, the LS under test with multiple bins
There is a problem in that the cost of burn-in testing of I5 increases.

The present invention was created in view of the problems of the conventional example, and devises the internal circuit of the LSI under test without connecting a pull-up resistor to each input/output bin of the socket adapter related to the burn-in test. An object of the present invention is to provide a semiconductor integrated circuit device and a test method thereof, which make it possible to simplify and reduce the cost of burn-in tests for devices with a large number of bins. [Means for Solving the Problems] Figure 1 is a diagram showing the principle of a semiconductor integrated circuit device according to the present invention, and Figures 2 (a) and (b) are diagrams showing the principle of the test method. There is.

The first device includes an internal circuit 11 and the internal circuit 11.
A plurality of external input terminals IN1 to INn, n,
n=1.2. - i-..., external output terminal OT
1~OTn.

In a semiconductor integrated circuit device including an external clock terminal CL and another external terminal ET, at least between one input section pi of the internal circuit 11 and an external input terminal INi extending from the input section pi, A test mode generating circuit 12 that generates test signals SA and SB based on externally applied voltages is provided between the clock supply point pc of the internal circuit 11 and the external clock terminal CL. A clock mode generation circuit 13 is provided which changes the supply destination of the clock signal CLK, and connects the other input section pn+pi of the internal circuit 11 and the other input section p.
External input terminal INn extending from n qk p i
A mode selection circuit 14 for selecting a normal operation mode and a test mode based on the test signals SA and SH is individually provided between the test mode generating circuit 12 and the test mode generation circuit 12.
and a control line SL from the clock mode generation circuit 13,
S2 is connected to each moto selection circuit 14, and the second device is a first device, and the mode selection circuit 14 is connected to the output parts q1 to qn of the internal circuit 11. External output terminals OTI~O extending from the output parts q1~qn
The test method is as described in the above-mentioned No. 1. A second device testing method, in which an external input terminal INi connected to a test mode generation circuit 12 is determined in advance as a test mode setting terminal 7-TT, and the test mode setting terminal TT is set to a voltage higher than a normal operating voltage VCC. The present invention is characterized in that a high mode setting voltage Tv>VCC is applied, a clock signal clk is supplied to the external clock terminal CL, and the internal circuit 11 is operated in a high-temperature atmosphere.

[Function] According to the first device of the present invention, the test mode generation circuit 12
．． Clock mode generation circuit 13 and mode selection circuit 14
are provided, and control lines S1 and S2 from the test mode generation circuit 12 and the clock mode generation circuit 13 are connected to each mode selection circuit 14, respectively.

Therefore, by applying, for example, an external voltage higher than the normal operating voltage to the external input terminal INi provided with the test mode generating circuit 12, the mode generating circuit 12 is first
2, test signals SA and SB are generated. The test signals SA and SB are output to the clock mode generation circuit 13 and the mode selection circuit 14 via control lines S1 and S2.

Further, in the clock mode generation circuit 13, the test signal SA
, SB, the clock supply point pc and the external clock terminal CL are separated, and the external clock terminal CL is connected to each mode selection circuit 14 to receive the clock signal C.
The LK supply destination is changed.

- In each mode selection circuit 14, the test signal SA
, the other input part pr+f of the internal circuit 11 based on SB
-pi and the external input terminal INn≠INi are separated, and the clock signal C is applied to the other input terminal pn≠pi of the internal circuit 11.
The LK supply line is connected and the test mode is selected from the normal operation mode.

This eliminates the need to connect a pull-up resistor to the manual pin of the socket adapter in order to prevent problems such as a latch knob as in the conventional example.

This reduces the manufacturing cost of the socket adapter and simplifies the design of the burn-in board since no resistor is required. Therefore, it is possible to simplify the burn-in test of the device with a large number of bins, and to reduce the cost.

Further, according to the second device of the present invention, the mode selection circuit 1
4 is the output part 91~qn of the internal circuit 11 and the output part q1~
They are individually connected between external output terminals 0T1-OTn extending from qn.

For this reason, similar to the first device, the test signal SA.

The output parts q1 to qn of the internal circuit 11 and the external output terminals OTI to OTn are separated based on SB, and the internal circuit 11
A supply line for the clock signal CLK is connected to the output parts q1 to qn of the test mode, and the test mode is selected from the normal operation mode.

This eliminates the need to connect a pull-up resistor to the output pin of the socket adapter in order to prevent problems such as latch-up as in the conventional example, as in the first device.

This makes it possible to simplify and reduce the cost of burn-in tests for the multi-bin device.

Further, according to the test method of the present invention, a mode setting voltage TV>VCC is applied to a predetermined test mode setting terminal TT, a clock signal clk is supplied to an external clock terminal CL, and the internal circuit 11 is placed in a high temperature atmosphere. It is running inside.

Therefore, compared to the conventional method of applying a uniquely determined level voltage to an external input/output terminal, by supplying the activated clock signal clk to the input/output terminal,
Burn-in tests can be performed assuming the actual usage conditions of the device.

This makes it possible to improve the burn-in effect of eliminating initial failure modes and stabilizing the characteristics.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

3 to 7 are explanatory diagrams of a semiconductor integrated circuit device and a testing method thereof according to an embodiment of the present invention.

(1) Description of the first embodiment FIG. 3 is a block diagram of a semiconductor integrated circuit device according to the first embodiment of the present invention.

In the figure, 21 is an example of the internal circuit 11.
This is an internal logic circuit such as a MOS gate array. The internal logic circuit 21 includes, for example, external input terminals IN1 to IN50.
．． Input section p connected to (n = L2. ・50)
1-p 50. Output sections 91-950. connected to external output terminals OTI-0T50. a clock supply point pc and a power supply terminal ET (+) connected to an external clock terminal CL;
A power supply section e(+)(-) connected to (-) is provided.

Here, in the embodiment of the present invention, the external input terminal INI is the test mode setting terminal TT, and the other external input terminals IN2 to l
It has a higher insulation structure than N50.

A burn-in mode generating circuit 22 is an embodiment of the test mode generating circuit 12, and generates test signals SA and SB based on an externally applied voltage. The burn-in mode generating circuit 22 is provided between a specific input section P1 of the internal logic circuit 21 and a test mode setting terminal lN1=TT extending from the input section P1.

The generation circuit 22 includes a level generator 22A and a comparator 22B.
and a buffer 22C. The level generator 22A generates a preset comparison voltage level VR. The comparator 22B applies the normally used voltage VC to the setting terminal TT.
When a mode setting voltage TV>νCC higher than C is applied, AND logic processing of both voltages TV and VR is performed to activate the buffer 22C.

The buffer 22C generates test signals S^, SB such as inverted and non-inverted signals based on AND logic processing.

The test signals SA and SB are transmitted to the clock mode generation circuit 23 and each mode selection circuit 24 via control lines Sl1 and S12, respectively.

23 is a clock mode generation circuit, which generates test signals SA,
The supply destination of the clock signal CLK is changed based on SB. The clock mode generation circuit 23 connects the clock supply point pc of the internal logic circuit 21 and the external clock terminal C.
It is provided between L. In addition, the mode generation circuit 2
3 comes from switching transistors TI and T2. The TI function is "○NJL" during normal use, and "○FFJ" during testing based on the test signals SA and SB.The T2 function is rOFFJL during normal use, and similarly based on the signals SA and SB during testing. This is what I do at rONJ.

The clock signal CLK is transmitted to each mode selection circuit 24 via the supply line S2.

As a result, the clock signal CLK is supplied to the clock supply point pc of the internal logic circuit 21 during normal use, and the signal CLK is supplied to the mode selection circuit 24 during testing.

Reference numeral 24 denotes a mode selection circuit, which selects between a normal operation mode and a test mode based on test signals SA and SH. The mode selection circuit 24 is individually provided between the other input parts p2-P50 of the internal logic circuit 21 and the external input terminals IN2-1150 extending from the other input parts P2-p50. The selection circuit 24 also includes switching transistors T3. Powerful from T4. The function of T3 is rONJ L during normal use and test signal S during testing.
A, rOFFJ based on SH. In addition, the function of T4 is to turn OFF during normal use, and turn ON during testing based on the signals SA and SB.

As a result, during normal use, external input terminals INI to lN
50 terminal information is transmitted to input parts pi-p50, respectively, and clock signal CLK is transmitted to input parts p2 to p5 during testing.
0, the mode setting voltage RTV is set to the test mode setting terminal TT.
are supplied respectively.

These constitute a semiconductor integrated circuit device according to the first embodiment of the present invention.

4 is an equivalent circuit in burn-in mode according to the first embodiment of the present invention, and FIG. 5 is an equivalent circuit in the burn-in mode according to the first embodiment of the present invention.
The equivalent circuits of the embodiments in normal use are shown respectively.

Thus, according to the first embodiment of the present invention, burn-in mode generating circuit 22. Clock mode generation circuit 23
and a mode selection circuit 24 are provided, and a control line Sl from the mode generation circuit 22 and the clock mode generation circuit 23 is provided.
1. S12 and supply line S2 are connected to each mode selection circuit 24
are connected to each.

Therefore, by applying, for example, a mode setting voltage TV higher than the normal operating voltage VCC to the external input terminal INI provided with the burn-in mode generating circuit 22, the test signals SA, SB are first generated from the mode generating circuit 22. occurs. These test signals S^, SB are the control line S11
．． 312. Clock mode generation circuit 2 via S2
3 and the mode selection circuit 24.

Further, in the clock mode generation circuit 23, the test signal SA
, SB, the clock supply point pc and the external clock terminal CL are separated, and the external clock terminal CL is connected to each mode selection circuit 14 to output the clock signal CL.
The supply destination of K is changed.

On the other hand, in each mode selection circuit 24, the test signal SA
, the other input part p2 of the internal logic circuit 21 based on SB
~p50 and the external input terminals IN2-11150 are separated, and the supply line S2 of the clock signal CLK is connected to the other input parts p2-P50 of the circuit 21, so that the test mode is selected from the normal operation mode.

This eliminates the need to connect a pull-up resistor to the input bin of the socket adapter in order to prevent problems such as a launch amplifier as in the conventional example.

This reduces the manufacturing cost of the socket adapter by eliminating the need for a resistor, and simplifies burn-in test design. Therefore, it is possible to simplify the burn-in test of the device with a large number of bins, and to reduce the cost.

(II) Description of Second Embodiment FIG. 6 is a block diagram of a semiconductor integrated circuit device according to a second embodiment of the present invention.

In the figure, in the second embodiment, which is different from the first embodiment, the mode selection circuit 24 is connected to the output section q of the internal logic circuit 21.
1-(150) and the external output terminals OTI to 0T50 extending from the output parts q1 to qso.

Note that components having the same reference numerals and names as those in the first embodiment have the same functions, and therefore their explanations will be omitted.

In this manner, according to the second embodiment of the present invention, the mode selection circuit 24 is configured to output the outputs 91 to Q5 of the internal logic circuit 21.
0 and an external output terminal O extending from the output parts 91 to q50.
They are individually connected between TI and 0T50.

Therefore, as in the first embodiment, the test signal SA.

Output part ql-q50 of internal logic circuit 21 based on SB
and external output terminals OTI-0T50 are separated, and the supply line S2 of the clock signal CLK is connected to the output parts 91-Q50 of the circuit 21, so that the test mode is selected from the normal operation mode.

This eliminates the need to connect a pull amplifier resistor to the output bin of the socket adapter in order to prevent problems such as latch-up as in the conventional example, as in the first embodiment.

This makes it possible to simplify and reduce the cost of burn-in tests for devices with a large number of pins.

(iii) 1st. Explanation of the test method according to the second embodiment FIGS. 7(a) and (b) show the LS according to the embodiment of the present invention.
FIG. 2 is an explanatory diagram of a burn-in test method for I, and FIG.

In the same figure (a), the first. A high temperature running test device 25 that performs a burn-in test on an LSI under test 26 such as a semiconductor integrated circuit device according to the second embodiment includes a test control circuit 25.
a, high temperature container 25b, socket adapter 25c, heater 25d, etc.

The test control circuit 25a supplies the mode setting voltage TV, the clock signal elk, and the operating voltages VCC (+) and (-) to the socket adapter 25c, and supplies heating power to the heater 25d to set the initial failure mode of the LSI 26 under test. This is to stabilize the characteristics of the material. In addition,
Unlike the conventional example, a pull-up resistor is not connected to the terminal portion of the socket adapter 25c according to the embodiment of the present invention.
That part is empty.

FIG. 6(b) shows the test flowchart.

In FIG. 2B, first, in step P1, the external input terminal I is connected to the burn-in mode generation circuit 22 in advance.
NI is defined as burn-in mode setting terminal TT. In addition,
It is sufficient if the manufacturer knows the position of the terminal TT.

Next, in step P2, the burn-in mode setting terminal TT is
mode setting voltage Tν> which is higher than the normal operating voltage vCC>
Apply VCC. At this time, the ratio H'TI pressure level R from the level generator 22A of the burn-in mode generation circuit 22 is compared with the mode setting voltage TV, and the both types of pressure TV,
As a result of VR's AND logic processing, buffer 22C is activated. As a result, the test signal SA from the buffer 22C,
SB is transmitted to the clock mode generation circuit 23 and each mode selection circuit 24 via control lines Sl1 and 312, respectively.

Thereafter, in step P3, the clock signal elk is supplied to the external clock terminal CL. At this time, the test signal SA,
Based on SB, the switching transistor T1 of the clock mode generation circuit 23 changes from rONJ to rOFFJ.

Further, the transistor T2 is turned on from 0FFJ, and thereby the clock signal CLK is transmitted to each mode selection circuit 24 via the supply line S2.

Further, in step P4, the LSI under test 26 is carried into the high temperature running test apparatus 25.

Next, in step P5, the LSI under test 26 is operated in a high temperature atmosphere for a predetermined period of time.

As a result, the first aspect of the present invention. A burn-in test can be performed on the semiconductor integrated circuit device according to the second embodiment.

In this way, according to the test method according to the embodiment of the present invention, the mode setting voltage TV>VCC is applied to the predetermined burn-in mode setting terminal TT in step P2, and the clock is applied to the external clock terminal CL in step P3. signal elk
is supplied, and the internal logic circuit 21 is operated in a high temperature atmosphere in step P5.

Therefore, compared to the conventional method of applying a level voltage uniquely determined by a pull-up resistor connected to an external input/output terminal to the external input/output terminal,
．． An activated clock signal elk is supplied to ql to q50. This makes it possible to conduct a burn-in test assuming the actual usage state of the device, that is, the normal operating state in which reversal and non-reversal are repeated.

This makes it possible to improve the burn-in effect of eliminating initial failure modes and stabilizing the characteristics.

〔Effect of the invention〕

As described above, according to the present invention, a test mode generation circuit, a clock mode generation circuit, and a mode selection circuit are provided, and in the burn-in mode, a clock signal is sent to each mode selection circuit based on control information from the test mode generation circuit. Each can be supplied.

Therefore, there is no need for a pull amplifier resistor to prevent problems such as latch-up as in the conventional example. This makes it possible to reduce the manufacturing cost of the socket adapter and simplify the design of the burn-in board.

This makes it possible to simplify the burn-in test of the semiconductor integrated circuit device with a large number of pins, and to reduce the cost. It also greatly contributes to improving the reliability of burn-in tests.

[Brief explanation of drawings]

FIG. 1 is a diagram of the principle of a semiconductor integrated circuit device according to the present invention, FIG. 2 is a diagram of the principle of a test method for a semiconductor integrated circuit device according to the present invention, and FIG. 3 is a diagram of a first embodiment of the present invention. FIG. 4 is an equivalent circuit diagram in hun-in mode according to the first embodiment of the present invention, and FIG. 5 is a normal circuit diagram according to the first embodiment of the present invention. An equivalent circuit diagram in use; FIG. 6 is a configuration diagram of a semiconductor integrated circuit device according to a second embodiment of the present invention; FIG. 7 is an explanatory diagram of an LSI burn-in test method according to an embodiment of the present invention. , FIG. 8 is a block diagram of a burn-in test method for a semiconductor integrated circuit device according to a conventional example, and FIG. 9 is a peripheral circuit diagram of a socket adapter illustrating problems related to the conventional example. (Explanation of symbols) 11...Internal circuit, 12...Test mode generation circuit, 13...Clock mode generation circuit, 14...Mode selection circuit, IN1-INn, INi-external input terminal ,
OTI~OTn...external output terminal, CL...external clock terminal, ET...other external terminal, pi...input section, SA, SB...test signal, pC...clock supply point , CL... external clock terminal, CLK... clock signal, pn≠pi... other input section, 51, S2... control line.

Claims (3)

[Claims] (1) An internal circuit (11) and a plurality of external input terminals (IN1 to INn, n=1) connected to the internal circuit (11).
, 2,...i...), external output terminals (OT1 to OTn), external clock terminal (CL), and other external terminals (ET)
In a semiconductor integrated circuit device comprising: at least one input section (pi) of the internal circuit (11) and an external input terminal (INi) extending from the input section (pi), an Test signal (SA, SB) based on voltage
A test mode generation circuit (12) that generates the test signals (SA,
A clock mode generation circuit (13) is provided that changes the supply destination of the clock signal (CLK) based on the clock signal (CLK) based on the input section (pn≠pi) of the internal circuit (11) and the other input section ( External input terminal (pn≠pi) extending from
The test signals (SA, SB
) are individually provided with mode selection circuits (14) for selecting the normal operation mode and the test mode based on the control lines (S1, S2) from the test mode generation circuit (12) and the clock mode generation circuit (13). ) are respectively connected to each mode selection circuit (14). (2) The semiconductor integrated circuit device according to claim 1, wherein the mode selection circuit (14) extends from an output section (q1 to qn) of the internal circuit (11) and the output section (q1 to qn). 1. A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is individually provided between external output terminals (OT1 to OTn). (3) The method for testing a semiconductor integrated circuit device according to claim 1, wherein the external input terminal (INi) to which the test mode generating circuit (12) is connected is connected to the test mode setting terminal (TT) in advance.
), and a mode setting voltage (TV>VC) higher than the normal operating voltage (VCC) is applied to the test mode setting terminal (TT).
C), a clock signal (clk) is supplied to the external clock terminal (CL), and the internal circuit (11) is operated in a high-temperature atmosphere.