JPH03235356A - Ic mounting structure - Google Patents
Ic mounting structureInfo
- Publication number
- JPH03235356A JPH03235356A JP3183990A JP3183990A JPH03235356A JP H03235356 A JPH03235356 A JP H03235356A JP 3183990 A JP3183990 A JP 3183990A JP 3183990 A JP3183990 A JP 3183990A JP H03235356 A JPH03235356 A JP H03235356A
- Authority
- JP
- Japan
- Prior art keywords
- pedestal
- wiring board
- heat
- sections
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims abstract description 24
- 230000017525 heat dissipation Effects 0.000 claims description 37
- 238000012546 transfer Methods 0.000 claims description 18
- 229910052802 copper Inorganic materials 0.000 abstract description 24
- 239000010949 copper Substances 0.000 abstract description 24
- 229920001721 polyimide Polymers 0.000 abstract description 24
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 23
- 239000004642 Polyimide Substances 0.000 abstract description 20
- 239000000919 ceramic Substances 0.000 abstract description 14
- 230000005855 radiation Effects 0.000 abstract description 11
- 238000007747 plating Methods 0.000 description 4
- 239000009719 polyimide resin Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000003780 insertion Methods 0.000 description 3
- 230000037431 insertion Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、複数のチップを高密度に搭載するマルチチッ
プモジュール等に用いられるＩＣ実装構造に関し、特に
その放熱構造に関する。DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to an IC mounting structure used in a multi-chip module or the like in which a plurality of chips are mounted at high density, and particularly to a heat dissipation structure thereof.
〈従来の技術）
近年、高速信号処理及び高集積を目的として、誘電率の
低いポリイミド樹脂を居間絶縁膜とじた銅ポリイミド配
線基板か用いられるようになってきた。ところがこのポ
リイミド樹脂は熱伝導率が非常に低い為、許容発熱密度
が小さく、高速・高発熱ＩＣチップの搭載に制限を受け
る。従って、特にこの様な熱伝導率の低い配線基板上に
複数のＩＣチップを高密度に搭載するマルチチップモジ
ュール等のＩＣ実装構造では、ＩＣチップの放熱か重要
な問題となる。(Prior Art) In recent years, for the purpose of high-speed signal processing and high integration, copper polyimide wiring boards made of polyimide resin with a low dielectric constant and an insulating film have been used. However, since this polyimide resin has extremely low thermal conductivity, its allowable heat generation density is low, which limits the mounting of high-speed, high-heat generation IC chips. Therefore, particularly in IC mounting structures such as multi-chip modules in which a plurality of IC chips are mounted at high density on a wiring board with low thermal conductivity, heat dissipation from the IC chips becomes an important issue.
ＩＣチップの放熱を高めた従来のＩＣ実装構造としては
、例えば、「銅ポリイミド配線板を用いたマルチ・チッ
プモジュールの冷却特性、（１９８９年電子情報通信学
会春季全国大会講演論文集Ｃ−１６０）に示されたもの
がある。そのＩＣ実装構造を、第３図の断面図を用いて
説明する。Conventional IC mounting structures that improve the heat dissipation of IC chips include, for example, ``Cooling Characteristics of Multi-Chip Modules Using Copper-Polyimide Wiring Boards'' (1989 Institute of Electronics, Information and Communication Engineers Spring National Conference Proceedings C-160). The IC mounting structure will be explained using the cross-sectional view of FIG.
図の様にこのマルチチップモジュールでは、セラミック
配線基板２１上に銅ポリイミド配線基板２２か形成され
、その銅ポリイミド配線基板２２上に複数のＩＣチップ
２３か搭載されるとともに、セラミック配線基板２１の
下面には放熱フィン２４か接着されている。上記ＩＣチ
ップ２３は、ボンディングワイヤ２５で上記銅ポリイミ
ド配線基板ｚ２と電気的に接続され、更にＩ１０ピン２
６の付いたパッケージ２７て封止されている。As shown in the figure, in this multi-chip module, a copper polyimide wiring board 22 is formed on a ceramic wiring board 21, and a plurality of IC chips 23 are mounted on the copper polyimide wiring board 22. Radiating fins 24 are bonded to the fins. The IC chip 23 is electrically connected to the copper polyimide wiring board z2 by a bonding wire 25, and further connected to the I10 pin 2.
The package 27 marked with 6 is sealed.
そしてこのＩＣ実装構造ては、ＩＣチップＺ３の放熱の
為に、熱伝導率の極めて低い銅ポリイミド配線基板２２
に、各ＩＣチップ２３とセラミック配線基板２１とを連
結した状態で、多数の放熱用ヴイア２８か形成されてい
る。この放熱用ヴイア２８は、ＩＣチップ２３をダイボ
ンドする前に、銅ポリイミド配線基板２２に、エツチン
グにより直径１００〜２００ ｇｍの穴を開け、その穴
の内壁を、熱伝導率の高い銅でメツキすることにより形
成される。This IC mounting structure uses a copper polyimide wiring board 22 with extremely low thermal conductivity to dissipate heat from the IC chip Z3.
A large number of heat radiation vias 28 are formed in a state where each IC chip 23 and the ceramic wiring board 21 are connected. This heat dissipation via 28 is made by etching a hole with a diameter of 100 to 200 gm in the copper polyimide wiring board 22 before die-bonding the IC chip 23, and plating the inner wall of the hole with copper having high thermal conductivity. It is formed by
上記構造により、ＩＣチップ２３て発生した熱は、放熱
用ウィア２８てセラミック配線基板２１へ伝えられ、更
にセラミック配線基板２１から放熱フィン２４へ伝えら
れて外部へ放出されることになる。With the above structure, the heat generated by the IC chip 23 is transmitted to the ceramic wiring board 21 through the heat dissipation vias 28, and further transmitted from the ceramic wiring board 21 to the heat dissipation fins 24 and radiated to the outside.
〈発明か解決しようとする課題〉
しかし上述の様な放熱用ヴイア２８を形成した従来のＩ
Ｃ実装構造では、熱伝導率の低い銅ポリイミド配線基板
２２を用いた場合に、充分な放熱効果か得られないとい
う問題かある。<Problem to be solved by the invention> However, the conventional I that formed the heat dissipation via 28 as described above
In the C mounting structure, there is a problem in that a sufficient heat dissipation effect cannot be obtained when a copper polyimide wiring board 22 having low thermal conductivity is used.
例えば、直径１００〜２００ ｐｓの穴の内壁に厚さ５
０鉢富の銅メツキをして成る放熱用ウィア２８を、５Ｘ
５ｔｓサイズのＩＣチップ２３に対応させて０．５ｍ園
のピッチて形成するとした場合、約１００本の放熱用ヴ
イア２８を形成することかてきるが、その約１００本の
放熱用ヴイア２８の全断面積は０．７８■鳳２程度であ
り、これはＩＣチップ２３の面積（２５■ｍ ２ ）の
３％程度にしかならない。よって熱伝達の効率か悪く、
高発熱のＩＣチップを使用することかできない。For example, the inner wall of a hole with a diameter of 100 to 200 ps has a thickness of 5
Heat dissipation wire 28 made of copper plating with 0 pottiness
If it is formed at a pitch of 0.5 m to accommodate a 5ts size IC chip 23, approximately 100 heat dissipation vias 28 will be formed, but all of the approximately 100 heat dissipation vias 28 will be The cross-sectional area is about 0.78 square meters, which is only about 3% of the area of the IC chip 23 (25 square meters). Therefore, the efficiency of heat transfer is poor,
It is only possible to use IC chips that generate high heat.
しかもＩＣチップ２３の下面全域に対応させて多数の放
熱用ヴイアＺ８を形成すると、チップ２３の真下の配線
が不可能となり、配線密度か低下するという問題もある
。Moreover, if a large number of heat dissipating vias Z8 are formed to correspond to the entire lower surface of the IC chip 23, there is a problem that wiring directly under the chip 23 becomes impossible and the wiring density decreases.
更に上述の様な放熱用ウィア２８を形成するには手間と
時間がかかり、その結果大幅なコスト増となってしまう
。Furthermore, it takes time and effort to form the heat dissipation weir 28 as described above, resulting in a significant increase in cost.
〈課題を解決するための手段〉
本発明は、上記種々の問題を解決すべく提案されたＩＣ
実装構造て、本発明に係るＩＣ実装構造では、ＩＣチッ
プをダイボンドする台座部と、その台座部の下面に突設
され配線基板を貫通して放熱フィンに達するピン状の熱
伝達部とより成る台座付放熱ピンを設けた。<Means for Solving the Problems> The present invention is an IC proposed to solve the various problems mentioned above.
The IC mounting structure according to the present invention includes a pedestal portion for die-bonding the IC chip, and a pin-shaped heat transfer portion that protrudes from the lower surface of the pedestal portion and penetrates the wiring board to reach the heat dissipation fins. A heat dissipation pin with a pedestal is provided.
〈作用〉
上記構造によれば、ＩＣチップから発生した熱は、台座
付放熱ピンの台座部から熱伝達部を通して放熱フィンへ
直接伝達され、外部へ放出されることになる。<Operation> According to the above structure, heat generated from the IC chip is directly transmitted from the pedestal part of the pedestal-attached heat radiating pin to the heat radiating fin through the heat transfer part, and is emitted to the outside.
〈実施例〉 以下、図面に基づいて本発明の一実施例を説明する。<Example> Hereinafter, one embodiment of the present invention will be described based on the drawings.
第１図は、本発明に係るＩＣ実装構造を説明する、銅ポ
リイミド配線基板を用いたマルチチップモジュールの断
面図である。FIG. 1 is a sectional view of a multi-chip module using a copper polyimide wiring board, illustrating an IC mounting structure according to the present invention.
図に示す様に、本発明のＩＣ実装構造の特徴は、ＩＣチ
ップｌの放熱手段として、台座部２ａとその台座部２ａ
の下面に突設されたピン状の熱伝達部２ｂとより成る台
座付放熱ピン２を設けた点にある。この台座付放熱ピン
２は、熱伝導率の高い材質、例えば窒化アルミニウムに
より形成される。As shown in the figure, the feature of the IC mounting structure of the present invention is that the pedestal part 2a and the pedestal part 2a serve as heat dissipation means for the IC chip l.
A heat dissipating pin 2 with a pedestal is provided, which consists of a pin-shaped heat transfer portion 2b protruding from the lower surface of the holder. The base-attached heat radiation pin 2 is made of a material with high thermal conductivity, such as aluminum nitride.
このマルチチップモジュールの構造を、製造工程に沿っ
て説明する。The structure of this multi-chip module will be explained along with the manufacturing process.
先ずセラミック配線基板３に、ＩＣチップｌの搭載位置
に対応させて、上記台座付放熱ピン２の熱伝達部２ｂを
挿入させる直径２〜３１の貫通孔３ａを開ける。このセ
ラミック配線基板３には、電源線、クランド線、Ｉ１０
接続用配線等を厚膜印刷などにより形成しておく。First, a through hole 3a having a diameter of 2 to 31 mm is formed in the ceramic wiring board 3, corresponding to the mounting position of the IC chip 1, into which the heat transfer portion 2b of the heat dissipating pin 2 with a base is inserted. This ceramic wiring board 3 includes a power line, a ground line, an I10
Connection wiring and the like are formed by thick film printing or the like.
次いて上記セラミック配線基板３上に、ポリイミド樹脂
を層間絶縁膜とする多層高密度配線基板である銅ポリイ
ミド配線基板４を形成する。その形成には、樹脂コート
、ウイアホールエツチンク、銅メツキ、フォトリソエツ
チングによるパターニングの各工程を繰返すことになる
。この銅ポリイミド配線基板４には、上記セラミック配
線基板３の貫通孔３ａに対応して穴４ａが自然に形成さ
れる。Next, a copper polyimide wiring board 4, which is a multilayer high-density wiring board using polyimide resin as an interlayer insulating film, is formed on the ceramic wiring board 3. For its formation, the steps of resin coating, via hole etching, copper plating, and patterning using photolithography are repeated. Holes 4a are naturally formed in this copper polyimide wiring board 4 in correspondence with the through holes 3a of the ceramic wiring board 3.
次いて上記台座付放熱ピン２の熱伝達部２ｂを、銅ポリ
イミド配線基板４の穴４からセラミック配線基板３の貫
通孔３ａへ挿入し、両配線基板３．４を貫通させる。そ
の際、貫通孔３ａの径が、銅ポリイミド配線基板４形成
時のポリイミド樹脂の流れ込みにより小さくなっている
場合には、トリル等により所定の径まて広げる。Next, the heat transfer portion 2b of the heat dissipation pin 2 with a pedestal is inserted from the hole 4 of the copper polyimide wiring board 4 into the through hole 3a of the ceramic wiring board 3, and penetrates both wiring boards 3.4. At this time, if the diameter of the through hole 3a has become smaller due to the inflow of polyimide resin during the formation of the copper polyimide wiring board 4, it is enlarged to a predetermined diameter using a trill or the like.
上記台座付放熱ピン２の寸法については、本実施例の場
合１台座部２ａの大きさをＩＣチップｌと同し５％５ｍ
ｍ、その台座部２ａの厚さをｌ＋ｓｍに設定した。又熱
伝達部２ｂの直径を２■璽とし、その長さを、後述の放
熱フィン５の中央部まて達する様に設定する。この台座
付放熱ピン２は、非常に安価に提供されるものである。Regarding the dimensions of the heat dissipation pin 2 with a pedestal, in this embodiment, the size of the pedestal part 2a is the same as that of the IC chip l, and is 5%5 m.
m, and the thickness of the pedestal portion 2a was set to l+sm. Further, the diameter of the heat transfer portion 2b is set to 2 cm, and its length is set so as to reach the center of the heat dissipation fin 5, which will be described later. This heat dissipation pin 2 with a base is provided at a very low cost.
上述の如く熱伝達部２ｂを両配線基板３．４に挿着させ
た台座付放熱ピン２の台座部２ａに、ＩＣチップｌをタ
イボンドする。次いてこの様にして搭載したＩＣチップ
ｌと銅ポリイミド配線基板４とを、ボンデインタワイヤ
６で電気的に接続する。The IC chip 1 is tie-bonded to the pedestal part 2a of the heat dissipation pin 2 with a pedestal with the heat transfer part 2b inserted into both wiring boards 3.4 as described above. Next, the IC chip l mounted in this manner and the copper polyimide wiring board 4 are electrically connected by bonder interconnect wires 6.
その後、Ｉ１０ピン７をセラミック配線基板３に取付け
るとともに、ＩＣチップｌを搭載した銅ポリイミド配線
基板４上をパッケージ８て封止する。更にセラミック配
線基板３の下面に、放熱フィン５を接着する。この放熱
フィン５には予め、台座付放熱ピン２の熱伝達部２ｂを
挿着させる挿着孔５ａを形成しておく。モして挿着時に
は、その挿着孔５ａ内に熱伝導率の高いシリコン樹脂等
を充填しておき、放熱フィン５と台座付放熱ピン２の熱
伝達部２ｂとを熱的に結合させる。これでマルチチップ
モジュールか完成する。Thereafter, the I10 pin 7 is attached to the ceramic wiring board 3, and the copper polyimide wiring board 4 on which the IC chip 1 is mounted is sealed with a package 8. Further, heat dissipation fins 5 are bonded to the lower surface of the ceramic wiring board 3. The heat radiation fin 5 is previously formed with an insertion hole 5a into which the heat transfer portion 2b of the heat radiation pin 2 with a base is inserted. At the time of insertion, the insertion hole 5a is filled with silicone resin or the like having high thermal conductivity to thermally couple the radiation fin 5 and the heat transfer portion 2b of the heat radiation pin 2 with a base. This completes the multi-chip module.
上記構造によれば、ＩＣチップ１から発生した熱は、台
座付放熱ピン２の台座部２ａから熱伝達部２ｂを通して
放熱フィン５へ直接伝達され、外部へ放出されることに
なる。According to the above structure, the heat generated from the IC chip 1 is directly transmitted from the pedestal part 2a of the pedestal-attached heat radiation pin 2 to the heat radiation fin 5 through the heat transfer part 2b, and is emitted to the outside.
上記台座付放熱ピン２ては、熱を伝達する部分、つまり
熱伝達部２ｂの断面積が大きくなる。例えば熱伝達部２
ｂの直径を２ｍｍとした場合、その断面積は３．１４■
朧２で、これは５×５履■サイズのＩＣチップｌの面積
の１２．５％に達する。しかも熱を放熱フィン５へ直接
伝達する為、熱伝達の効率は、従来の放熱用ヴイアな用
いた構造より格段に向上する。更に、ＩＣチップ１下方
の両配線基板３゜４の配線不可領域が、ピン状の熱伝達
部２ｂの一箇所たけとなる為、配線密度の低下は小さく
抑えられる。In the heat dissipating pin 2 with a base, the cross-sectional area of the portion that transfers heat, that is, the heat transfer portion 2b is large. For example, heat transfer part 2
If the diameter of b is 2mm, its cross-sectional area is 3.14■
In Oboro 2, this reaches 12.5% of the area of a 5×5 inch size IC chip. Furthermore, since the heat is directly transferred to the radiation fins 5, the efficiency of heat transfer is significantly improved compared to the conventional structure using heat radiation vias. Furthermore, since the area where wiring is not possible on both wiring boards 3.degree. 4 below the IC chip 1 becomes only one place for the pin-shaped heat transfer portion 2b, a decrease in wiring density can be suppressed to a small extent.
第２図は、上記実施例に示したマルチチップモジュール
の放熱特性（図中実線）と、第３図に示した従来のＩＣ
実装構造を有するマルチチップモジュールの放熱特性（
図中破線）とを示す図である。Figure 2 shows the heat dissipation characteristics of the multi-chip module shown in the above example (solid line in the figure) and the conventional IC shown in Figure 3.
Heat dissipation characteristics of multi-chip module with mounting structure (
FIG.
何れのモジュールも、７０Ｘ ７０■朧のセラミック配
線基板上に銅ポリイミド配線基板を形成し、５％５騰膳
の発熱用のチップを六個搭載したものである。又従来の
実装構造によるモジュールでは、直径１００ ｇｍの穴
の内壁に厚さ３０ルーの銅メツキをして成る放熱用ヴイ
アを、各ＩＣチップに対応させて１００本ずつ形成して
いる。そしてこれらのモジュールの放熱フィンに、５
ｍ／ｓｅｅの風を当てた状態て、モジュールへの供給電
力（Ｗ／モジュール）を変え、その際の各モジュールの
温度変化を測定した。Each module has a copper polyimide wiring board formed on a 70 x 70 mm ceramic wiring board, and six 5% 5-temperature heat generating chips are mounted thereon. In addition, in a module with a conventional mounting structure, 100 heat dissipation vias are formed by plating copper with a thickness of 30 Roux on the inner wall of a hole with a diameter of 100 gm, corresponding to each IC chip. And on the heat dissipation fins of these modules, 5
The power supplied to the module (W/module) was varied while applying wind of m/see, and the temperature change of each module at that time was measured.
この特性図に示される様に、本発明の実装構造によるモ
ジュールの温度変化は、従来の実装構造のものに比べて
明らかに小さく、よって放熱特性か向上したことか確認
される。As shown in this characteristic diagram, the temperature change of the module with the mounting structure of the present invention is clearly smaller than that of the conventional mounting structure, which confirms that the heat dissipation characteristics are improved.
尚１本発明のＩＣ実装構造は、熱伝導率の低い銅ポリイ
ミド配線基板を用いたマルチチップモジュールにおいて
特に効果を発揮するか、もちろん配線基板の種類を限定
するものではない。Note that the IC mounting structure of the present invention is particularly effective in a multi-chip module using a copper polyimide wiring board with low thermal conductivity, and of course is not limited to the type of wiring board.
又台座付放熱ピン２の材質は、熱伝導率の高いものてあ
ればよく、窒化アルミニウム以外に銅やアルミニウムで
もよい。Further, the material of the pedestal-attached heat dissipation pin 2 may be any material having high thermal conductivity, and may be copper or aluminum in addition to aluminum nitride.
〈発明の効果〉
以上述べた様に、台座付放熱ピンを設けた本発明のＩＣ
実装構造によれば、熱伝導率の低い銅ポリイミド配線基
板を用いた場合にも、充分な放熱効果が得られ、高発熱
のＩＣチップを使用することがてきる。しかも配線密度
の低下を小さく抑えることかできる。よって高性能のマ
ルチチップモジュールを実現し得る。<Effects of the Invention> As described above, the IC of the present invention provided with a heat dissipation pin with a pedestal
According to the mounting structure, a sufficient heat dissipation effect can be obtained even when a copper polyimide wiring board with low thermal conductivity is used, and an IC chip that generates a high amount of heat can be used. Moreover, the decrease in wiring density can be suppressed to a small level. Therefore, a high-performance multi-chip module can be realized.
更に１台座付放熱ピンは非常に安価に得られるものであ
り、モジュールへの組込みも容易である為、コストの増
加も抑えられる。Furthermore, the heat dissipation pin with one pedestal can be obtained at a very low cost and can be easily incorporated into a module, so that an increase in cost can be suppressed.
第１図は、本発明の実施例を示すマルチチップモジュー
ルの断面図、
第２図は、放熱特性を示す図、
第３図は、従来例を示すマルチチップモジュールの断面
図である。
１・・・ＩＣチップ、 ２・・・台座付放熱ピン。
２ａ・・・台座部、 ２ｂ・・・熱伝達部。
３・・・セラミック配線基板。
４・・・銅ポリイミド配線基板。
５・・・放熱フィン。FIG. 1 is a cross-sectional view of a multi-chip module showing an embodiment of the present invention, FIG. 2 is a view showing heat dissipation characteristics, and FIG. 3 is a cross-sectional view of a multi-chip module showing a conventional example. 1... IC chip, 2... Heat dissipation pin with pedestal. 2a... Pedestal part, 2b... Heat transfer part. 3...Ceramic wiring board. 4...Copper polyimide wiring board. 5... Heat dissipation fin.
Claims (1)
基板の下面に放熱フィンを取着したＩＣ実装構造におい
て、 ＩＣチップをダイボンドする台座部と、その台座部の下
面に突設され上記配線基板を貫通して放熱フィンに達す
るピン状の熱伝達部とより成る台座付放熱ピンを設けた
ことを特徴とするＩＣ実装構造。[Claims] In an IC mounting structure in which an IC chip is mounted on a wiring board and a heat dissipation fin is attached to the lower surface of the wiring board, there is provided a pedestal portion to which the IC chip is die-bonded, and a protrusion on the lower surface of the pedestal portion. An IC mounting structure characterized in that a heat dissipation pin with a pedestal is provided, the heat dissipation pin having a pedestal consisting of a pin-shaped heat transfer portion extending through the wiring board and reaching the heat dissipation fin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3183990A JPH03235356A (en) | 1990-02-13 | 1990-02-13 | Ic mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3183990A JPH03235356A (en) | 1990-02-13 | 1990-02-13 | Ic mounting structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03235356A true JPH03235356A (en) | 1991-10-21 |
Family
ID=12342226
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3183990A Pending JPH03235356A (en) | 1990-02-13 | 1990-02-13 | Ic mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03235356A (en) |
-
1990
- 1990-02-13 JP JP3183990A patent/JPH03235356A/en active Pending
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