JPH03235351A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To effectively reduce a fuse area so as to easily make an element finer without reducing the width and pitch of conductive wiring by providing a fuse formed of two or more conductive wiring layers through insulating films. CONSTITUTION:After a field oxide film 12 and CVD oxide film 13 are successively deposited on a semiconductor substrate 11, the first conductive wiring 14 of polysilicon is formed on the film 13. After the film 13 and wiring 14 are coated with the first PSG film (a silicon oxide film added with phosphorus) 15, the second conductive wiring 16 of polysilicon is formed on the film 15 and the second PSG film 17 is formed on the film 15 and wiring 16. Since the fuse thus formed has a double structure of the wiring 14 and wiring 16 through the film 15, the combination of the fuse per one place necessary for a plurality of layers becomes three or more and, when the wiring 14 is arranged immediately below the wiring 16, the fuse area can be compressed further. Therefore, this element can easily be made finer without reducing the width and pitch of the conductive wiring.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a semiconductor memory device.

(Prior Art) Semiconductor storage devices are becoming more highly integrated and larger in capacity, and the circuit configurations of storage devices are also becoming more and more complex. However, since there is a limit to the area of the entire semiconductor memory device,
There is a need to compress peripheral circuits such as redundant circuits, which are becoming increasingly complex, and to suppress increases in area. A redundant circuit is a circuit that replaces a defective memory cell with a spare memory cell, and this replacement is performed by cutting a fuse in the membrane.

That is, by cutting the fuse at the address corresponding to the defective memory cell, the defective memory cell is replaced with a spare word line/bit line, and the defective memory cell is replaced with the spare word line/bit line.

FIG. 8 is a perspective view of a conventional fuse. In this process, a conductive wiring 64 made of polysilicon is formed on a semiconductor substrate 61 via a field oxide film 62 and an oxide film made by CV'D method (hereinafter referred to as a CVD oxide film) 63, and the CVD oxide film is 63 and the conductive wiring 64 are covered with a phosphorous-doped silicon oxide film (hereinafter referred to as PSG film) 65.

In such a configuration, since the fuse has a single-layer structure, there are two combinations for each fuse in a plan view: when the fuse is cut and when the fuse is not cut.
That's right.

However, as the capacity of semiconductor memory devices increases, the number of Hines inevitably increases, and the fuse area also increases. Therefore, due to the limited area of the fuse, there is a limit to the reduction of this area with conventional fuses having a single layer structure. For this reason, it is conceivable to narrow the width and pitch of the conductive wiring in the fuse. However, when cutting conductive wiring using a laser, for example, the laser spot diameter and alignment accuracy must be taken into consideration, so there are limits to the width and pitch of the fuses, and this method naturally has its limits. Therefore, it is not easy to reduce the fuse area.

(Problems to be Solved by the Invention) As described above, in the past, there has been a problem that it is difficult to compress the fuse area as the degree of integration increases. The present invention provides a semiconductor memory device in which the area of a fuse can be effectively reduced without narrowing the width and pitch of conductive wiring, thereby facilitating miniaturization of elements.

[Structure of the Invention] (Means for Solving the Problem) In order to achieve the above object, the present invention includes a semiconductor substrate, a memory cell array formed on the substrate,
The present invention provides a semiconductor memory device having a spare memory cell array formed on this substrate and a fuse formed from two or more layers of conductive wiring on this substrate with an insulating film interposed therebetween.

Further, regarding the positions of the upper layer and lower layer conductive wiring in the fuse, the lower layer conductive wiring is preferably located directly below the upper layer conductive wiring.

Furthermore, it is effective to form the upper layer and lower layer conductive wiring with materials having different light absorption coefficients.

(Function) In the device configured as described above, since the fuse is composed of two or more layers of conductive wiring, the number of combinations of fuses at one location when viewed from a plurality of layers is three or more.

Further, by arranging the lower layer conductive wiring directly below the upper layer conductive wiring, the area of the fuse can be further reduced.

Furthermore, by forming the conductive wiring in the upper and lower layers with materials having different light absorption coefficients, it is possible to selectively cut the conductive wires in the upper or lower layer made of materials with different light absorption coefficients depending on the wavelength of the laser beam. can.

(Example) A first example of the present invention will be described below. FIG. 1 is a perspective view of a fuse in a redundant circuit in a first embodiment.

This is a field oxide film 12, C
A VD oxide film 13 is sequentially deposited, and a first conductive wiring 14 made of polysilicon is formed thereon. Next, the C
The VD oxide film 13 and the first conductive wiring 14 are covered with a first PSG film 15, and a second conductive wiring 16 made of silicon is formed on the first PSG film 1. Further, a second PSG film 17 is formed on the first PSG film 15 and the second conductive wiring 16.

In such a configuration, the fuse has a two-layer structure of the first conductive wiring 14 and the second conductive wiring 16 with the first PSG film 15 in between.

FIG. 2 is a sectional view showing a combination of fuses in this embodiment. That is, when the conductive wiring is not cut as shown in FIG. 2(a), that is, when the memory cell is not replaced with a spare memory cell, only the second conductive wiring 16 is cut as shown in FIG. 2(b). In other words, when the memory cell corresponding to the second conductive wiring 16 is replaced with a spare memory cell,
And as shown in FIG. 2(c), both the first conductive wiring 14 and the second conductive wiring 16 are cut, that is, the memory cells corresponding to the first conductive wiring 14 and the second conductive wiring 16 are cut. In some cases, the memory cell is replaced with a spare memory cell. therefore,
There are three combinations for each fuse.

Generally, in this embodiment, there are N+1 combinations of fuses having an N-layer structure per fuse location.
There are more combinations than the conventional single layer structure. Therefore, it is possible to effectively reduce the area of the fuse without narrowing the width of the conductive wiring and the width of the conductive wiring, thereby making it possible to miniaturize the device.

A second embodiment of the invention will be described below. FIG. 3 is a perspective view of the fuse of the redundant circuit in the second embodiment.

This is a field oxide film 22 on a semiconductor substrate 21, a C
A first conductive wiring 24 made of polysilicon is formed via the VD oxide film 23. Then, the CVD oxide film 23 and the first conductive wiring 24 are transferred to the first PSG film 2.
A second conductive wiring 26 made of a high melting point metal (for example, molybdenum silicide, tungsten silicide, etc.) having a different optical absorption coefficient from silicon is formed on the first PSG film 2 . Furthermore, the first PSG
A second PSG is formed on the film 25 and the second conductive wiring 26.
It has a structure in which a film 27 is formed.

In such a configuration, the fuse has a two-layer structure of the first conductive wiring 24 and the second conductive wiring 26 with the first PSG film 25 interposed therebetween.

Then, the first conductive wiring 24 and the second conductive wiring 26
Since the light absorption coefficients of the two layers are different, it is possible to selectively cut the upper layer or lower layer conductive wiring by adjusting the wavelength of the laser during laser irradiation. FIG. 4 is a sectional view showing a combination of fuses in this embodiment.

That is, when the conductive wiring is not cut (Fig. 4(a)
), when only the second conductive wiring 26 is cut (the fourth
(b)), when only the first conductive wiring 24 is cut (Fig. 4(c)), and when the first conductive wiring 24 and the second conductive wiring are cut! When both 126 and 126 are cut (Fig. 4 (
d)). Therefore, there are four combinations for each fuse.

In general, the combinations of fuses in the N-layer structure in this embodiment are 2N per fuse location, which is a far greater number of combinations than in the conventional single-layer structure. Therefore, it is possible to miniaturize the element without increasing the fuse area.

A third embodiment of the invention will be described below. FIG. 5 is a sectional view of a fuse in a redundant circuit in the third embodiment.

This is a field oxide film 32 on a semiconductor substrate 31, C
A first conductive wiring 34 is formed through the VD oxide film 33, and the CVD oxide film 33 and the first conductive wiring 3
4 with a first PSG film 35, and this first PSG film 3
A second conductive wiring 36 is formed on the film 5, and the -PSG
A second PSG is formed on the film 35 and the second conductive wiring 36.
A film 37 is formed, and a well layer 38 in an electrically floating state is formed in the semiconductor substrate 31 and below the first conductive wiring 34 and the second conductive wiring 36. ing.

Generally, when cutting conductive wiring with a laser, the heat generated in the conductive wiring also melts the surrounding insulating film, etc., and this melting brings the conductive wiring into electrical contact with the semiconductor substrate.
There is a risk of damaging the board and affecting the operation of the main unit. Therefore, by forming a well layer 38 in an electrically floating state directly under the first conductive wiring 34 and the second conductive wiring 36, it is possible to prevent the conductive wiring from coming into electrical contact with the semiconductor substrate. damage to the semiconductor substrate can be effectively prevented. Further, as in the above embodiments, it is possible to effectively reduce the fuse area and miniaturize the element.

A fourth embodiment of the present invention will be described below. FIG. 6 is a sectional view of a fuse in a redundant circuit in the fourth embodiment.

This is a field oxide film 42, C
An electrically floating polysilicon film 48 is formed via the VD oxide film 43. Then, a first PSG film 4 with a length of 5 is formed on this polysilicon film 48, and this first PSG film 4 is formed with a film length of 5.
A conductive wiring 44 is formed on the SG film 4, and the first conductive wiring 44 is covered with a second PsG film 47, and the 20th PSG film 4 is covered with a second PsG film 47. A second conductive wiring 46 is formed on the film 47, and a third PSGS conductive film is formed on the -th PSG film 45 and the second conductive wiring 46.

In such a configuration, as in the third embodiment, by forming a polysilicon film in an electrically floating state, the conductive wiring is prevented from being electrically connected to the semiconductor substrate, and the semiconductor Damage to the substrate can be effectively prevented. Similarly, it is possible to miniaturize the element without increasing the fuse area.

A fifth embodiment of the present invention will be described below. FIG. 7 is a sectional view of a fuse in a redundant circuit in the fifth embodiment.

This is a field oxide film 52 on a semiconductor substrate 51, C
A first conductive wiring 54 made of polysilicon is formed via the VD oxide film 53, and the CVD oxide film 53 and the first conductive wiring 54 are covered with a first PSG film 55.
A second conductive wiring 56 made of silicon is formed on the first PSG film 5, and a second PSG film 57 is formed on the -th PSG film 55 and the second conductive wiring 56. do. A groove 58 is provided between the fuses formed by the first conductive wiring 54 and the second conductive wiring 56.

In this embodiment, the heat generated in the conductive wiring by laser irradiation is dissipated from the groove, so that damage to the insulating film and the substrate can be effectively prevented. Note that this embodiment is similar to the above embodiment in that it is possible to miniaturize the element without increasing the fuse area.

[Effects of the Invention] As described above, according to the present invention, even if the degree of integration of semiconductor memory devices improves, the fuse can be compressed without narrowing the width or pitch of the conductive wiring, and the area of the fuse can be increased. This makes it possible to effectively prevent this and miniaturize elements.

[Brief explanation of drawings]

Fig. 1 is a perspective view of the fuses of the redundant circuit in the first embodiment, Fig. 2 is a sectional view showing the combination of fuses in the first embodiment, and Fig. 3 is a perspective view of the redundant circuit in the second embodiment. FIG. 4 is a sectional view showing the combination of fuses in the second embodiment; FIG. 5 is a sectional view of the fuses in the redundant circuit in the third embodiment;
The figure is a sectional view of a fuse in a redundant circuit in the fourth embodiment, FIG. 7 is a sectional view of a fuse in a redundant circuit in a fifth embodiment, and FIG. 8 is a perspective view of a conventional fuse. 11.21.31.41, 51.61... Semiconductor substrate, 12.22, 32.42.52.62...
...Field oxide film, 13.2L33.43.53.
83----CV D oxide film, 14.24.34.
44.54 ...First conductive wiring, 15
．． 25.35.45.55 -...-117) PS
G film, 16.28.3B, 46.56...
・Second conductive wiring, 17.27.37.47.57
--... Second PsG film, 38... Well layer, 48... Polysilicon film, 58... Groove.

Claims (3)

[Claims] (1) A semiconductor substrate, a memory cell array formed on this substrate, a spare memory cell array formed on the substrate, and two or more layers of conductive wiring on the substrate via an insulating film. What is claimed is: 1. A semiconductor memory device comprising a fuse formed therein. (2) A semiconductor substrate, a memory cell array formed on this substrate, a spare memory cell array formed on the substrate, and two or more layers of conductive wiring on the substrate via an insulating film. What is claimed is: 1. A semiconductor memory device, wherein the lower layer conductive wiring has a fuse located directly below the upper layer conductive wiring. (3) The semiconductor memory device according to claim 1 or 2, comprising conductive wiring formed of materials having different light absorption coefficients.