JPH03232195A - Nonvolatile semiconductor storage device capable of electronic erasure and write - Google Patents

Abstract

PURPOSE:To attain readout for a prescribed time at any time and to quicken the collation of data by disconnecting a cell for readout during the rewrite cycle from a write digit line and connecting the cell to a readout digit line. CONSTITUTION:The device is provided with a latch circuit 10 latching an output X0 of an X decoder, a level shift circuit 11 shifting a level of an output of the latch circuit 10, an N-channel MOS transistor (TR) (N-channel TR) 12 whose on/off is controlled by an output of the level shift circuit 11, an AND circuit 13 ANDing a readout signal RD and an output X0 of the X decoder, an inverter circuit 14 inverting the output of the latch circuit 10, and an AND circuit 15 ANDing an output of the inverter circuit and an output of the inverter circuit 14. Since the readout is attained at any time, the data verify time is reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an electrically erasable/writable nonvolatile semiconductor memory device, and particularly to an electrically erasable/writable nonvolatile semiconductor memory device that enables cell read operations during rewriting operations. Non-volatile semiconductor memory device 1 - Listen.

[Conventional technology]

In a conventional electrically erasable/programmable nonvolatile semiconductor memory device (hereinafter abbreviated as EEPROM), only one digit line is connected to one memory cell.

A plurality of memory cells are usually connected to these - digit lines.

When rewriting such a memory cell, first a control signal instructing a rewrite mode is input, a built-in timer is started, and address data is taken in, erased, and written in accordance with the control signal generated by the timer.

Next, in the address/data fetch cycle, the address and data to be rewritten are held in the address latch circuit and data launch circuit, respectively, and the address buffer and data huffer do not accept inputs thereafter until the rewriting is completed. In addition, in the erase cycle, the source and drain of the memory cell are grounded, and a high voltage for erasing/rewriting generated by a charge pump is applied to the gate.Furthermore, in the write cycle, the memory cell is connected to the A high voltage is applied to the digit line that is connected, and this high voltage is applied to the source. During the erase/write cycle described above, all input signals are not accepted, while the output terminals of the storage device are placed in a high impedance state. .

In the following text, to simplify the explanation,
The period including the erase cycle and the write cycle is defined as a rewrite cycle.

[Problem to be solved by the invention]

In the conventional EEPROM described above, one digit line is connected to one memory cell, and the voltage applied to the digit line differs between rewriting and reading, so rewriting is not performed during the rewriting cycle. It is not possible to read a memory cell connected to the same digit line as the cell being connected.

Therefore, in the conventional storage device, data cannot be read until all rewriting operations are completed, and there is a drawback that not only does it take time to collate data, but also reading cannot be performed for a fixed period of time.

An object of the present invention is to provide an EEFROM that not only speeds up such data collation but also allows reading for a fixed period of time at any time.

[Means to solve the problem]

The EEP'ROM of the present invention has a read digit line connected to the read side through a sense amplifier, a write digit line connected to the data input side, and connected to the read and write digit lines, respectively. a memory cell array formed by arranging a plurality of sets of read selection transistors, write selection transistors, and one memory cell connected to both the selection transistors in an array; and the both selection transistors and the memory cells of the memory cell array. For memory cells that are connected to each date and whose data is to be rewritten during the rewrite cycle, the read digit line is disconnected and connected to the write digit line to apply the necessary voltage for rewriting. The memory cell to be read includes a voltage switching control circuit that disconnects the write digit line, connects the read digit line, and applies a voltage necessary for reading.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a nonvolatile semiconductor memory device showing a first embodiment of the present invention.

As shown in FIG. 1, this embodiment includes an output buffer 1 for read data, an input buffer 2 for write data, a data latch 3 that holds the output of this manual buffer 2, and amplifies and outputs the read data. A sense amplifier 4 that supplies a buffer 1, an address buffer 5 that inputs a memory address, a column (Y) decoder 6 and a row (X) lever that decode the output of this address buffer 5, and this X decoder. 7 output X. , X+, etc. when reading.

A voltage switching control circuit 8 that determines the gate voltage during writing, and a selection transistor MOR1 for reading and writing.
A memory cell array 9 consisting of MIRI M, W, M, W and memory cells C0, C1, and a read digit line W.
LR and a write digit line WLW.

In particular, in this embodiment, a read digit line WLR is connected to the read side via the sense amplifier 4, a write digit line WLW is connected to the data input side, and these read and write digit lines WLR, WLW
read selection transistors M respectively connected to the readout selection transistors M; R
I MIR and write selection transistor M O, V
, M l 1% and memory cells Co, C, which are connected in series to both selection transistors, are arranged in an array, and both selection transistors of this memory cell array 9 M ORI M I R: M
as52M11, and signals (lines) RXo and WXo to each state of memory cells Co and C+.

GXo; connected via RX+, WX+, GXo,
Furthermore, for the memory cell C8 whose data is to be rewritten during the rewrite cycle, the read digit line WLR is disconnected and the write digit line WLW is connected to apply the necessary voltage for rewriting, while the memory cell C8 whose data is to be rewritten during the rewrite cycle For the cell C1, a voltage switching control circuit 8 disconnects the write digit line WLW and connects the read digit line WLR to provide the voltage necessary for reading.
It has

FIG. 2 is a specific circuit diagram of the voltage switching control circuit shown in FIG. 1.

As shown in FIG. 2, this voltage switching control circuit 8 is
A latch circuit 10 that holds the output X0 of the (Nch transistor) 12, read signals RD and
An AND circuit 13 that takes the AND of the derota output X0, an inverter circuit 14 that inverts the output of the latch circuit 10, an output of the inverter circuit 14, and an AND circuit 13.
and an AND circuit 15 that performs the logical product of the outputs of.

The output RXO of the AND circuit 15 is used as a gate signal for reading, and the output W of the level shift circuit 11
Xo becomes a gate signal for writing. Furthermore, the output GX of the Nch transistor 12 becomes a word line signal for the memory cell.

FIG. 3 is a waveform diagram of various signals in the voltage switching control circuit shown in FIGS. 1 and 2.

As shown in FIG. 3, the rewrite operation in this embodiment, that is, the rewrite cycle, includes an address/data capture cycle (not shown), an erase cycle, and a write cycle. It is assumed that cell C1 is to be read.

Next, the operation of the above-mentioned nonvolatile semiconductor memory device will be explained with reference to FIGS. 1 to 3.

First, memory cells C0, C, select transistor M01
1. The read digit line WLR and the write digit line WLW are connected via MORI M1112M11, respectively.
and is connected to. Now, in order to rewrite the memory cell C8 and read the memory cell C1 during the rewrite cycle, various signals shown in FIG. 3 are applied.

In the erase cycle, the gate GX of memory cell C8
High voltages v and P are applied to o. Here, memory cell C
If 1 is selected, the read voltage Ov of the read signal RD is applied to the gate (GX) of the memory cell C2, so the read digit line W changes depending on the state of the memory cell.
Changes in the current or voltage of LR are amplified by the sense amplifier 4, making reading possible.

Next, in a write cycle, the word line signal G X o applied to the gate of the memory cell Co becomes a ground potential, and Vl is applied to the drain through the write digit line WLW. At this time, Ov is applied to the gate (GXl) of the memory cell C1, and the readout line WLR is electrically isolated from the memory cell C8 because RX is "°0"'. ing.

Therefore, it is possible to write to the memory cell C0 and read from the memory cell C1 at the same time.

FIG. 4 is a specific circuit diagram of a voltage switching control circuit for explaining a second embodiment of the present invention.

As shown in FIG. 4, the voltage switching control circuit 8 in this embodiment eliminates the need to provide a write time margin, as in the first embodiment described above, and is an example for reliably checking data verification. The configuration is the output X of the X decoder 7. A latch circuit 10 holding the read signal R
An inverter circuit 17 that inverts D and a latch circuit 10
AND circuit 1 which takes the AND of the output of inverter 7
6, a level shift circuit 11 that performs level shifting based on the output of the AND circuit 16, and the level shift circuit 1.
an inverter circuit 18 that inverts the output of the inverter circuit 1; and a level shift circuit 1 that level-shifts the output of the inverter circuit 17.
9, and the output of this level shift) circuit 19 and the cell gate applied voltage V. It has an AND circuit 15 that performs a logical product of 0.

FIG. 5 is a waveform diagram of various signals in FIG. 4.

As shown in FIG. 5, in this embodiment, the cells that can be read during a rewrite cycle consisting of an erase cycle and a write cycle are only the cells that are currently being rewritten.

That is, in the first embodiment described above (FIG. 1),
M when rewriting. 1 is turned on and M. R is off, but M is on when reading. 1 turns off and MAR turns on, so
Reading becomes possible. On the other hand, the high voltage VPP for writing is M
. 1 is temporarily cut off, the high voltage is maintained without being discharged, and there is no need for recharging when rewriting is resumed.

Therefore, there is an advantage that the state of the currently rewritten cell can be read out during the rewriting operation, and loss of rewriting time due to reading can be suppressed to a small level.

As can be seen from the above two embodiments, this embodiment has two digit lines for reading and writing for one memory cell, a selection transistor for reading and writing, and a drive for these memory cells and selection transistors. It has a voltage switching control circuit that switches the voltage for memory cells to be rewritten, and connects the write digit line to apply the voltage necessary for rewriting to the memory cells to be rewritten. By connecting it to the read digit line and applying the necessary voltage for reading, it is possible to read from a memory cell other than the memory cell being written to, or to simultaneously read from the memory cell itself being written to. , simultaneous reading during a rewriting cycle can be realized.

〔Effect of the invention〕

As explained above, in the electrically erasable/writable nonvolatile semiconductor memory device of the present invention, cells to be rewritten are connected to a write digit line, and cells to be read during a rewrite cycle are connected to a write digit line. Since it is disconnected and connected to the read digit line, the cell can be read even during a rewrite cycle. Therefore, read operations can be performed at any time, which has the effect of shortening data verification time.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a nonvolatile semiconductor memory device showing a first embodiment of the present invention, FIG. 2 is a specific circuit diagram of the voltage switching control circuit shown in FIG. 1, and FIG. 3 is a circuit diagram of the voltage switching control circuit shown in FIG. Waveform diagram of various signals in the voltage switching control circuit shown in Fig. 4.
The figure is a specific circuit diagram of a voltage switching control circuit for explaining the second embodiment of the present invention, and FIG. 5 is a waveform diagram of various signals in FIG. 4. 1: Output buffer, 2: Input buffer, 3: Data latch, 4: Sense amplifier, 5: Address buffer, 6...
... Column decoder, 7... Row decoder, 8.
... Voltage switching control circuit, 9 ... Memory cell array, WLW ... Write digit line,
WLR・・・Reading digit line, Co, C+・
...Memory cell, Mow, Ml, %...
・Write selection transistor, MORIMIR...
...Reading selection transistor, X o , X 1
``'''' Row (X) decoder, WXO, WX+-=- write gate signal, GXo, GX,... write signal (word line signal), RD... read signal ,Vpp
...Write/erase high voltage, VCG...Cell gate applied voltage, 10...Latch circuit, 11
．． 19...Level shift circuit, 12...
・N-channel MO8) transistor, 13.15.16・
...AND circuit, 14,17°18...
inverter circuit. 1 Figure 2 Figure 3

Claims (1)

[Claims] A read digit line connected to the read side via a sense amplifier, a write digit line connected to the data input side, a read selection transistor and a write digit line connected to the read and write digit lines, respectively. a memory cell array comprising a plurality of sets of selection transistors and one memory cell connected to both selection transistors arranged in an array; connected to both selection transistors of the memory cell array and each gate of the memory cell; For memory cells whose data is to be rewritten during a rewrite cycle, the read digit line is disconnected and connected to the write digit line to apply the necessary voltage for rewriting. An electrically erasable/writable nonvolatile semiconductor memory device comprising a voltage switching control circuit that disconnects a write digit line, connects a read digit line, and supplies a voltage necessary for reading.