JPH03229381A - Data drive type computer - Google Patents

Abstract

PURPOSE:To carry on the operation of a data drive type computer with no discontinuation by replacing all packets with other ones in a queuing memory if a discontinuation state is detected by the presence or absence of ignition of all packets included in a circulating pipeline. CONSTITUTION:If a packet unstorable in a queuing memory 112 is produced, this packet is transmitted through the processing parts 101 - 103 set on a circulating pipeline and inputted again into the memory 112. Meanwhile it is decided whether or not an ignition processing part 101 applied the ignition processing to the packet, i.e., the packet is outputted from the memory 112 for proceeding of the data processing. If not, all packets are replaced with other ones in the memory 112. Thus the input packets are stored in the memory 112 without fail and the processing is carried on with no discontinuation.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data-driven computer that employs a method of driving processing based on data dependencies, and particularly relates to a data-driven computer that uses a method of driving processing based on data dependencies, and particularly in a cyclic pipeline configuration. This invention relates to a technique for avoiding execution stoppage caused by.

(Prior Art) Fig. 7 is a conceptual diagram of data processing in a data-driven computer, showing how two pieces of data are added. When the packet 81 with ``a'' added is given to the firing processing unit 87, the identifier field comparison unit 84 determines whether or not a packet with an identifier matching the identifier "a" of the packet 81 is stored in the waiting memory 85. Search for. In FIG. 7, a packet 82 having a value of "B" and an identifier of "a" is stored, so this packet 82 is read out from the waiting memory 85 and is sent to the data pair forming unit 82 along with the input packet 81. sent to.

The data pair forming unit 86 combines the packets 81 and 82 to form data 83, which is the value "A" and the value "B" with an identifier "a" added (this is called firing), and data processing. The operation A+B is executed in the unit 88. The operation result is given to a program memory (not shown) using an identifier as an address, and after being updated there, it is outputted to the outside or given again to the firing processing unit 87. A cyclic pipeline is constructed from these firing processing section 87, data processing section 88, and program memory.

In the example of FIG. 7, the same identifier as the input packet 81 “
a” was stored in the waiting memory 85, but if a packet with the same identifier as the input bucket) 81 is not stored in the waiting memory 85, the input packet 81 is stored in the waiting memory 85. Alignment memory 8
5 and waits until a packet with an identifier matching this is input.

In this way, the firing processing section 87 has the role of searching for packets to be operated on in the data-driven computer.

In normal data-driven computers, the bit width of an identifier is several tens of bits, so if a memory address is assigned to each identifier, the memory capacity will be enormous. Memory whose width is compressed (hereinafter referred to as hash) and used as a memory address (hereinafter referred to as hash memory)
is used.

FIG. 8 is a bitmap diagram showing the structure of an example of an input packet, and FIG. 9 is a block diagram showing the structure of an example of the hash memory.

The input packet contains 18-bit operand data OD to be operated on, a 7-bit operation code QC that indicates the content of the operation, a 1-bit processor selection bit PS, and I that indicates whether the input packet is a 2-input instruction or a 1-input instruction. Attributes such as the input order of the input data of the selection court SC1 that performs various selections, including the FC processing selection bit of the bit and the left and right data selection bits that indicate placement on the left or right of the calculation location (node) depending on the calculation order. 9 showing
It consists of 60 pins of a bit color/generation number DN and a 21-bit node number NN indicating the location where the calculation is to be performed. and processor selection bit ps
A 31-bit identifier is constructed from the color/generation number DN and the node number NN.

The hash memory 601 is accessed using the lower 9 bits of the node number NN as a hash address.
Read/write signal W/R that determines the read/write cycle
-H, and a cent reset signal S/π for updating write data and a presence bit PB indicating whether each address is valid or invalid. The write data stored is 1
It consists of 8-pin operand data OD, 9-bit color/generation number DN, 21-bit identifier of the remaining 12 bits of node number NN, and 1-bit processor selection bit PS, for a total of 40 bits. Additionally, the hash memory 601 has an additional 1-bit presence bit PB.
are stored, making a total of 1 word and 41 bits. The address space is 29=512, and the hash memory 601 has a size of 41 bits/word×512.

When a hash memory is used, when a hashed address (hereinafter referred to as a hash address) is accessed, there is a risk that a collision at the same address, a so-called hash collision, may occur.

In other words, a hashish collision is a hashish address that occurs when part of an identifier is used as a hashish address, and even if the hashish address matches data already stored in the hashish memory, the remaining identifiers do not match when data is accessed. This occurs because the address for storing data is already occupied.

[Problem to be solved by the invention]

Here, in a data-driven computer using the hash memory 601 as the waiting memory 85, FIG. Consider the case of executing the data flow graph shown in a).

To simplify the explanation, the following explanation assumes that the hash memory 601 is accessed using the lower two bits of the node number as the hash address, and has a capacity sufficient to store four packets (address space = 22 = 4). conduct.

As shown in Figure 10 (al), this data flow consists of 8 notes, and 6 input packets are processed. In particular, the second packet that is the left input of the node with number 0 is the node with number 7. The memory address for accessing the hash memory 601 is 4 memory addresses, and the node number of the data flow graph in FIG. 10(a) is the memory address shown in FIG. 10(b). When number 3 (01
The first packet, which is the left input of the node in 1), and the number 7 (
111), the lower two bits of the node number have the same value (=11), so the second packet is the same memory address "3" (=11) in the hash memory 601.
). If the second packet is stored in the hash memory 601 before the first packet, the second packet will wait for the third bucket, which is the right input of the node with number 7, but the third packet will be stored in the hash memory 601 before the first packet. It will not be generated unless nodes 5 and 6 are executed.

However, since the second packet is stored before the first packet and the meeting partner (third packet) is not generated, the second packet remains stored in the hash memory 601, and the first and second packets remain stored in the hash memory 601. Since there is a hash collision with the first packet, the first packet is not stored in the hash memory 601, and therefore the operation of the node numbered 3 is not executed, and the execution of the operation process ends up being stopped.

In this way, when executing a data flow graph larger than the capacity of the hash memory 601, multiple nodes use the same memory address for firing, so depending on the order of arrival of packets, hash collisions may occur, causing the execution of the data flow graph. There was a problem that the process would stop midway.

The present invention has been made to solve the above-mentioned problems, and because the packet is already stored in the hash memory, which is the waiting memory, the packet to be processed first is stored in the hash memory. It is detected by whether or not all packets in the cyclic pipeline are fired that the program execution is effectively stopped because the program cannot be stored in the waiting memory. The purpose of the present invention is to provide a data-driven computer which can store packets to be executed first in a waiting memory by exchanging all packets and can continuously execute operations without stopping them.

[Means to solve the problem]

The data-driven computer according to the present invention is provided with means for detecting whether or not an input packet cannot be stored in at least one waiting memory and has been fired before being waited for again via the cyclic pipeline. If the firing process is not performed during this time, it is determined that the data processing is not progressing, there is no packet output from the waiting memory for processing, and there is a risk that the data processing will be stopped. In this case, all the packets in the waiting memory are replaced by the replacement means.

[Effect]

In the present invention, when a packet that cannot be stored in the scheduling memory is generated, the packet passes through each processing unit on the cyclic pipeline and is inputted into the scheduling memory again.

During this period, the firing processing section detects whether or not the firing process has been performed, that is, whether or not the packet has been output from the waiting memory to proceed with data processing. , all packets in the waiting memory are replaced, so that the input packet is always stored in the waiting memory, and the execution of the process is no longer stopped.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram of a data-driven computer according to the present invention. In the figure, 101 is an ignition processing section. When a packet is input, the firing processing unit 101 stores the packet whose node number indicating the destination node and color/generation number match among the identifiers attached to the packet in the associative memory 112, which is a waiting memory. If there is a packet with a matching node number and color/generation number, merge the two packets and generate a firing packet, and if there is no packet with a matching node number and color/generation number. In this case, it has a function of storing the input packet in the associative memory 112.

The firing packet fired by the firing processing section 101 is given to the arithmetic processing section 102, which performs arithmetic processing according to the instruction code attached to the firing packet. The packet resulting from the calculation is given to the program memory 103, the contents of the program memory 103 are read using the node number attached to the packet as an input address, and the node number and instruction code of the identifier are updated based on the read contents.

As described above, the firing processing section 101, the arithmetic processing section 102, and the program memory 103 have a one-stage pipeline configuration for the firing processing section 101, and a multi-stage pipeline configuration for the others, and have a cyclic pipeline configuration as a whole.

FIG. 2 is a diagram showing the data structure of a packet. The packet has a total of 81 bits, and from the highest order, 18-bit operand data 20D2, operand data 1001
．． 7-bit operation code 0C 11-bit mark bit MB, 1-bit through bit TH1 7-bit selection bit including left/right data selection bit SL and FC processing selection bit 5C 119-bit color/
It consists of a generation number DN and a 21-bit node number NN. Here, bit MB is the firing processing unit 10.
This is to indicate a target packet for detecting whether firing processing has been performed from the time it is output from 1 to the time it is next input. On this circular pipeline,
A packet with the data structure shown in the figure is moving. however,
From the output of the arithmetic processing unit 102 to the input of the firing processing unit 101, the packet does not have operand data 20D2 and has 6
Although it has a 3-bit configuration, after processing in the firing processing unit 101, the two operand data of the packet before firing are 0.
01.002 to operand data 10D1 and operand data 2 according to the respective left/right data selection bits SL.
It is sent to the arithmetic processing unit 102 in a state stored as 0D2. In the arithmetic processing unit 102, two operand data 0
01, the operation result of OD2 is operand data 10D
1 and returns to its original 63-bit configuration.

However, even if the packet is between the firing processing unit 101 and the arithmetic processing unit 102, if it is a one-operand operation packet or a through packet that passes through the cyclic pipeline because the associative memory 112 is full, no operand data 20D2 is stored. Not retained.

Furthermore, the through packet output from the firing processing section 101 is processed by the arithmetic processing section 102 and the program memory 103.
The firing processing unit 1 retains the unprocessed information and fires it again.
Come back to 01.

Next, the internal configuration of the firing processing section 101 will be explained.

A data latch 111 latches a packet input to the firing processing unit 101. The input packet is latched at the timing when the signal CO from the previous stage of the wave line is "H". Among the latched packets, India via) MB, F
C processing selection bit, left/right data selection bit) SL is output to the control unit 118. In addition, each data of the input packet except MB and through bit TFI has the identifier 3.
Associative memory 11 divided into 0 bit and other 32 bits
2 is input. Similarly mark bit question and through pit 1-T
Each data of the input packet except H is sent to the data pair former 1.
16 is also input.

FIG. 3 is a block diagram showing the structure of the associative memo January 12. In the figure, 201 is an associative memory (hereinafter referred to as CAM) that searches for data that matches the 30-bit identifier included in the packet node input via the data latch 111, and has a capacity of 31 bits x 32 addresses. There is. One bit of the CAM 201 is a presence bit PB for determining the validity of stored data.
It is used for storing. The CAM 201 is provided with a match/mismatch signal line (hereinafter referred to as a match line) for each address, and a given 30-bit identifier and C
"H" is output only for the match line whose address matches the identifier stored in the AM 201. Also CAM
The presence bit P is sent to 201 via the selector 205.
A set signal S/π for updating B is given, and a read/write signal W/π determines a read/write cycle.
is given. The selector 205 has a reference voltage “H” at one end.
However, a cent signal S/π is applied to the other terminal, and a read/write signal W/π is applied to the switching terminal. The signal S/π is selected. That is, when the read cycle W/π=4L'', the presence pitch)P
Since it is necessary to search only the address with B=1, it is necessary to always set the bit corresponding to the presence bit PB of the search data to 1 and update the presence focus PB only when the write cycle W/π = “H”. This selector 205 is used for this purpose.

Further, the CAM 201 outputs a judgment signal indicating whether the identifiers match or do not match on the 32-bit match line, and also outputs the presence bit PB of each address to the empty address detector 203, where the presence bit P
An address in which no valid data is stored is detected from B.

The empty address detector 203 outputs a 32-bit detection signal indicating an empty address to one end of the address selector 206 and the address selector 207, and also indicates that there is no empty address in the CAM 20.
When packets are stored in all addresses of 1, a full signal FL indicating this is output to the control unit 118.

Note that the detection signal indicating an empty address is 3 of the CAM 201.
It is a 32-bit output corresponding to two addresses, and only the bit of the empty address is "H". The address selectors 206 and 207 are also given a determination signal from the match line.

The eviction address generator 204 generates eviction addresses for outputting all packets stored in the associative memory 112. The expulsion address generator 204 is the controller 11
At the timing of the signal Td output from 8, a eviction address representing each of the 32 addresses is generated in order and given to address selectors 206 and 207.

The address selector 206 generates a eviction signal according to the read/write signal W/π applied to the switching terminal and the eviction signal output from the control unit 118 to output all packets in the associative memo January 12. When the eviction signal is "H", the eviction address is set, and when the eviction signal is "L", the read cycle W is set.
When /π = “L”, select the fixed signal “0”, and when the eviction signal is “L” and write cycle W/R = “H”, select the detection signal of the empty address detector 203. do.

The eviction signal is also output to an output selector 117, which will be described later.

The address selector 207 outputs a eviction signal according to the read/write signal W/R applied to the switching terminal and the eviction signal inputted by the control unit 118 for outputting all packets in the associative memory 112. When it is “H”, the eviction address is read, and when the eviction signal is “L”, the read cycle is W.
When /π=“L”, the judgment signal and the expulsion signal are “
When the write cycle W/π=“H”, the detection signal of the empty address detector 203 is selected.

The RA gate 202 receives operand data 00118 bits,
It stores a total of 32 bits, including an operation code OC7 bit and a selection code SC7 bit, and has a capacity of 32 bits x 32 addresses. In the read cycle, 32 bits of address data input from the address selector 207 are output to the data latch 113 together with 30 bits of data from the CAM 201. That is, a 32-bit judgment signal output from the CAM 201 and a total of 94 bits of data are output to the data latch 113. On the other hand, in the write cycle, the data latch 1
The contents of the input packet given from 11 are stored.

Further, in the write cycle, when the CAM 201 hits or when the packet is evicted by control of the ejection signal, the presence bit PB of the output address is cleared.

In FIG. 1, 113 is a data latch, and the 92-bit data output from the associative memory 112 is applied to the signal TI.
= latched at “H”. Of the 94 bits, 32 bits of the judgment signal are used for hit detection, and the other 62 bits are output to the output selector 117. Operand data 1
The 18 bits of 0D1 are also output to data latch 115 at the same time.

The hit detector 114 monitors the inverted signals of the 32 munch lines from the CAM 201, and if even 1 bit among them rises to "H", the
201), the hit signal old T is sent to the control unit 1.
Give to 18.

The data pair generator 116 outputs the operand data 10 outputted from the associative memory 12 via the data latch 113.
01 is input to one end, and the 63-bit input packet data from the data latch 111 is applied to the other end. The two data are then merged to form an 81-bit packet containing two operand data 001 and 002. At this time, there are cases where the order of the operands is important, such as the subtraction instruction in binary operations, so
The selected operand data and the input operand data must be correctly placed as left or right operands.

FIG. 4 is a block diagram showing the configuration of the data pair former 116. The data pair forming unit 116 consists of two data selectors 501 and 502, and each switching terminal is given a selector-controlled '4B signal L/π that indicates its status using the left/right data selection bit SL of the input packet. . A terminal of data selector 501 and B of data selector 502
The operand data of the input packet from the data latch 111 is given to each terminal, and the data selector 5
The operand data stored from the data latch 115 is given to the B terminal of 01 and the A terminal of the data selector 502.

and the left/right data selection bit S of the input packet
L is input as the selector control signal L/π, and when L/π is “1”, the operand data given to the A terminal of each data selector 501 and 502 is input, and when L/π is “0”, are the respective data selectors 501 and 502
The operand data given to the B terminal of is selected, the selected output from data selector 501 becomes the left operand (operand data 1), the selected output from data selector 502 becomes the right operand (operand data 2), The data other than the operand data of the packet is merged with the other data and is input to the output selector 117. When the input packet is a one-operand instruction, or when the associative memory 112 is full and the input packet is output as is, the selector control signal L/π is used to select the left/right data of the input packet. 1
Since the selector control signal L/π is forced to "1" by 18, the input packet is output as is.

The output selector 117 selects whether to output a packet ejected from the associative memo January 12, a fired packet, an input packet containing a one-operand instruction, or a through packet. This selection is made by the control unit 1.
The selection is made according to the eviction signal given from 18. This eviction signal becomes "H" when the control unit 118 detects that all packets in the cyclic pipeline are not fired.

The control unit 118 includes two registers, namely a mark counter 1
19 and an firing flag register 120 are provided.

The mark counter 119 is a register that counts the number of packets whose mark bit MB is "1" (hereinafter referred to as "marked packets") on the cyclic pipeline, and the firing flag register 120 is a register that counts the number of packets whose mark bit MB is "1" (hereinafter referred to as "marked packets"). If firing occurs after the output of , "1" is held, and if no firing occurs, "O" is held. The control unit 118 also controls the input selection signal FC (which is determined by the mark bit MB, the left/right selection bit/node SL of the input packet, and the FC processing selection bit indicating whether the input packet is a 2-operand instruction or a 1-operand instruction). Two input commands FC=1.1 input command FC=0), a hit signal old T and a full signal PL are given. In addition, a signal CO indicating that the processing at the previous stage of the pipeline has been completed and the output data of the previous stage has been latched into the data latch 111, and the processing at the next stage of the pipeline has been completed and the result packet of the firing processing unit 101 is output to the next stage. A permission signal (■) is given indicating that it is OK to do so. These input signals are judged to generate an eviction signal D, a read/write signal W/R, a set signal S/π, a selector control signal /R to be output to the data pair former 116, and a through bit T)l of the output packet. It outputs a hit mark bit MB, a data output signal CI, and a data input permission signal ■.

Also, a timing signal Tl that determines the timing of processing,
T2. It also outputs Td.

Next, the operation of the firing processing section 101 of the data-driven computer of the present invention configured as described above will be explained. It is assumed that the associative memory 112 stores a plurality of packets waiting for data pairs. FIG. 5 is a flowchart illustrating the general operation of the firing processing section 101.

When a packet is input, the mark bit MB of the input packet is input to the control unit 118, and it is determined whether the mark bit MB is "1" (Sl). If the mark bit MB is "B", this packet is the previous packet. When the processing was performed by the firing processing unit 101, there was no packet whose destination node number NN and color/generation number DN matched in the associative memory 112, but since the associative memory 112 was full, the input packet is output as a through packet. Therefore, the control unit 118 uses the mark counter 119 to check whether all packets in the cyclic pipeline have not fired since this packet was output from the firing processing unit 101 last time. and needs to be detected by the firing flag register 120. First, a marked packet is input to the firing processing unit 101, and since the number of marked packets has decreased by one from the cyclic pipeline, the marking counter 119 is decremented (S2). Next, the content of the mark counter 119 is checked (S3).If the mark counter 119 is other than "0", firing occurs since the input marked packet was output last time, and once the associative memo January 12 became empty, but due to new storage in the associative memo January 12, the associative memo January 12 became full again, and a new through packet was generated and marked as a packet. In other words, since this indicates that there was a packet that fired after the output of this marked packet, it cannot be determined that all packets on the cyclic pipeline have not fired, and the process moves to normal processing S6. 119 is “0”
”, further check the contents of the firing flag (
S4). If the firing flag is “0”, that is, if firing has not occurred since the last marked packet output, it means that firing has not occurred since the input marked packet was output from the firing processing unit 101 last time. It shows.

That is, when this input packet was output from the firing processing unit 101 last time, it is detected that all the packets existing on the circular pipeline passed through the firing processing unit 101 without firing, and the associative memo January Output all packets stored in 12 onto the cyclic pipeline (
S5). The output of the packet stored in the associative memory 112 is first outputted to the associative memory 11 by setting the eviction signal to "H".
The output from 2 is outputted by the output selector 117. After that, the content addressable memory 11 is activated by the timing signal Td.
Address selector 206 sequentially selects all addresses within 2,
207 and outputs packets of all addresses to the data latch 113. Thereafter, packets of all addresses are sequentially outputted via the output selector 117 in accordance with the input permission signal (2) of the next stage of the pipeline. After all putty/nods in the associative memo January 12 are output, normal input packets are processed from step S6 onwards.

Based on the old T signal from the hit detector, it is determined whether there is a packet with the same identifier as the input packet in the associative memory 112 (S6). Old T signal is “1”
, that is, if there is a packet with the same identifier as that of the large Kapake Nodo in the associative memo January 12, the control unit 1
Please set the firing flag in 18 to "l" (5IO),
The input packet and the data in the associative memo January 12 are merged, and the firing packet is output via the output selector 117 (Sll). On the other hand, if you do not give a hint, associative memo 1
It is determined whether the associative memory 112 is full based on the full signal FL from month 12 (S7). Associative memory 112
1 if is not full, the input packet is in content addressable memory 11
If the associative memo January 12 stored in 2 (S14) is full, it will be output as a through packet, but at this time a judgment is made as to whether or not it will be a marked packet (S14).
8, S9).

First, if the currently marked packet is not on the circular pipeline and is the first through packet, that is, the marked counter 1
If 19 is "O", the process advances to step S12, where the firing flag register 120 is reset, the mark counter 119 is incremented, the through bit TH and the mark bit MB are set, and the packet is output as a marked packet. If the mark counter 119 is other than 0'', that is, a marked packet has already been output to the circular pipeline, the firing flag is checked in step S9 to determine whether firing has occurred since the last marked packet was output. If firing is not occurring, set the through pit T)I and output.If firing is occurring, firing occurs after the last marked packet is output, and then again. , it is thought that the associative memo January 12 is full and a through packet is generated, so the mark counter 1
19 is incremented, the firing flag is reset, the through pit TO and mark bit MB are set, and the packet is output as a marked packet.

FIG. 6 is a timing chart explaining the operation cycle of the device of the present invention. In particular, when it is detected that all packets on the circular pipeline have passed through the firing processing unit 101 without firing, It is a timing chart when all packets are output. An input packet is launched into the data latch 111 at the timing when the signal CO is "H". When the control unit 118 detects from the data of this input packet and the information of the mark counter 119 and firing flag register 120 in the control unit 118 that all packets on the cyclic pipeline have passed through the firing processing unit 101 without firing, First, the eviction signal becomes "H". As a result, the output from the content addressable memory 112 is selected as the output from the output selector 117. Initially, the signal W/π is "L", which is a read cycle. After that, a signal Td is sent from the control unit 118 to the eviction address generator 20 of the associative memory 112.
4, one eviction address is generated at the timing when the signal Td is "H", and the address selector 206.2
Given on 07. The eviction signal is also input to the address selector, and the eviction address is thereby selected. After a delay from generation of the evicted address to address selection and determination of the output from the associative memory 112, the signal Tl
is set to "H", and the output from the associative memory 112 is latched into the data latch 113. After the data is launched, the signal W/π becomes "H" and the presence bit PB of the output address is reset. Further, when both the "H" of the timing signal T1 and the input of the data input permission signal (■) from the next stage of the pipeline are confirmed, the data output signal C1 is output, and the packet latched in the data latch 113 is transferred to the output selector 117. Output via . By repeating this operation 32 times, the associative memory 112
All packets within are output onto the cyclic pipeline. Thereafter, the process is completed through a read cycle, a processing cycle, and a write cycle. When the processing is completed, an input permission signal (■) is output to the previous stage of the pipeline, prompting input of the next packet.

In the above-described embodiment, an associative memo January 12, which uses the entire identifier of the packet as a key to perform the waiting operation, was used as the operand waiting memory, but the present invention is not limited to this, and part of the identifier, Alternatively, the packet is stored in the waiting memory using a number generated by some calculation from the identifier as an address, and is fired by comparing all identifiers to see if it is a packet that should be fired only for packets with the same address. The configuration may be such that the hash memory that determines whether or not the request is made is a waiting memory.

In addition, the detection that a packet that has passed through the waiting memory has returned to the waiting memory is achieved by marking the packet, but it is possible to detect that a packet that has passed through the waiting memory has returned to the waiting memory. The halted state of execution may be detected by detecting this.

Furthermore, as a replacement of all packets in the waiting memory,
Although an example has been shown in which packets are allowed to be input after all packets have been output, switching can also be achieved by outputting one packet and then inputting one packet.

〔Effect of the invention〕

As explained above, according to the present invention, in order to detect that a packet to be executed first cannot be stored in the waiting memory and the data processing is stopped, the packet that has passed through the waiting memory is 7. It is detected whether or not the firing process has been performed before the computer returns to the waiting memory again. If the firing process has not been performed, the situation has not changed at all and there is a possibility that the system will be in a stopped state. , all the packets in the waiting memory are replaced, and by repeating the detection of the stop state and the replacement of all the packets in the waiting memory, the packet to be executed first will be stored in the waiting memory at some point, and the execution will proceed. This provides an equivalent effect of avoiding stoppage.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data-driven computer according to the present invention, FIG. 2 is a diagram showing a packet configuration operating on the data-driven computer according to the present invention, and FIG. 3 is a diagram showing the configuration of a data-driven computer according to the present invention. FIG. 4 is a block diagram showing the structure of the memory, FIG. 4 is a block diagram showing the structure of the data pair generator of the data-driven computer of the present invention, FIG. 5 is a flowchart showing the process flow of the present invention, and FIG. FIG. 7 is a conceptual diagram of processing in a conventional data-driven computer; FIG. 8 is a bitmap diagram showing the structure of an example of a packet; FIG. Block diagram showing the configuration of an example of hash memory, FIG. 10(a)
is a diagram showing an example of a data flow graph, FIG. 10(b)
is a diagram showing the relationship between memory addresses and node numbers in a conventional example. 101... Ignition processing unit 102... ALU 10
3...Program memory 112...Associative memory
117... Output selector 118... Control section 20
4... Eviction address generator In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] (1) storing a packet having identification information and data including at least an instruction code indicating the content of the operation to be executed and a destination node number indicating the location of the next instruction to be executed;
A firing processing unit that includes one or more waiting memories for detecting two packets whose destination node numbers match at least the stored packet and the input packet, and performs firing processing to combine the two matched packets. In a data-driven computer that has a cyclic pipeline structure with multiple processing units including means for detecting whether or not all packets in the cyclic pipeline have been fired in the firing processing unit before being inputted to the waiting memory that were not stored again through the firing processing unit; 1. A data-driven computer comprising: means for exchanging all the contents of the waiting memory at the time of the appointment.