JPH0322711A - A/d converter - Google Patents

Abstract

PURPOSE:To reduce the size and power consumption of a chip while maintaining a fast speed with an all parallel type by putting latch circuits and AND circuits in composite comparators together by (n-m) bits as to low-order (n-m) bits and generating a digital signal consisting of (n-m) bits. CONSTITUTION:An (n)-bit digital output is divided into high-order (m) bits and low-order (n-m) bits. The high-order (m) bits are converted into digital data by using (2<m>-1) composite comparators F1-F(2<m>-1) as usual, but the low-order (n-m) bits are converted into (n-m)-bit digital data by putting the latch circuits 14 and AND circuits 15 in the composite comparators together by (n-m) bits. Latch circuits 14 and AND circuits 15 are reduced in number and the substantially necessary number of elements is reduced to half. Consequently, the high speed is maintained with the all parallel type and the chip area and power consumption are reducible.

Description

[Detailed Description of the Invention] [Summary] Regarding an A/D converter, the present invention aims to provide an A/D converter that is fully parallel and capable of maintaining high speed while reducing the size of the chip and reducing power consumption. The purpose is to provide a fully parallel A/D converter with a resolution of n bits, which converts n bits of digital output into upper m bits and lower (m) bits.
(n-m) bits, (2I1-1) comparators are provided in parallel at the input stage, and a reference voltage that divides the input voltage range into 2n equal parts is divided and supplied to these comparators. The upper m bits are used as a reference value for comparison of each comparator with respect to the analog input, and the upper m bits are the voltage at the point where the reference voltage is divided by 2n and the analog input, including at least a latch circuit and an AND circuit in addition to the comparator (2''' -1) The comparison result is sent to an encoder to generate a digital signal for m bits, and the lower (nm) bits are processed by a latch circuit and an AND signal in the composite comparison means. The circuit (n
- m) bits, the comparator outputs the comparison results for each predetermined column corresponding to (n-m) bits, and sends the comparison results for each column to the encoder through the summarized latch circuit and AND circuit. It is configured to generate a digital signal of (n−m) bits.

[Industrial application field]

The present invention relates to an object inspection device, and in particular, a parallel type A
/D converter.

In recent years, A/D converters for video signals used in digital VTRs, digital TVs, etc. have become smaller and consume less power as VTRs and TV sets become smaller and consume less power. Demand for electrification is increasing.

In order to meet these demands, in recent years, high-speed A/D converters for image signal processing (1-chip) have been developed.
d video analog-to-digital
converter) are being developed one after another.

The A/D conversion method is parallel type (parallel type).
yp-e) and successive approximation form (successive ap
There are various types such as proximation type, but the parallel type is the most advantageous in terms of conversion speed.

? 2. Description of the Related Art A conventional A/D converter used for video is, for example, the one shown in FIG. 3, which is called a fully parallel type. In the same figure, V■, vl? is a reference voltage that determines the analog input voltage range, VIN is an analog input, and the one shown in this figure is an example with an 8-bit resolution. Also, R. ~Rzss is the input voltage range 2n=
In order to generate a voltage divided into 256 equal parts, the reference voltage V Rl%
VR? The reference resistance, F, is divided to create a reference value for comparison.
1~F255 are analog input V4 and reference resistance R1~R
The composite comparator Fl-F255 is a composite comparator that compares each reference voltage divided by 2 and S, and the composite comparator Fl-F255 includes a comparator, a latch circuit, an AND circuit, and the like. Therefore, in this conventional example, in order to obtain 8-bit resolution, (2' - 1) = 255 composite comparators F1 to F255 are arranged in 8 columns, and each composite comparator F1 to F255 has an input voltage VIN and a reference voltage. VRII% V RT is divided into 2l1 equal parts and compared with the reference values for comparison, and the results are shown on 8 lines 1.
The signal is inputted to the encoder 2 through the encoder 2 and converted into a binary code 2, and the digital signal is taken out from the output buffer 3.

That is, analog input v1.4 and reference voltage VRII,
The voltage level obtained by dividing the VRT into two equal parts is simultaneously compared by each composite comparator F1 to F255 at the same time as the analog signal is applied, and a digital signal is generated based on the comparison result of "H" and "L".

[Problem to be solved by the invention]

However, in such a conventional A/D converter, for example, when decomposing an analog input signal into an n-bit digital signal, (2n-1) comparators are prepared. The analog input signal and the voltage level obtained by dividing the reference voltage into 2n equal parts are simultaneously compared in each comparator to instantly determine which voltage level the input signal is at, so high-speed conversion is possible. Although it is possible,
In order to obtain n-bit resolution, it is necessary to obtain (2'-1)
Since multiple composite comparators are required, the chip area
There was a problem that power consumption was large.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an A/D converter that is fully parallel and capable of maintaining high speed while reducing the size of the chip and reducing power consumption.

[Means to solve the problem]

In order to achieve the above object, the A/D converter according to the present invention is a fully parallel A/D converter having an n-bit resolution, and converts n bits of digital output into upper m bits, lower m bits, lower (n-
m) Divide into bits, install (2'1> comparators in parallel in the input stage, and divide and supply the reference voltage that divides the input voltage range into 2n equal parts to these comparators. The reference value for comparison of each comparator is the upper m bits,
The voltage at the point where the reference voltage is divided by 2n and the analog input are compared by <2'-1) composite comparison means including at least a latch circuit and an AND circuit in addition to the comparator, and the comparison result is sent to the encoder. The lower (n-m) bits combine the latch circuits and AND circuits in the composite comparison means for (n-m) bits, and the comparator generates (n-m) digital signals. A comparison result is output for each predetermined column corresponding to the bit, and the comparison result for each column is sent to the encoder through the latch circuit and AND circuit to generate a digital signal for (n-m) bits. It is composed of

[Effect]

In the present invention, of the n-bit digital output, the upper m
For bits, the voltage at the point where the reference voltage is divided by 2n and the analog input are compared by (2'-1) composite comparing means and the information is sent to the encoder.
A digital signal is generated. Regarding the lower (n-m) bits, the latch circuit and AND circuit in the composite comparison means are combined for (n-m) bits, and the (n-m) bits are collected from the comparator.
−m) A digital signal for ゜(nm) bits is generated by outputting a comparison result for each predetermined column corresponding to bits and sending the comparison result for each column to the encoder through the latch circuit and AND circuit. Ru.

Therefore, the number of latch circuits and AND circuits, especially in the composite comparison means, is reduced, and chip area and power consumption are reduced.

? Explanation of Principle] First, the principle of the present invention will be explained. FIG. 1 is a diagram showing the configuration of an A/D converter according to the present invention, and in this diagram, V■, Vll, and VI+4 are the same as in the conventional example. Rx is a reference resistor for dividing the reference voltage Vll1""Vll by 2n, and there are 2n-2 of them. In the figure, only the highest and lowest positions are labeled, and the middle parts are omitted. The A/D converter shown in the figure has a digital resolution of n bits, of which the upper m bits divide the voltage at the point where the reference voltage Vllll to VRT is divided by 2n1 and the analog input VIM (2'-1 ) composite comparators (corresponding to composite comparison means) Fl-F (2n-1), the comparison results are sent to the encoder 11, and the encoder l1 converts them into m-bit binary code digital signals. The generated digital signal is taken out to the outside through the output bath sofa 12.

In this case, the composite comparators F1 to F(2n-1) each include a comparator, a latch circuit, and an AND circuit, and as an example, the composite comparator F1 includes a comparator 13,
It includes a latch circuit 14 and an AND circuit 15. The same applies to the other internal elements of the composite comparator, but the numbering is omitted to avoid complication in the drawings.

The comparator l3 compares the corresponding reference voltage with the analog input and outputs a digital signal of "H" or "L" depending on the comparison result, and the latch circuit 14 performs a comparison judgment to avoid the influence of jitter, for example. The AND circuit 15 operates to immediately latch the result, and AND circuit 15 performs an AND logic on its own data and its higher-order data and sends it to the encoder 1l, where it is converted into n-bit digital data.

Although the AND circuit 15 calculates the logical product in the figure by ANDing its own data and its higher-order data (the same applies to other AND circuits), this is just one example, and other methods may be used.

Furthermore, conversion of lower (nm) bins is performed as follows. First, the reference voltage V. -VII
The output of the reference resistor 2l1 at the point where T is divided into 2n is connected to each group of {2 ``-'' − 1} 2n resistors in a row, and the output line of each group is connected to the resistor Rc. is connected to a predetermined potential ■7 through
~A (2n-” − 1). Note that the ratio t
QSQ (=“H” or “L”) for each row of 2 (2n-1)
”).Here, if the current flowing through the comparator is IC, the voltage of the latch circuits L1-L is output, so the latch circuits iL1-L(2'-"- 1)
The voltage received by is converted into digital data by
1-1), take the logic, and encoder 11 (n-m)
output buffer 12
Extract the digital signal from.

Therefore, the top m bisoto is (2n-1) as before
The data is converted into digital data using multiple composite comparators, but for the lower (nm) bits, the latch circuit and AND circuit within the composite comparator are combined into (nm) bits. It will be converted into bit digital data. Therefore, while maintaining high speed, which is a feature of the fully parallel type, the comparator remains the same as before, but the number of latch circuits and AND circuits has been significantly reduced, making it virtually unnecessary. Since the number of elements is halved (specific values are detailed in the examples), it is possible to reduce the chip area and reduce power consumption, and as a result, yields are improved, IC packages are made smaller, and they are significantly It is possible to achieve significant cost reductions.

〔Example〕

FIG. 2 is a diagram showing an embodiment of the present invention based on the above principle, and this embodiment is an example of an A/D converter having a resolution of 8 bits (n=8). In this embodiment, the upper and lower divisions are 2 bits and 6 bits, respectively (i.e.,
m=2, nm=6), upper composite comparator Fl-
Three F3s (=221) perform the above 2-bit conversion. On the other hand, the number of lower comparators C1 to C252 is 252, and the number of comparators C1 to C252 is 63 (= 2 "-"
-1) are arranged in 4 rows, and each row has its output. , Q is divided into 63 parts and put together into 4 parts, each of which is divided into latch circuits Ll-L63 and AND circuits A1 to A6.
3 and is connected to a predetermined potential v through a resistor Rc.
Connected to 1. And these comparators C1 to C25
2, latch circuits L1 to L63, AND circuits A1 to A6
3 and resistor Rc, the lower 6 bits are converted using the same logic as described in the principle of the invention above. Note that the encoder l1 and the output buffer l2 have similar structures and are given the same numbers.

Here, a comparison with a conventional A/D converter will be made.

First, in the case of 8-bit resolution, in the conventional configuration shown in FIG. 3, the composite comparator 7! l<(2' - 1)
= 255 pieces are required. Therefore, in order to compare the number of constituent elements of a composite comparator, if the breakdown of the number of elements is set as comparator = X latch circuit = Y and circuit = 2, in the conventional structure, 255 (X0Y10Z)+252 xX+63x (Y+
Z). Therefore, in this example, 189
The number of prime numbers is reduced by Y0Z). Actually, X = 20 pieces,
Assuming Y-10 pieces and Z=15 pieces, in the conventional configuration, 10
Although 200 pieces are required, in this embodiment, 5475 pieces are sufficient.

Therefore, the number of required elements is halved, resulting in the following effects.

stomach. Chip area reduction. Lower power consumption c. Increased yield. Miniaturization of the package e. Significant cost reduction [Effects of the invention] According to the present invention, it is possible to reduce the number of required elements while maintaining high speed, which is a feature of the fully parallel type, reducing the chip area and reducing electrode consumption. be able to. Further, as a derivative effect, it is possible to improve the yield, miniaturize the IC package, and significantly reduce costs.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a block diagram showing an embodiment of an A/D converter according to the present invention, and FIG. 3 is a block diagram of a conventional A/D converter. ? 1... Encoder, 12... Output bass sofa, 13... Comparator, 14... Latch circuit, l5... AND circuit, V ■VIT...Reference voltage, VIN...Analog input,

Claims (1)

[Claims] A fully parallel A/D converter with n-bit resolution, which converts n bits of digital output into upper m bits and lower (n-m
) bits, (2^n-1) comparators are installed in parallel at the input stage, and a reference voltage that divides the input voltage range into 2^n equal parts is divided and supplied to these comparators. is used as a reference value for comparison of each comparator with respect to the analog input, and the upper m bits are the voltage at the point where the reference voltage is divided by 2^n and the analog input, including at least a latch circuit and an AND circuit in addition to the comparator ( 2^m-1) composite comparison means send the comparison results to the encoder and m
A digital signal for bits is generated, and the lower (nm) bits combine a latch circuit and an AND circuit in the composite comparison means for (nm) bits, and the comparator generates a digital signal for (nm) bits. The comparison result is output for each corresponding predetermined column, and the comparison result for each column is sent to the encoder through the latch circuit and the AND circuit to generate a digital signal for (n-m) bits. An A/D converter characterized by: