JPH03226287A - Controller - Google Patents

Abstract

PURPOSE:To improve output accuracy and to prevent deterioration of rotary performance of a motor by setting the number of input bit to a digital phase compensation filter higher than that of output bit. CONSTITUTION:A phase compensation filter in a control loop is a digital filter comprising multipliers 20, 22, 24, a subtractor 23, delay units 21, 25, and an adder/subtractor 26. Coefficients K1-K4, shown on the figure, are determined by subjecting transfer function to double primary conversion. Number of input bit to the digital filter is set higher than the number of output bit(n+m). By such arrangement, electrical disturbance of output from the digital filter can be suppressed resulting in suppression of the rotational fluctuation of motor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control device in which a phase compensation filter in a control loop is configured with a digital filter.

[Conventional technology]

FIG. 2 is a block diagram of a control system that controls the speed and phase of, for example, a drum motor or capstan motor of a VTR.

In the figure, 1 is the motor and 2 is the motor angular velocity.
(Frequency Generator) FG section that converts into frequency, 3 is a speed detector that detects speed from FC frequency, 4 is an integrator that converts motor angular velocity into phase,
5 is a phase detector that detects the difference between the reference phase and the rotational phase of the motor, 6 is a phase compensation filter that compensates for the frequency characteristics of the system, 7 is an amplifier that amplifies the control command, and 8 is an MDA that drives the motor. driver amplifier).

An example of the phase compensation filter 6 of FIG. 2 configured with an analog circuit is the circuit shown in FIG. 3. In FIG.
12 is a capacitor with a capacitance C, 13 is an input terminal, and 14 is an output terminal.

The transfer function G (II) of this circuit is expressed by the following equation.

The input/output gain of this circuit is the frequency 1/2πC(R1+
Rt) and below, it is 1, and above the frequency 1/2πCR1, it is Rt/(R+ +Rz).

An example of this phase compensation filter configured with a digital filter is the block diagram shown in FIG.
5 is a delay device, 2G is an adder/subtractor, 27 is an input terminal, and 28 is an output terminal. Coefficient K1. Kg, Ks, and 4 are obtained by bilinear transformation of the aforementioned transfer function G.

In a software servo type control device using a microcomputer or the like, the speed detector 32 in FIG.
The phase detector 51 and phase compensation filter 6 are configured by software, and the phase compensation filter 6 is configured by, for example, a software-based digital filter shown in FIG.

Next, the operation will be explained. The angular velocity of the motor is FC part 2
It is converted into an FC frequency and input to the speed detector 3, and a voltage corresponding to the speed error is output from the speed detector 3. On the other hand, the rotational phase of the motor is obtained by integrating the angular velocity in an integrator 4 to obtain a phase, which is compared with a reference phase in a phase detector 5.
A voltage corresponding to the phase error is output from the phase detector 5.

The output of the phase detector 5 passes through a phase compensation filter 6, is added to the output of the speed detector 3, and is amplified by an amplifier 7.
The signal is input to DA8, and the drive of the motor is controlled.

Next, the operation of the digital filter shown in FIG. 4 will be explained.

For example, K,=27. Kg = 25. Assume that, =213, -211, input/output is 8 bits, and takes a value of θ~255. If the (N-1)th input/output is 128 and the Nth input is 115, then the multiplier 2
The output of 0 is 115X27=3105, the output of multiplier 22 is 128X25=3200, and the output of multiplier 24 is 128
x211=27008, the output of adder/subtractor 26 is 3105
-3200+27008=26913, the output of the divider 23 is 26913÷213-126.35211,...
,,(01111110,01011010°,,,;
(binary display), and the integer part 12 is output from the output terminal 28.
6 (OIIIILO) is output as 8-bit data.

[Problem to be solved by the invention]

A control device in which a conventional phase compensation filter is configured with a digital filter is configured as described above, and since the number of bits of the input and output of the digital filter is the same, sufficient calculation accuracy can be achieved for the output of the digital filter. cannot be obtained, and this lack of calculation accuracy results in electrical disturbances that cause rotational fluctuations in the motor.

This invention was made to solve the above problems, and aims to provide a control device that reduces electrical disturbances output from a digital filter and reduces rotational fluctuations of a motor. .

[Means to solve the problem]

The control device according to the present invention has a digital filter when the phase compensation filter of the control system is configured with a digital filter.
The number of output points of the filter is greater than the number of input points of the filter.

[Effect]

The digital filter for phase compensation in this invention improves accuracy by increasing the number of output bits than the number of input bits, so the electrical disturbance is sufficiently small and hardly causes rotational fluctuations of the motor. .

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a digital filter for phase compensation in a control system according to an embodiment of the present invention, and the configuration of each block is the same as the conventional digital filter shown in FIG. In the conventional example, the input and output bit numbers are the same, whereas in this example, the output (
n+m) bits, which means that the number of output bits is greater than that of input.

The overall configuration of the control device is the same as the block diagram of the conventional control system shown in FIG.

Next, regarding the operation, n=8. The case where m=4 will be explained as an example. The operation during calculation is the same as the conventional digital
The operation is the same as that of the filter, but the output of the divider 23 (for example, 01111110°01011010 , ,
, , ), 8 bits of integer part and 4 bits of fractional part are 12
Bit data (011111100101) is output from the output terminal 28. This output is converted to D/D by PWM output.
The signal is A-converted and added to the output of the speed detector 3. Alternatively, the output of the output terminal is added to the output of the speed detector 3 by software, and then D/A converted by the PWM output. The output obtained by adding the output of the phase detector 5 and the output of the speed detector 3, which have passed through a phase compensation filter using a digital filter, is amplified by the amplifier 7 and then applied to the MDA 8 to control the drive of the motor l. Ru.

In the above embodiment, a digital filter of the form shown in FIG. 1 is shown, but other forms of digital filter may be used.

Further, in the above embodiment, a phase compensation filter for a phase control system has been described, but the present invention may be applied to a phase compensation filter for a speed control system or a filter for other purposes, and the same effects as described above can be obtained.

〔Effect of the invention〕

As described above, according to the control device of the present invention, the number of output bits is greater than the number of input bits of the digital filter for phase compensation in the control system, so the accuracy of the output is improved and the rotation of the motor is This has the effect of not deteriorating performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a digital filter in a control device according to an embodiment of the present invention, FIG. 2 is a block diagram of a control system of a conventional control device, and FIG. 3 is a circuit diagram of a conventional phase compensation filter. FIG. 4 is a block diagram of a conventional digital filter. In the figure, 20, 22, and 24 are multipliers, 23 is a divider, 21.25 is a delay device, and 26 is an adder/subtractor. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A control device characterized in that the number of bits of the output of a digital filter for performing phase compensation of the control system is greater than the number of bits of the input of the filter.