JPH03226090A - Digital convergence circuit - Google Patents

Abstract

PURPOSE:To recover data automatically by allowing a data revision means to revise the data in a 2nd memory means when the storage data of 1st and 2nd memory means are found out to be noncoincident for a vertical blanking period of a video signal. CONSTITUTION:Since a color television receiver generates a pulse signal P in response to a vertical blanking period TV to generate a vertical synchronizing signal S in general. While a video signal is displayed, whether or not a current point of time is within a vertical blanking period TV is judged based on the pulse signal P. In the case of YES, an address is designated sequentially in an address space in response to various adjustment at each adjustment point on a screen and whether or not the data in a RAM 5 in the address and the data in a ROM 4 are coincident is judged. In the case of noncoincidence, the data in the ROM 4 is written in a same address in the RAM 5. Then the same operation is repeated.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a color display such as a color television receiver, and more particularly to a digital convergence circuit for correcting convergence of an electron beam.

(Prior Art) Conventionally, a digital convergence circuit according to the present invention shown in FIG.
A convergence correction device that operates based on the software shown in Fig. 4 has been proposed (for example, the
No. 3-43954 (HO4N9728)).

As shown in the figure, a deflection yoke (
10) and a convergence coil (9),
The RT (11) is supplied with a primary color signal V from a color signal reproducing circuit (not shown), and the deflection yoke (10) is supplied with a sawtooth current A from a deflection circuit (not shown).

A circuit for controlling the amount of energization is connected to the convergence coil (9), and the ROM (4) included in the circuit stores a predetermined value on the CRT (11) screen during the convergence adjustment work in the receiver assembly process. The results after convergence adjustment work at multiple points are written in advance.

When power is turned on to a Calais television receiver equipped with the above circuit, all stored data is transferred from ROM (4) to RAM (5) (Fig. 4 (22)), and then
The adjustment data in M (5) is sent to an interpolation calculation circuit (6), and adjustment data at other points located between the plurality of adjustment points are calculated by interpolation.

A group of adjustment data obtained by this is converted into an analog signal by the D/A converter (7), and then the output circuit (8)
) to create a current C to be supplied to the convergence coil (9).

Further, in readjustment after the convergence adjustment work or adjustment during maintenance after shipment from the factory, the adjustment data is corrected by operating the adjustment operation section (1) in FIG. At this time, the procedure shown in Figure 4 (2
2) to (26) are executed, and the data in ROM (4) is updated.

In other words, determine whether convergence adjustment is in progress (23)
After that, the adjustment data at the adjustment point is input directly to the RAM (5), and the RAM data is changed (2.4).

After that, when it is determined (25) that writing (25) to the ROM (4) is possible, the data in the RAM (5) or the ROM (
4) (26), and returns to the judgment (23).

(Problem to be Solved) However, in the conventional convergence correction device, the adjustment data in the RAM (5) is destroyed by electrostatic noise or dielectric noise caused by, for example, sparks in the CRT (11). Then, misconvergence will continue to occur until readjustment is performed through maintenance.

Therefore, an object of the present invention is to provide a convergence correction circuit that automatically restores the data even if the data in the RAM (5) is destroyed.

(Means for Solving the Problems) A convergence correction circuit according to the present invention includes a first memory means storing reference adjustment data at each position of a plurality of adjustment points on a screen, and a first memory means. and 1
a second memory means having an address space corresponding to one pair and storing adjustment data used directly to control the amount of current to the convergence coil (9); It comprises a control means for controlling writing and reading, and a signal processing means for generating a current to be passed through the convergence coil (9) according to the adjustment data stored in the second memo J means.

Further, the control means includes means for determining whether or not the present moment is in a vertical blanking period of the video signal, and a means for determining whether or not the present moment is in a vertical blanking period of the video signal, and a means for determining whether or not the present moment is in a vertical blanking period of the video signal, and a means for determining whether or not the present time is in a vertical blanking period of the video signal, and a means for controlling the stored data in the second memory means to correspond to the same adjustment point during the vertical blanking period. and data changing means for matching data stored in the first memory means.

(Function) Adjustment data at a plurality of predetermined adjustment points are stored in advance in the first memory means and the second memory means, respectively.

When the adjustment is completed, the data stored in both memory means at the same adjustment point match.

Since the second memory means is always in operation for reading data, there is a higher possibility that stored data will be destroyed than in the first memory means.

However, the corrupted data in the second memory means is automatically restored in the following manner.

While a video signal is being displayed on the CRT (11), when it is determined by the control means that the video signal has entered a vertical blanking period, for example, the data stored in the first memory means and the data stored in the first memory means are When a discrepancy is found in the stored data based on the comparison with the stored contents of the second memory means, the data changing means changes the data so that the data in the second memory means matches the data in the first memory means. Do this.

If changes to all mismatched data are not completed within a single vertical blanking period, remaining data modification processing continues in a subsequent vertical blanking period.

The signal processing means performs processing on the data stored in the second memory means.
For example, by performing interpolation calculations, D/A conversion, etc., a current to be passed through the convergence coil (9) is generated, and as a result,
Convergence of the electron beam of the CRT (11) is performed.

Note that since the nIJ data change process is always performed within the vertical blanking period of the video signal, no disturbance occurs on the screen on which the video signal is displayed.

(Effect of the invention) According to the digital convergence circuit according to the present invention,
Even if the data in the second memory means is destroyed by a spark in the CRT (11), the data is automatically restored without any operation by the user, so accurate convergence can be performed.

(Examples) Examples are provided to explain the present invention, and should not be construed as limiting the invention described in the claims or reducing its scope.

FIG. 1 shows an example of a circuit configuration in which a digital convergence circuit according to the present invention is implemented in a color television. Adjustment operation unit (1), ROM (4), RAM (5), interpolation calculation circuit (6), D/A converter (7) and output circuit (
8) has the same configuration as the conventional one, so its explanation will be omitted. still,
ROM (4) becomes the first memory means, and RAM (5) becomes the second memory means. In addition, the interpolation calculation circuit (6), D/
The A converter (7) and the output circuit (8) form the signal processing means which are to supply current to the convergence coil (9).

The information processing unit (2), which serves as a control means for controlling the writing and reading of data to and from RO~1 (4) and RAM (5), is constituted by a microcomputer, and is controlled by software (Fig. 3) to be described later. The ROM (3) that is installed is connected.

In general, in color television, Fig. 2 (a)
) In order to generate the vertical synchronizing signal S shown in FIG. In order to make a determination, the pulse signal P is connected to the information processing unit (2) of FIG. 1.

The operation of the above circuit will be explained below with reference to FIG. still,
It is assumed that reference adjustment data is stored in advance in RO to □f(4) by adjustment at the assembly stage as in the conventional case.

When you turn on the power to the television receiver, first the ROM (
The stored data is read from 4), and the data is stored in RAM (
5) is written (13).

Thereafter, it is determined (14) whether or not convergence is being adjusted for maintenance or the like, and if NO, that is, if a video signal is being displayed, the current time is within the vertical blanking period Tv based on the pulse signal P. It is judged (15) whether or not it is in
It is determined (17) whether the data in A M (5) and the data in ROM (4) match. If they match, the process returns to the above judgment (14), and if they do not match, the data is written in the ROM (4) or to the same address in the RAM (5) (18), and then the process returns to the judgment (1).
The process returns to step 4) and the same operation is repeated.

If the determination procedure (14) is YES, that is,
In the case of readjustment due to maintenance etc., the same processes (19) to (26) as the conventional processes (24) to (26) shown in FIG.
21) is executed and the data in the ROM (4) is updated.

In the above digital convergence circuit (for example, there are N adjustment points on the screen, adjustment operations at each adjustment point (horizontal adjustment, vertical adjustment, adjustment for each primary color)
is required M times, ROM (4) and RAM M
The number of addresses in the address space required for (5) is N - M, but the number of times procedures (16) to (18) in Figure 3 can be executed within one vertical blanking period is X, one field. Assuming that the period is Tf, the time Tn required to update data in all address spaces is expressed by the following formula.

T n =(N-M/X) T f Therefore, this time can be shortened by increasing X.

In procedures (16) to (18) in Figure 3, only the data with mismatches are changed, so the ROM
The processing time can be reduced compared to the method (4) in which all the contents are moved to RAM (5).

The digital convergence circuit described above does not require any hardware changes compared to conventional convergence devices.
This is extremely effective because it can be achieved by only modifying a portion of the software.

Furthermore, the present invention can be implemented not only in direct-view type televisions but also in projection type televisions equipped with a plurality of CRTs.

The above description of the embodiments is for illustrating the present invention, and should not be construed to limit or reduce the scope of the invention described in the claims. Further, it goes without saying that the configuration of each part of the present invention is not limited to the above-mentioned embodiments, and various modifications can be made within the technical scope of the claims.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital convergence circuit according to the present invention, FIG. 2 is a timing chart showing a video signal and a pulse signal for vertical blanking period detection, and FIG. 3 is a flow chart explaining the circuit operation. ,
FIG. 4 is a flowchart explaining the conventional circuit operation. (2)...Information processing unit (4)...ROM (5)...RAM (6)...Interpolation calculation circuit (9)...Convergence coil

Claims (1)

[Claims] [1] The CRT (11) is equipped with a convergence adjustment coil (9), and the convergence coil (9) is energized according to adjustment data set corresponding to multiple adjustment points on the screen. In the digital convergence circuit for controlling the amount, a first memory means storing reference adjustment data at each position of the plurality of adjustment points, and an address space corresponding one-to-one with the first memory means. a second memory means in which adjustment data used directly to control the amount of current applied to the convergence coil (9) is stored; and control for controlling writing and reading to and from the first and second memory means. and signal processing means for generating a current to be applied to the convergence coil (9) in accordance with the adjustment data stored in the second memory means, and the control means is configured to perform vertical blanking of the video signal at the current moment. means for determining whether the vertical blanking period is in progress; and data changing means for making the data stored in the second memory means coincide with the data stored in the first memory means corresponding to the same adjustment point during the vertical blanking period. A digital convergence circuit characterized by: