JPH03222462A - Mold package type thick film hybrid ic - Google Patents
Mold package type thick film hybrid icInfo
- Publication number
- JPH03222462A JPH03222462A JP1613390A JP1613390A JPH03222462A JP H03222462 A JPH03222462 A JP H03222462A JP 1613390 A JP1613390 A JP 1613390A JP 1613390 A JP1613390 A JP 1613390A JP H03222462 A JPH03222462 A JP H03222462A
- Authority
- JP
- Japan
- Prior art keywords
- thick film
- circuit board
- circuit
- film hybrid
- mold package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 claims abstract description 4
- 238000001721 transfer moulding Methods 0.000 claims description 18
- 229910001220 stainless steel Inorganic materials 0.000 claims description 14
- 239000010935 stainless steel Substances 0.000 claims description 14
- 239000011521 glass Substances 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 9
- 238000010304 firing Methods 0.000 claims description 8
- 238000007639 printing Methods 0.000 claims description 7
- 239000011347 resin Substances 0.000 abstract description 15
- 229920005989 resin Polymers 0.000 abstract description 15
- 230000000694 effects Effects 0.000 abstract description 10
- 238000004806 packaging method and process Methods 0.000 abstract description 6
- 238000000465 moulding Methods 0.000 abstract description 4
- 238000003466 welding Methods 0.000 abstract description 2
- 230000000191 radiation effect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 26
- 238000000034 method Methods 0.000 description 18
- 239000000758 substrate Substances 0.000 description 13
- 239000010953 base metal Substances 0.000 description 12
- 239000000919 ceramic Substances 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 2
- 238000007598 dipping method Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、トランスファーモールドによりパッケージソ
ゲされたモールドパッケージ型厚膜ハイブリットＩＣに
関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a mold package type thick film hybrid IC whose package is soldered by transfer molding.
（従来の技術）
従来、厚膜ハイブリットＩＣ（厚膜混成集積回路）のパ
ッケージングには、大別して気密封止法と樹脂封止法と
があり、樹脂封止法としては注型法、浸漬法、滴下法、
流動浸漬法、トランスファーモールド法があった。その
うち、トランスファーモールド法は溶融した樹脂を小孔
を通じて金型のキャビティ内に送り込んで硬化する方法
であり、樹脂封止法の中では電気的・機械的特性が最も
高く、信転性が期待できるものである。(Prior art) Conventionally, packaging for thick film hybrid ICs (thick film hybrid integrated circuits) can be roughly divided into hermetic sealing methods and resin sealing methods.Resin sealing methods include casting methods and dipping methods. method, drip method,
There were fluid immersion methods and transfer molding methods. Among these, the transfer molding method is a method in which molten resin is sent into the mold cavity through small holes and hardened.It has the highest electrical and mechanical properties among the resin sealing methods, and is expected to be reliable. It is something.
このような分野の技術としては、「トランスファーモー
ルド構造ハイブリットＩＣの緒特性改善Ｊ （ＮＥＣ
，込山利男他、第３回マイクロエレクトロニクスシンポ
ジウム（Ｍ Ｅ Ｓ ’ ８９） １９８９年７月Ｐ、
１１３ ）に記載されるものがあった。Technologies in this field include ``Transfer mold structure hybrid IC characteristics improvement J (NEC
, Toshio Komiyama et al., 3rd Microelectronics Symposium (MES'89) July 1989 P.
113).
以下、その構成を図を用いて説明する。The configuration will be explained below using figures.
第２図は従来のトランスファーモールドパッケージ型ハ
イブリットＩＣ（ＨＩＣ）の−構成例を示す断面図であ
る。FIG. 2 is a sectional view showing an example of the configuration of a conventional transfer mold package type hybrid IC (HIC).
この図に示すモールドパッケージ型ハイブリットＩＣは
、通常のモールドＩＣのパッケージ構造と比較して、リ
ードフレーム付配線基板を採用している点が異なってい
る。リードフレーム２の基板搭載用台座３に回路基板５
が接着剤４を介して接着固定されている。このように固
定された回路基板５上にペアチップＩＣ７が搭載され、
このペアチップＩＣ７と回路基板５上の導体配線がワイ
ヤボンデングされることにより、ワイヤ８で接続されて
いる。このように構成されたリードフレーム２に接着固
定された回路基板５は成形樹脂１によりトランスファー
モールドされている。The mold package type hybrid IC shown in this figure differs from the package structure of a normal mold IC in that it uses a wiring board with a lead frame. The circuit board 5 is mounted on the pedestal 3 for mounting the board on the lead frame 2.
are adhesively fixed via an adhesive 4. A pair chip IC 7 is mounted on the circuit board 5 fixed in this way,
This paired chip IC 7 and the conductor wiring on the circuit board 5 are connected by a wire 8 by wire bonding. The circuit board 5 adhesively fixed to the lead frame 2 constructed in this way is transfer molded with the molding resin 1.
このようなトランスファーモールドによるパッケージン
グの目的は、半導体素子と搭載部品の機械的保護及び耐
湿保護にある。また、厚膜ハイブリットＩＣをトランス
ファーモールドでパッケージングすることにより、通常
の半導体ＩＣと同様の形状になるため、自動搭載化、薄
形化、製造工程の自動化等多くの利点がある。ここで使
用する厚膜ハイブリット基板としては、従来では主とし
てセラミック基板が用いられており、その他に、Ａ１又
はＦｅ−ＮＩをベースにした金属コア基板も捉案されて
いる。The purpose of packaging using such transfer molding is to provide mechanical protection and moisture protection for semiconductor elements and mounted components. In addition, by packaging a thick film hybrid IC using transfer molding, it has a shape similar to that of a normal semiconductor IC, so there are many advantages such as automatic mounting, thinning, and automation of the manufacturing process. As the thick film hybrid substrate used here, a ceramic substrate has conventionally been mainly used, and metal core substrates based on A1 or Fe-NI are also being considered.
（発明が解決しようとする課題）
しかしながら、通常の半導体【Ｃをトランスファーモー
ルドによりパッケージングした周知のモールドＩＣの場
合とは異なり、厚膜ハイブリットＩＣのトランスファー
モールドには特有の技術的困難性が有り、上記構成の従
来の基板では、以下のような問題点があった。(Problem to be Solved by the Invention) However, unlike the well-known case of molded ICs in which ordinary semiconductors are packaged by transfer molding, transfer molding of thick film hybrid ICs has unique technical difficulties. The conventional substrate having the above structure had the following problems.
（１）セラミック基板
セラミック基板自体の放熱性が悪いので、素子に悪影響
を与えたり、また、樹脂とセラミックの熱膨張の違いか
ら、モールド時に基板にクラックが生じ、更に、基板搭
載台座３とセラミック基板５とは、接着剤４で固着せざ
るを得ないため、接着剤４及び接着側塗布装置が必要で
あり、コストアップにつながると共に、接￥Ｉ削４のは
み出しによるワイヤポンディングパッドへの流れ出しに
より、ワイヤボンディングが不能になる等の問題点があ
った。(1) Ceramic board Since the heat dissipation of the ceramic board itself is poor, it may have an adverse effect on the device, and due to the difference in thermal expansion between resin and ceramic, cracks may occur in the board during molding. Since the substrate 5 has no choice but to be fixed with adhesive 4, the adhesive 4 and adhesive side applicator are required, which leads to an increase in cost and also prevents damage to the wire bonding pad due to protrusion of the contact I cutting 4. There were problems such as wire bonding becoming impossible due to the outflow.
（２）ＡＩ、Ｆｅ−ＮＩをベースとした金属コア基ＡＩ
又はＦｅ−Ｎｉをベースとした金属コア基板は、厚膜印
刷後焼成するときの高温（８５０〜９００℃）に耐える
ことができないため、この基板上に厚膜焼成印刷回路を
作ることは実質上できなかった。また、焼成によらない
厚膜印刷回路の形成方法として、金属コア基板上に樹脂
をコーティングすることによって絶縁層を形成し、この
上に導電パターンを厚膜印刷するトランスファーモール
ド法が考えられるが、絶縁層が樹脂のため、トランスフ
ァーモールド時に加熱された溶融樹脂が絶縁層の樹脂に
接触して影響を与え、絶縁層上の厚膜印刷抵抗が不安定
となることから、この方法を採用することはできない、
更に、金属コア基板上の絶縁層として樹脂の代わりにセ
ラミック等の無機質材料をコーティングすれば、トラン
スファーモールドを採用することができるが、絶縁層上
の回路が薄膜回路となるので、コストアップを招くと共
に、電気的パワーが取れない等の欠点を有する。(2) AI, metal core based AI based on Fe-NI
Alternatively, since Fe-Ni-based metal core substrates cannot withstand the high temperatures (850-900°C) during firing after thick film printing, it is virtually impossible to create thick film fired printed circuits on this substrate. could not. In addition, as a method for forming a thick film printed circuit that does not involve firing, a transfer molding method is considered, in which an insulating layer is formed by coating a metal core substrate with resin, and a conductive pattern is thickly printed on the insulating layer. Since the insulating layer is made of resin, the molten resin heated during transfer molding will come into contact with the resin of the insulating layer and affect it, making the thick film printed resistor on the insulating layer unstable, so this method is adopted. can't,
Furthermore, if an inorganic material such as ceramic is coated instead of resin as an insulating layer on the metal core substrate, transfer molding can be used, but the circuit on the insulating layer becomes a thin film circuit, which increases costs. Additionally, it has drawbacks such as the inability to obtain electrical power.
本発明は、上記問題を解決するために、Ｗ、膜ハイブリ
ットＩＣをパッケージングするのに電気的・機械的特性
が最も高く、信親性が期待できるトランスファーモール
ド法を採用するにあたり、セラミック基板におけるモー
ルド時のクラックの発生、及びＡＩ、Ｆｅ−Ｎｉをベー
スとした金属ベース基板において、高温焼成（８５０〜
９００″Ｃ）に耐えられないことによる厚膜印刷焼成が
できない等の問題点を除去し、厚膜印刷焼成が可能で、
放熱性が高く、しかもトランスファーモールドによりパ
ッケージングできるモールドパッケージ型厚膜ハイブリ
ットＩＣを提供することを目的とする。In order to solve the above-mentioned problems, the present invention employs a transfer molding method, which has the highest electrical and mechanical properties and can be expected to be reliable, for packaging W and film hybrid ICs. In metal base substrates based on AI and Fe-Ni, high temperature firing (850 ~
It eliminates problems such as not being able to print and fire thick films due to the inability to withstand temperatures of 900″C), and allows thick film printing and firing.
It is an object of the present invention to provide a mold package type thick film hybrid IC which has high heat dissipation properties and can be packaged by transfer molding.
（課題を解決するための手段）
本発明は、上記目的を達成するために、モールドパッケ
ージ型厚膜ハイブリットＩＣにおいて、ステンレス鋼を
ベースにし、該ベース上の両面又は片面の全面又は一部
及び周囲側面の全面又は−部をガラス絶縁層で覆って焼
成されたベース上に厚膜印刷焼成により導体、抵抗体、
スルーホール接続を含む回路パターンを形成してなる金
属ベース厚膜回路基板に回路部品を搭載し、全体をトラ
ンスファーモールドによりパッケージングするようにし
たものである。(Means for Solving the Problems) In order to achieve the above object, the present invention provides a molded package type thick film hybrid IC, which is based on stainless steel, and includes the entire or part of both sides or one side on the base and the surrounding area. Conductors, resistors,
Circuit components are mounted on a metal-based thick-film circuit board formed with a circuit pattern including through-hole connections, and the whole is packaged by transfer molding.
（作用）
本発明によれば、上記のように構成したので、ベース金
属として、高温焼成（８５０〜９００℃）に十分耐える
と共に、高温で酸化され難いステンレス鋼を使用してい
るため、ベース金属の周囲に無機質のガラスを絶縁層と
して形成することができる。従って、金属ベース基板上
の絶縁層は焼成されたガラスであるので、トランスファ
ーモールドの材料である樹脂と反応することはない。ま
た、この後は通常の厚膜印刷及び焼成が可能となるため
、抵抗体の高精度な形成とトリミングを行うことができ
る。(Function) According to the present invention, with the above structure, stainless steel, which can withstand high temperature firing (850 to 900°C) and is not easily oxidized at high temperatures, is used as the base metal. An inorganic glass can be formed as an insulating layer around the . Therefore, since the insulating layer on the metal base substrate is made of fired glass, it does not react with the resin that is the material of the transfer mold. Further, since normal thick film printing and baking are possible after this, highly accurate formation and trimming of the resistor can be performed.
更に、厚膜回路であるため、電気的にパワーのあるもの
ができる。更に、トランスファーモールド法が適用可能
となるので、電気的・機械的にも信頼のおけるパンケー
ジングを行うことができる。Furthermore, since it is a thick film circuit, it can be electrically powerful. Furthermore, since the transfer molding method can be applied, electrically and mechanically reliable pancaging can be performed.
また、トランスファーモールドした際の基板へのクラン
クの発生を防止することができると共に、放熱効果が高
く、電気的ノイズに対するシールド効果を有する。In addition, it is possible to prevent the generation of cranks on the substrate during transfer molding, and it has a high heat dissipation effect and a shielding effect against electrical noise.
（実施例）
以下、本発明の実施例について図面を参照しながら詳細
に説明する。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図は本発明の実施例を示すトランスファーモールド
パッケージ型厚膜ハイブリットＩＣの断面図、第３図は
本発明のリードフレームと回路基板とが結合した状態を
示す斜視図、第４図は本発明のトランスファーモールド
パッケージ型厚膜ハイブリットＩＣの斜視図、第５図〜
第７図は本発明の他の実施例を示すベース金属と絶縁層
の斜視図である。FIG. 1 is a cross-sectional view of a transfer mold package type thick film hybrid IC showing an embodiment of the present invention, FIG. 3 is a perspective view showing a state in which the lead frame and circuit board of the present invention are combined, and FIG. A perspective view of the transfer mold package type thick film hybrid IC of the invention, FIG.
FIG. 7 is a perspective view of a base metal and an insulating layer showing another embodiment of the present invention.
これらの図に示すように、ステンレス鋼をベース金属１
９としたステンレスペース回路基板をリードフレーム１
２に固定する。そして、前記ベース金属１９の裏及び周
囲側面に印刷又は浸漬により、ガラス材料をコーティン
グして焼成することによって、ガラス絶縁層１３．１５
を形成する。このようにして作られたガラス絶縁層１３
．１５上に、グイポンディングパッド、ワイヤポンディ
ングパッド、その他、モールドパッケージＩＣパッド、
回路部品パッド、クロスオーバガラス、抵抗体、オーバ
ガラス等を含む回路パターン２０（第３図参照）を、通
常用いられている厚膜印刷、乾燥、焼成（８５０〜９０
０℃）を繰り返すことにより形成する。As shown in these figures, stainless steel is used as base metal 1
Lead frame 1 is a stainless steel paced circuit board with 9
Fixed at 2. Then, a glass insulating layer 13.15 is coated with a glass material by printing or dipping on the back and surrounding side surfaces of the base metal 19 and fired.
form. Glass insulation layer 13 made in this way
．． On 15, Gui bonding pad, wire bonding pad, other, mold package IC pad,
A circuit pattern 20 (see FIG. 3) including circuit component pads, crossover glass, resistors, overglass, etc., is printed using conventional thick film printing, drying, and baking processes (850 to 90 mm).
0°C).
第３図に示すように、回路形成されたステンレスペース
回路基板２１を溶接又はカシメ等により、リードフレー
ム１２に固定する。この時、ステンレスペース回路基板
２１のベース金属１９とリードフレーム１２とを、予め
一体化しておくこともできる。As shown in FIG. 3, the stainless steel pace circuit board 21 on which the circuit has been formed is fixed to the lead frame 12 by welding, caulking, or the like. At this time, the base metal 19 of the stainless steel paced circuit board 21 and the lead frame 12 may be integrated in advance.
次に、第４図に示すように、ステンレスペース回路基板
２１上にペアチップＩＣ１７、モールドパッケージＩＣ
，その他の回路部品１０を搭載し、必要箇所を一例とし
て、ステンレスペース回路基板２１のパッド２２とリー
ドフレーム１２とをワイヤ１８により接続する。続いて
、ペアチップＩＣ１７も同様にステンレスペース回路基
板２１と接続する。このように構成された厚膜ハイブリ
ットＩＣを、成形樹脂１１でトランスファーモールドし
てパンケージングする。Next, as shown in FIG.
, and other circuit components 10 are mounted, and the pads 22 of the stainless steel pace circuit board 21 and the lead frame 12 are connected by wires 18, as an example. Subsequently, the paired chip IC 17 is also connected to the stainless steel pace circuit board 21 in the same manner. The thus constructed thick film hybrid IC is transfer molded with molding resin 11 and pancaged.
ステンレスペース回路基板２１の形態は、第５図に示す
ように、ステンレス鋼のベース金属１９の片面全面にガ
ラス絶縁層１５′及び回路パターン（図示せず）を設け
たものを用いてもよいが、第６図に示すように、ステン
レス鋼のベース金属１９の片面の一部に、ガラス絶縁層
１５“及び回路パターン（図示せず）を設けたものを用
いてもよい。As shown in FIG. 5, the stainless steel pace circuit board 21 may have a glass insulating layer 15' and a circuit pattern (not shown) on the entire surface of one side of the base metal 19 made of stainless steel. As shown in FIG. 6, a glass insulating layer 15'' and a circuit pattern (not shown) may be provided on a portion of one side of a stainless steel base metal 19.
更に、第７図に示すように、ステンレス鋼のベース金属
１９の表面全面と裏面の一部にガラス絶縁層１５ａ、１
５ｂ及び回路パターン（図示せず）を設け、表裏をスル
ーホール２３で接続したものを用いてもよい。Furthermore, as shown in FIG. 7, glass insulating layers 15a, 1
5b and a circuit pattern (not shown), and the front and back sides are connected by through holes 23 may be used.
また、リードフレーム１２とベース金属１９は最初から
一体化しておくこともできるが、別体にして後でハンダ
付は等で一体化してもよい。Further, the lead frame 12 and the base metal 19 can be integrated from the beginning, but they may be made separate and later integrated by soldering or the like.
なお、本発明は上記実施例に限定されるものではなく、
本発明の趣旨に基づいて種々の変形が可能であり、これ
らを本発明の範囲から排除するものではない。Note that the present invention is not limited to the above embodiments,
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.
（発明の効果）
以上、詳細に説明したように、本発明によれば、次のよ
うな効果を奏することができる。(Effects of the Invention) As described above in detail, according to the present invention, the following effects can be achieved.
ベース金属として、高温焼成（８５０〜９００°Ｃ）に
十分耐えると共に、高温で酸化され難いステンレス鋼を
使用しているため、ベース金属の周囲に無機質のガラス
を絶縁層として形成することができる。As the base metal is stainless steel, which can withstand high temperature firing (850 to 900°C) and is not easily oxidized at high temperatures, it is possible to form inorganic glass as an insulating layer around the base metal.
これにより、この後は通常の厚膜印刷及び焼成が可能と
なるため、高精度な抵抗体を形成してトリミングするこ
とができる。また、厚膜回路であるため、電気的にパワ
ーのあるものができる。As a result, normal thick film printing and firing can be performed thereafter, so that highly accurate resistors can be formed and trimmed. Also, since it is a thick film circuit, it can be electrically powerful.
更に、トランスファーモールド法が適用可能となるので
、電気的・機械的に最も信頼のおけるパッケージングが
可能となる。そして、トランスファーモールドした際の
基板へのクラックの発生を防止することができると共に
、放熱効果が高く、しかも電気的ノイズに対するシール
ド効果を奏することができる。Furthermore, since the transfer molding method can be applied, the most electrically and mechanically reliable packaging is possible. In addition, it is possible to prevent the occurrence of cracks in the substrate during transfer molding, and it is also possible to have a high heat dissipation effect and a shielding effect against electrical noise.
第１図は本発明の実施例を示すトランスファーモールド
パッケージ型厚膜ハイブリットＩＣの断面図、第２図は
従来のトランスファーモールドパッケージ型ハイブリッ
トＩＣの一構成例を示す断面図、第３図は本発明のリー
ドフレームと回路基板とが結合した状態を示す斜視図、
第４図は本発明のトランスファーモールドパッケージ型
厚膜ノ１イブリッドＩＣの斜視図、第５図〜第７図は本
発明の他の実施例を示すベース金属と絶縁層の斜視図で
ある。
１１・・・成形樹脂、１２・・・リードフレーム、１３
．１５１５’ 、 １５“、１５ａ、１５ｂ−・・ガラ
ス絶縁層、１７−・・ペアチップＩＣ，１８・・・ワイ
ヤ、１９・・・ベース金属、２０・・・回路パターン、
２１・・・ステンレスペース回１１［，２２・・・パッ
ド、２３・・・スルーホール。Fig. 1 is a sectional view of a transfer mold package type thick film hybrid IC showing an embodiment of the present invention, Fig. 2 is a sectional view showing an example of the configuration of a conventional transfer mold package type hybrid IC, and Fig. 3 is a sectional view of the present invention. a perspective view showing a state in which the lead frame and the circuit board are combined;
FIG. 4 is a perspective view of a transfer mold package type thick film hybrid IC of the present invention, and FIGS. 5 to 7 are perspective views of a base metal and an insulating layer showing other embodiments of the present invention. 11... Molded resin, 12... Lead frame, 13
．． 1515', 15", 15a, 15b--Glass insulating layer, 17--Pair chip IC, 18--Wire, 19--Base metal, 20--Circuit pattern,
21... Stainless steel pace 11 [, 22... Pad, 23... Through hole.
Claims (1)
の全面又は一部及び周囲側面の全面又は一部をガラス絶
縁層で覆って焼成されたベース上に厚膜印刷焼成により
導体、抵抗体、スルーホール接続を含む回路パターンを
形成してなる金属ベース厚膜回路基板に回路部品を搭載
し、全体をトランスファーモールドによりパッケージン
グしたことを特徴とするモールドパッケージ型厚膜ハイ
ブリットＩＣ。Conductors, resistors, through-holes are printed on the base made of stainless steel, and the whole or part of both sides or one side of the base and the whole or part of the surrounding side surfaces are covered with a glass insulating layer and fired by thick film printing and firing. A mold package type thick film hybrid IC characterized in that circuit components are mounted on a metal base thick film circuit board formed with a circuit pattern including hole connections, and the whole is packaged by transfer molding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1613390A JP2605157B2 (en) | 1990-01-29 | 1990-01-29 | Mold package type thick film hybrid IC |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1613390A JP2605157B2 (en) | 1990-01-29 | 1990-01-29 | Mold package type thick film hybrid IC |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03222462A true JPH03222462A (en) | 1991-10-01 |
| JP2605157B2 JP2605157B2 (en) | 1997-04-30 |
Family
ID=11907995
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1613390A Expired - Fee Related JP2605157B2 (en) | 1990-01-29 | 1990-01-29 | Mold package type thick film hybrid IC |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2605157B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012248889A (en) * | 2008-01-15 | 2012-12-13 | Dainippon Printing Co Ltd | Wiring member for semiconductor device, composite wiring member for semiconductor device, and resin-sealed-type semiconductor device |
-
1990
- 1990-01-29 JP JP1613390A patent/JP2605157B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012248889A (en) * | 2008-01-15 | 2012-12-13 | Dainippon Printing Co Ltd | Wiring member for semiconductor device, composite wiring member for semiconductor device, and resin-sealed-type semiconductor device |
| US8796832B2 (en) | 2008-01-15 | 2014-08-05 | Dai Nippon Printing Co., Ltd. | Wiring device for semiconductor device, composite wiring device for semiconductor device, and resin-sealed semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2605157B2 (en) | 1997-04-30 |
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