JPH03222077A - Contour paint-out circuit - Google Patents

Abstract

PURPOSE:To execute paint-out exactly and quickly by connecting N numbers of EXOR gates and one latch(LT) as prescribed, and outputting an EXOR gate output Q after the paint-out to an input decision bit. CONSTITUTION:When N=8, the first input D1-DN is 00100000 of I, and the output of LT is C0=00. Then, output Q1-QN is 00111111, that is, when D1=0, C0=0 then Q1=0, when D2=0 and Q1=0, then Q2=0, but since D3=1 when Q2=0 then Q3=1 when Q3=1, then D4=0 and Q4=1, and so on, and when D5-D8 is zero, then Q5-Q8 becomes one, and Q8=1 is fetched to a latch circuit LT. Next, for an input of 10110000, the output is 00100000. Next, for an input of 01001000, the output becomes 01110000. Apparently, the places between the first one and the next even number order is filled with one, so dots are filled between contour dots. Further, a generated discrimination dot is used, so it does not end at an odd number, so the error of painting out until the end of the character/ graphic does not occur.

Description

[Detailed Description of the Invention] [Summary of the Invention] An outline filling circuit for filling in an outline area based on outline data of characters or figures, so that filling can be done accurately and quickly without mistakes. It is equipped with a plurality of exclusive OR gates and one latch circuit, and sets the first dot position z of the contour dot or group of contour dots of the image that is detected oddly in the scanning direction, and A plurality of pieces of pattern data each having a discrimination bit set at a position one dot away from the last dot of the contour dot or group of contour dots detected the second time are input to one side of the exclusive OR gate, and the The output of the circuit and the output of the previous stage exclusive OR gate are used as the other inputs, and the output of the final stage exclusive OR gate is input to the latch circuit, which is used as the other input of the first stage exclusive OR gate when the next discrimination bit is input. The output of the OR gate is configured to be the output after filling in the input discrimination bit.

[Industrial application field]

The present invention relates to an outline filling circuit for filling in an area within an outline based on outline data of a character or figure.

Text or figure data may be held as pattern data or as outline data (vector data, etc.).The latter makes it easy to enlarge/reduce the text/figure, but for display/recording it is necessary to fill in the outline. is necessary. The former is the opposite; recording/display can be performed immediately using the pattern data, but there are problems in that enlarging/reducing is not easy and quality deteriorates. The present invention belongs to the latter category, and relates to its contour filling means, and more specifically to its filling circuit.

[Conventional technology]

A conventional outline filling circuit includes a circuit disclosed in Japanese Patent Application Laid-Open No. 61-34677, an outline of which is shown in FIG.

As shown in the figure, this includes n OR gates G1 to Gn, n exclusive OR gates EG, -EG, and one U-NC LT, and includes n-bit contour pattern data A, to A.
7 and outputs n-bit pattern data B, -B, and 1 after filling processing.

The inputs of the exclusive OR gates EC, EC, . . . are the corresponding contour pattern data bits A, , A2 .・・・・・・
...and the outputs of the previous stage exclusive OR gate C+, Cz, ...
...(Shodan EG.

is the output Co) of the latch LT. The output C,l of the exclusive OR gate EC, for the end bit A, of the data block A,-A, is taken into the latch LT, and when the next data block A,~A,1 is input, the exclusive OR gate for the start end bit A1 It becomes one input of the OR gate E G t.

The outline pattern data is, for example, the data in which the outline of the character A in FIG.

Speaking only on chain l1IIL, point P2. P2. P3゜P
4 in 1, other Po to P, Pl to Pl, Pl to P3, P3 to P4, P4 to P
, everything is 0. Data oooooio
Divide o... into n bits each, and repeatedly input the first block, second block, etc. to terminals A1 to A7, each time obtaining outputs B, ~B, and l. .

Initially, the latch LT is reset by the reset signal R3 and the output C0 is 0. Therefore input AI.

Az,... is oooooioiooooo...
..., then A t ” Co = 0, so B
1 is O, C, is also O. Also, C r = A z =
OT: Because there is, B2 is 0. Cz is also 0. The same goes for 83. C3 is 01B4. C4 also becomes O. But As
= 1, so B is 1, C5 is also 1, and A h ”
'O, but since C1 is l, B6 becomes 1 and C6 also becomes 1. Similarly, B, =i.

C? ,=1, and B6 also becomes 1, but C8 becomes O because Ag=1°C7=1. B9 is CIl, A9 is O
Therefore, it becomes O, and C1 also becomes O. B. .

B, etc. are also 0. C8°+C11 etc. also become 0. In this way, in this circuit, the corresponding bits of B, ~B7 become 1 from the first 1 of A, ~A7 to the next 1, and A1 ~A, .
If 1 appears again in , from that l to the next 1, B, ~
The corresponding bits of B, , become 1 (odd numbers to even numbers become 1), and the inside of the outline is filled in.

However, in this circuit, if there is only one 1 in the contour pattern data (there is no even numbered 1 for an odd numbered 1), everything after that number will become 1 (will be filled out).
There is a problem. In the case where there is only one l,
Occurs on sharp corners and narrow parts of characters and figures.

The present inventor has previously filed an application (Japanese Unexamined Patent Publication No. 305478/1986) for a method in which discriminant points are determined from contour points and the contour is filled in by software processing to fill in the spaces between the discriminant points.

To explain this overview using Figure 7, (a) is the original figure,
When the outline of this original figure is extracted, the same figure (b) is obtained. If each pixel (each dot) of this contour figure is traced counterclockwise as shown in FIG. 10C and the dots are generated/erased according to a predetermined logic, the image shown in FIG. 2D is obtained. The dots indicated by double circles in this figure are here called discrimination points, and there are only two of each in the horizontal direction (scanning direction when filling in).

The table below shows how to set the discrimination points. In this table, ■ indicates that no discrimination point is set for the pixel in question, ■ indicates that a discrimination point is set for the pixel in question, ■ indicates that a discrimination point is set on the right side of the pixel, and ■ indicates both the pixel and the right side of the pixel. The decision point is set at .

For the reference pixel, the movement method from the previous pixel is set as the preceding movement direction, and for the reference pixel,
The moving direction to the next pixel is set as the moving direction to be followed, and how to set the discrimination point for the reference pixel is the intersecting process. As for processing,■
There are four ways ~ ■, and the discrimination point J I + J I 1 +
... are set according to the rules in this table.

In Fig. 7(d), the scanning is done as a TV scan (from left to right, top to bottom), and the filling starts at the first discrimination point (the first discrimination point is filled out), and the filling ends at the next discrimination point (
Assuming that the next discrimination point is not filled in, but only the one before it is filled in), the original figure shown in FIG. 7(a) is obtained.

[Problems to be Solved by the Invention] The conventional filling circuit shown in FIG. 6 has a problem in that if there is one 1 at an outline point, the area from that point to the end of the character/figure area will be filled.

In this respect, the method shown in Figure 7 generates discriminant points from contour points,
There are always two discrimination points (one exists in pairs), and by sorting the areas between the discrimination points in the pair, it is possible to perform error-free filling processing.

However, since it is a software process, it takes time.

It is an object of the present invention to improve the visibility and to enable filling in accurately and quickly without making any mistakes.

(Means for Solving the Problems) FIG. 1 shows a filling circuit of the present invention. It is formed by connecting N OR gates EXORI to EXORN and a latch circuit LT as shown. Exclusive or gate EOR+~EX
One input of ORH is for N pits of discrimination point data, -
D, and the other input is the output of the previous stage EXOR gate, except that the first stage EXOR is the output of the launch circuit LT. (Final stage exclusive off-game) The output of EXORM is input to the latch circuit LT. This latch circuit LT receives the output of the EXORN from the input of the clock CK, and is reset by the input of the reset signal FST to set the output to 0.
Make it. The FST input is the output Q1~Q of each exclusive OR gate into which the beginning of each scanning line is input, and the input is ~DN.
This is the output after the filling process.

Text/shapes are inverted black and white (black text on a white background/
In contrast to normal graphics, there is one in which white characters/figures are used on a black background.The filling circuit in this case is shown in FIG. In this case, a group of N exclusive OR gates EOR+ for black-and-white inversion is placed before EXOR and ~EXORN in Figure 1.
+~EORMI, and later for black and white inversion (for restoration)
N exclusive OR gate groups EOR, , ~EOR, □ are added.

[Effect]

With this circuit, the judgment bit D divided into N bits each
Q, -Q, obtained by correctly filling out r to D, can be quickly output.

To explain this in detail with reference to FIG. 3 assuming N=8, the inputs D1 to D7 in FIG. 1 are 00 in FIG. 3(a)1.
100000, and the output C6 of the latch circuit LT is initially cleared to 0, so the outputs Q1 to QN are as shown in Figure 3 (
b) [ becomes 00111111. That is, D1=0, C
If 0=0, then Ql=o and Dz=0. If Q1=0 then Q2
=0. However, since D=1, if Q2=0, then Q3
=t, and if Q3=l, then D4=0 and Q4=1. Similarly, if D5 to D are O, Q and Q8 are l. This Qs=t is taken into the latch circuit L'.

Next, when the processing unit 10110000 of FIG. 3(a) 11 is input as D I-D s, Q, -Q,
b>n<00100000. That is, D.

= 1 and C0 = 1, so Q+ = o, D z =
0, and since Q1=0, Q2=0, D3==1, and Q2=0, so Q3=1. D4=l and Q-1
Therefore, Q4=0, D,=0, and Q,=0, so Q,=O, and so on, so that Q6 to Q,=0.

Next, when the processing unit 0100IO00 of FIG. 3(a) I[[ is input as D1 to D8, Q1 to Q8 are
) I[[becomes 01110000. That is, D1=0
And since C0=0, Q,=0. D2=1 or Q=0
Therefore, Q2=1. Since D3=O and Qz=t, Q3=l, D,=0 and Q:l=1, so Q,=
1, D5=1 and Q,=1, so Q,=0, and so on, so that Q6 to Q,=0.

Obviously, Figure 3 (b) is the result of filling in the spaces between the 1's in Figure 4 (a) with 1's, more specifically, from the first (odd numbered) 1 to just before the next (even numbered) 1, it is filled in with 1's. The dots are filled in between the outline dots. As shown in Fig. 6, the OR gates Gt~G,l are not required, and instead of using the contour dots themselves as shown in Fig. 6, the discrimination dots generated from them are used, and these dots are always paired. Therefore, it does not end at an odd number, and therefore, there is no possibility of the error of filling in from the odd number to the end of the character/graphic area. Also, since it is a simultaneous process in hardware, it does not take much time to process, unlike sequential processing in software.

The circuit shown in FIG. 2 can similarly perform accurate and rapid filling processing. To explain this in detail with reference to FIGS. 3(C) to (f), now the input data in FIG. 2 (discrimination data generated for the contour points of the black and white inverted image) D I I ~
If D N I is 11011111 in FIG. 3(C) I, then if the black and white inversion control signal S is 1 (reversal instruction), the outputs of the black and white inversion exclusive OR gates EOR,, ~EOR,, and ~D are the Figure 3 (d) becomes I.

This is the same as (a) I in the same figure, and is the same as the discrimination point used for the contour point of a normal (black and white non-inverted) image. This corresponds to the next N focus inputs D11 to D□, that is, Fig. 3 (C
) II, (C) III, . Discrimination bit D+ ~D returned to this non-inverted one, Nikki EXORI""EXORN
T: If the filling process is performed, the outputs Q1 to Q obtained are as shown in I, U, and II in Fig. 3(e), and this is as shown in the same figure (
b) No.1. 11. Same as III. When this is inverted using exclusive OR gates EOR, 2 to EORN□ for black and white inversion, I and II in the same figure (f) are obtained.

It becomes like ■. This shows a white filled figure on a black background.

Figure 4 (a) shows black letters/figures on a white background, and Figure 4 (b)
) represents white characters/figures on a black background (of course, white/black can also be red/yellow, etc., and refers to a binary image and its inverted image), and the outline pattern data of the inverted image in Fig. 4(b) are contour points P1 and P2. P3 and P (the others are the same) are represented by O, and the others are represented by l. This contour point P, and P z, P 3
Filling in the space between and P4 with 0 is the filling process for the inverted image, and as is clear from comparing FIGS. 3(C) and 3(f), this filling process is certainly performed.

〔Example〕

FIG. 5 shows an embodiment of the present invention. 12 is a contour information input circuit, 14 is a discrimination bit extraction circuit, 16 is a memory, 18
2 is a discrimination bit reading circuit, 20 is a filling circuit shown in FIGS. 1 and 2, 22 is a writing circuit, and 24 is a memory.

When the contour information shown in FIG. 7(b) is input to the contour information input circuit 12, the discrimination bit extraction circuit 14 uses the discrimination bits lJ+t, Jz□, etc. shown in FIG. 7(d) from this input. and write these to the memory 16. The stored contents of the memory 16 may be conceptually the same as shown in FIG. 7(d) (considering a two-dimensional dot array, the discrimination bits Jz, Jz+
,...The corresponding dot is 1, other dots are 0, 2
dimensional pattern). The two-dimensional dot pattern in the memory 16 is read out by the discriminating biro sales circuit 18 in a television scan manner, and each N-bit processing unit is sequentially input to the contour filling circuit 20. The circuit 20 performs the above-mentioned filling process and outputs Q, , Q, . . .
Q, and the write circuit 22 writes it into the memory 24 in the same television scan manner. As a result, the filled image dot pattern shown in FIG. 7(a) is stored in the memory 24. Of course, the characters/figures to be filled out are not limited to the figures shown in FIG. If the image is a black and white inverted image, the filled-in image is stored in the memory 24.

In the circuit shown in Figure 2, when the black and white inversion control signal S is set to 0, the exclusive OR gate E OR+ r~FOR, , EOR1□
~EOR, □ is through, so the circuit shown in FIG. 2 can also fill in black and white non-inverted images.

The method for forming discrimination dots from outline dots is described in Japanese Patent Application Laid-open No. 1983
-305478, and a part of it will be explained with reference to FIG. 8. Pi, P, , Pk indicate three adjacent dots among the contour dots. Each has X, Y coordinates, the X, Y coordinates of P are X,,Y,, those of PJ are X,,Y,P
, are Xk and Yk.

dX+=Xt Xl dVI=yi Yj+ dx
2=xJ In Fig. 8(a), if we follow the direction of the arrow, at the contour point PJ, dXl, d, and □ are zero, but dyl,
dy2 is negative, and in this case, the discriminant point (indicated by an x mark) is P
Put it on top of 1.

In FIG. 8(b), dVI+dy2 is positive, and in this case, a discrimination point is placed to the right of the I dot of P.

In Fig. 8(C), the direction to be traced is the direction coming from the top and bending to the left.In this case, a discrimination point is placed one dot to the right of the bending point Pj, and in Fig. 8(d), the direction is coming from the bottom and bending to the right. This is the direction of bending, and in this case, a discrimination point is attached to the bending point PJ. In addition, in Fig. 8(e), the direction is coming from the left and downward, in this case, a discrimination point is placed to the right of the i-dot of the contour point P, and in Fig. 8(f), the direction is coming from the right and upward. Therefore, in this case, a discrimination point is attached to P.

In Fig. 8 (g), it comes from below and turns downwards, and in this case, a discrimination point is placed at turning point P4 and one dot to the right of it.
In the figure (h), the dot comes from above and turns back upwards, and in this case, a turning point P and a discrimination point are placed to the right of that dot.

Also, in Figure 8 (i), it comes from the right and turns back to the right. In this case, a discrimination point is attached to the turning point PJ, and
In this case, since it comes from the left and turns back to the left, in this case, a discrimination point is placed one dot to the right of the turning point PJ. Furthermore, in Figure 8 0<), it comes from the lower left and turns back to the lower left.
In this case, a turning point P and a discrimination point are placed one dot to the right of the turning point P.

In the table above, in this case (k), the decision point is set by process (2).

The discriminant points J1 and J in Fig. 7(d) are determined by the rule of Fig. 8 (Tue), the discriminant point J41 is determined by the rule of Fig. 8(b), and the discriminant point J31 is determined by the rule of Fig. 8(j). ) is generated according to the rule of .Contour points arranged in the horizontal direction (main scanning direction during filling processing) generate discriminant points only at the left and right ends, and do not generate discriminant points at intermediate points.Therefore, as shown in Fig. 7 (CC) There is no discrimination point at the contour point between DS+D6. Regarding the contour point D5, see FIG.
The discrimination point JSI is generated according to the + rule, and the discrimination point J6 is generated using a rule not shown in Figure 8 (the generation rule for the discrimination point attached to the bending point when coming from the right and proceeding to the upper left, the rule in the table above) ) is attached to the position of contour point D6. E7 in FIG. 7(d) is an end point of a group of contour points lined up in the horizontal direction, but since the forward movement direction is downward to the right and the following movement direction is to the right, the process (2) in the table above is applied. , no discrimination points are attached. As for the contour point to the right of E7, first the leading and following movement directions are rightward and rightward, and then (on the return) leftward and leftward, so the processing in the table above is applied, and the discrimination point is attached. I can't do it.

Note that since the determination point is set exclusively, it will be deleted if it is set an even number of times.

[Effects of the Invention] As described above, according to the present invention, it is possible to quickly and reliably fill in a contour point area without causing any errors, and the circuit configuration is also simple.

[Brief explanation of drawings]

Figures 1 and 2 are principle diagrams of the present invention 1.2, Figure 3 is an explanatory diagram of the operation of Figures 1 and 2, Figure 4 is an illustration of inverted/non-inverted images, and Figure 5 is FIG. 6 is a block diagram showing an embodiment of the present invention, FIG. 6 is a circuit diagram showing a conventional example, FIG. 7 is an explanatory diagram of discriminant points, and FIG. 8 is an explanatory diagram of a discriminant point generation procedure. In Figures 1 and 2, EXOR, ~EXORN are exclusive OR gates for filling, EOR, ~EORN are exclusive OR gates for black and white inversion, EOR, □~EOR, □ are exclusive OR gates for black and white inversion, D, ~DN is the number of N discrimination bits, and Q1~QN are the outputs after the filling process. Applicant: Fujitsu Limited

Claims (1)

[Claims] 1. A plurality of (N) exclusive OR gates (EXOR_1 to E
XOR_N) and one latch circuit (LT), and is set at the first dot position of the contour dot or contour dot group of the odd-numbered image detected in the scanning direction, and the contour dot detected even-numbered. Alternatively, a plurality (N) pieces of pattern data each having a discrimination bit set at a position one dot after the last dot of the outline dot group are input to one of the exclusive OR gates (EXOR_1 to EXOR_N), and the latch The output of the circuit and the output of the previous stage exclusive OR gate are used as the other inputs, and the final stage exclusive OR gate (EXOR_N
) is input as the other input of the first-stage exclusive OR gate (EXOR_1) when the next discrimination bit is input, and the outputs (Q_1 to Q_N) of these exclusive OR gates (EXOR_1 to EXOR_N) are input to the input discrimination bits (D_1 to D_
A contour filling circuit characterized in that it is an output after filling for N). 2. A plurality of (N) exclusive OR gates for black and white inversion (EOR_1_1 to EOR_N_1),
Exclusive OR gate for filling (EXOR_1 to EXOR_
N), and exclusive OR gate for black and white inversion (EOR_1_
2 to EOR_N_2) and one latch circuit (LT), which is set at the first dot position of the contour dot or group of contour dots of the black and white inverted image detected oddly in the scanning direction,
Further, a plurality (N) pieces of pattern data each having a discrimination bit set at a position one dot after the last dot of the even-numbered detected contour dot or group of contour dots are transferred to the black-and-white inversion exclusive OR gate. is used as one input of the exclusive OR gate for filling, the output of the latch circuit and the output of the previous stage exclusive OR gate are used as the other input, and the final stage exclusive OR gate (EXOR_N) is connected to the latch circuit.
) is input to the other input of the first-stage exclusive OR gate (EXOR_1) when the next discrimination bit is input, and these filling exclusive OR gates (EXOR_1 to EXOR
_N) outputs (Q_1 to Q_N) through black and white inversion exclusive OR gates (EOR_1_2 to EOR_N_2).