JPH03220915A - A/d converter - Google Patents
A/d converterInfo
- Publication number
- JPH03220915A JPH03220915A JP1695290A JP1695290A JPH03220915A JP H03220915 A JPH03220915 A JP H03220915A JP 1695290 A JP1695290 A JP 1695290A JP 1695290 A JP1695290 A JP 1695290A JP H03220915 A JPH03220915 A JP H03220915A
- Authority
- JP
- Japan
- Prior art keywords
- switch
- converter
- input
- arithmetic section
- digital value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims description 9
- 230000005856 abnormality Effects 0.000 abstract description 12
- 238000006243 chemical reaction Methods 0.000 description 13
- 230000002159 abnormal effect Effects 0.000 description 4
- 238000001514 detection method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- WYROLENTHWJFLR-ACLDMZEESA-N queuine Chemical compound C1=2C(=O)NC(N)=NC=2NC=C1CN[C@H]1C=C[C@H](O)[C@@H]1O WYROLENTHWJFLR-ACLDMZEESA-N 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この考案は、電子制御装置に用いられるアナログ信号入
力回路の異常検出回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to an abnormality detection circuit for an analog signal input circuit used in an electronic control device.
第２図は従来のＡ／Ｄ変換回路の回路図であり、図にお
いて、（ＩＡ）（ＩＢ）は外部アナログ信号、（２Ａ）
（２Ｂ）は入力抵抗、（３Ａ）（３Ｂ）、（４Ａ）（４
Ｂ） はノイズ防止用Ｊこ設置すられだ抵抗とコンデ
ンサによるフィルタ回路、（５Ａ）（５Ｂ）は多点入力
の場合の入力信号選択スイッチ、（６）は信号レベルを
変換するためのアンプ回路、（７）はアナログ信号から
デジタル信号に変溪するＡ／Ｄ変換器である。（８）は
Ａ／Ｄｆ換器（７）の出力であるディジタル信号が入力
さｎる演算部、Ｍは上記（ＩＡ）〜（５Ａ）から構成さ
ｎた１回路のみか、もしくは（ＩＢ）〜（５Ｂ）で構成
さ刺たもう１回路かもしくはそれ以上の回路とアンプ回
路（６）とＡ／Ｄ変換器（７）より構成されたＡ／Ｄ変
換カード、（ＩＩＡ）（ＩＩＢ）は外部アナログ信号（
ＩＡ）（ＩＢ）をＡ／Ｂｆ換カードＱＱに伝送する配線
である。Figure 2 is a circuit diagram of a conventional A/D conversion circuit. In the figure, (IA) (IB) are external analog signals, (2A)
(2B) is the input resistance, (3A) (3B), (4A) (4
B) is a filter circuit with a resistor and capacitor installed for noise prevention, (5A) (5B) is an input signal selection switch for multi-point input, and (6) is an amplifier circuit for converting the signal level. , (7) is an A/D converter that converts an analog signal into a digital signal. (8) is an arithmetic unit into which the digital signal that is the output of the A/Df converter (7) is input, and M is only one circuit consisting of (IA) to (5A) above, or (IB). An A/D conversion card (IIA) (IIB) consisting of one or more circuits consisting of ~ (5B), an amplifier circuit (6), and an A/D converter (7) External analog signal (
This is the wiring that transmits IA) (IB) to the A/Bf conversion card QQ.
次に動作について説明する。Next, the operation will be explained.
外部のアナログ信号（ＩＡ）は入力信号選択スイッチ（
５Ａ）がＯＮ４．た場合、入力抵抗（２Ａ）で終端され
、入力抵抗（２Ａ） 、抵抗（３Ａ）及びコンデンサ（
４Ａ〉で構成されたフィルタ回路（ノイズ除去用）を通
りスイッチ（５Ａ）を経てアンプ回路（６）に接続さハ
る。アンプ回路（６）によりこの信号はＡ／Ｄ変換器（
７）の入力信号レベルまでｉｔさハ、Ａ／Ｄ変換器（７
）でアナログ信号からデジタル信号に変換され演算部（
８）に入力さ力る。もし、この回路ｌこおいて異常が発
生した場合、Ａ／Ｄ変＃器（７）のデジタル信号喰は正
常な場合の信号値とは異なってくる。例えば、アナログ
信号（ＩＡ）からの配線（ｌ ＩＡ） が′断線しＴ
コリ、入力信号選択スイッチ（５Ａ）がＯＮＩ、ない故
障状態の場合はアンプ回路（６）の入力信号が０ＣＶ）
となり、Ａ／Ｄ変換器（７）のデジタル信号値はアナロ
グ入力信号０〉がＯ（■の場合の値と同じになる。アナ
ログ信号（ＩＢ）がＡ／Ｄ変換器（７ンでＡ／Ｄｇ換さ
れる動作についても同様である。The external analog signal (IA) can be selected using the input signal selection switch (
5A) is ON4. In this case, it is terminated with an input resistor (2A), an input resistor (2A), a resistor (3A) and a capacitor (
It passes through a filter circuit (for noise removal) composed of 4A> and is connected to an amplifier circuit (6) via a switch (5A). The amplifier circuit (6) converts this signal into an A/D converter (
7) until it reaches the input signal level of the A/D converter (7).
) converts the analog signal into a digital signal and sends it to the arithmetic unit (
8). If an abnormality occurs in this circuit, the digital signal value of the A/D converter (7) will differ from the signal value in the normal case. For example, the wiring (l IA) from the analog signal (IA) is disconnected.
If the input signal selection switch (5A) is ONI or not, the input signal of the amplifier circuit (6) is 0CV)
Therefore, the digital signal value of the A/D converter (7) is the same as the value when the analog input signal 0> is O (■. The same applies to the operation of Dg conversion.
また、同様にアンプ回路（６）やＡ／Ｄ変換器（７）自
身が異常になった場合も、Ａ／Ｄ変換器（７）は真のデ
ータと異なるデジタル信号を出力してしまう。Similarly, if the amplifier circuit (6) or the A/D converter (7) itself becomes abnormal, the A/D converter (7) will output a digital signal different from true data.
Ｃ発明が解決しようとするＩａ題〕
従来のＡ／Ｄ変換装置は以上のように償成さハていＴこ
Ｔこめ、回路に異常があった場合デジタル信号値は変化
するが、その変化が実際のアナログ入力信号の変化によ
るものか、回路異常によるものが判別できないという課
題がめっｔこ。Problem Ia to be solved by the invention C] Conventional A/D converters are constructed as described above, and when there is an abnormality in the circuit, the digital signal value changes, but the change is A real problem is that it is not possible to determine whether the problem is due to a change in the actual analog input signal or a circuit abnormality.
この考案は上記のようなＲ題を解消するγこめになさｔ
またもので、アナログ入力回路の異常を検出できるＡ／
Ｄ変換装置を得ることを目的とする。This idea was designed to solve the R problem mentioned above.
It is also an A/A that can detect abnormalities in analog input circuits.
The purpose is to obtain a D conversion device.
この発明に係るアナログ変換装置は、外部アナログ信号
を終端する入力抵抗と、この入力抵抗に接続されたＲ−
Ｃフィルタと、アナログ信号をディジタル信号に変換す
るＡ／Ｄ変換器とこのＡ／Ｄ変羨器と上記Ｒ−Ｃフィル
タとを接続するか否かを決定する第１のスイッチと、こ
のＡ／Ｄ変換器のディジタル信号が入力される演算部と
、上記入力抵抗、上記Ｒ−Ｃフィルタのコンデンサある
いはＡ／Ｄ変換器の入力端のいす力かに並列接続された
基準電源と第２のスイッチとの直列回路を備えたもので
ある。The analog conversion device according to the present invention includes an input resistor that terminates an external analog signal, and an R-
C filter, an A/D converter that converts an analog signal into a digital signal, a first switch that determines whether or not to connect the A/D converter and the R-C filter, and this A/D converter. A calculation unit into which a digital signal of the D converter is input, a reference power supply and a second switch connected in parallel to the input resistor, the capacitor of the R-C filter, or the chair at the input end of the A/D converter. It is equipped with a series circuit with.
この発明における基準源と第２スイツチの直列回路は、
この第２のスイッチにより基準電源がＡ／Ｄ変換回路に
接続され、基準電源電圧がディジタル信号値に変換され
洩算部に入力さ力る。上記第２のスイッチがオンの状態
のとき演算部に入力されたテ′イジタル値が基準電源電
圧相当のディジタル値か否かが演算部で判′定されるこ
とによりＡ／Ｄ変換器が正常か否かが判定され、上記第
２のスイッチがオンの状態からオフの状態へ移行した直
後演算部に入力されたディジタル値が基準電源電圧相当
のディジタル値か否かが演算部で判定されることにより
第１のスイッチが正常か否かが判定され、上記Ｍ２のス
イッチがオンの状態からオフの状態へ移行して一定時間
後に演算部に入力されたディジタル値が入力抵抗とＲ−
Ｃフィルタとにより決定されるとき定数に従った基準電
源電圧の減衰価相当のディジタル値か否かが演算部で判
定されるととｊこより外熱配線が断線か否かが判定さハ
る。The series circuit of the reference source and the second switch in this invention is as follows:
The second switch connects the reference power supply to the A/D conversion circuit, converts the reference power supply voltage into a digital signal value, and inputs the digital signal value to the leakage calculator. When the second switch is on, the A/D converter operates normally by determining whether the digital value input to the arithmetic unit is a digital value equivalent to the reference power supply voltage. Immediately after the second switch shifts from the on state to the off state, the arithmetic unit determines whether the digital value input to the arithmetic unit is a digital value equivalent to the reference power supply voltage. By this, it is determined whether the first switch is normal or not, and after a certain period of time after the switch M2 shifts from the on state to the off state, the digital value input to the arithmetic unit is equal to the input resistance and R-
When the arithmetic unit determines whether the digital value corresponds to the attenuation value of the reference power supply voltage according to the constant determined by the C filter, it is determined from this whether or not the external heat wiring is disconnected.
以下、この考案の一実施例を図について説明する。第１
図において、（ＩＡ）〜（５Ａ）、（ＩＢ）〜（５Ｂ）
（６） （７１（８） ＱＱ （１１Ａ） （１１Ｂ）
については、従来技術と全く同じである。Ｃ！υと
−が今曲の考案を実現するｒこめに設けられた部品で２
１１は基Ｑ！電圧を発生する基準電源、れは基準電激０
１１をアンプ回路（６）の入力部に接続したり切離した
りするだめのスイッチである。An embodiment of this invention will be described below with reference to the drawings. 1st
In the figure, (IA) to (5A), (IB) to (5B)
(6) (71(8) QQ (11A) (11B)
This is exactly the same as the conventional technology. C! υ and - are the parts installed in the r temple that realize the idea of this song.
11 is base Q! The reference power supply that generates the voltage, this is the reference voltage 0
This is a switch for connecting and disconnecting 11 from the input section of the amplifier circuit (6).
次に動作について説明する。Next, the operation will be explained.
基準電源入力回路のスイッチムがオフの状態ではＡ／Ｄ
変換カードＱ［Ｉは従来のＡ／Ｄ変換回路と全く同じ回
路となり、外部アナログ信号（ＩＡ）又は（ＩＢ）をデ
ジタル信号に変換する回路として働く。外部アナログ信
号（ＩＡ）に関する回路について説明する。回路の異常
検出は、まず基準電源入力回路のスイッチのをオンしだ
状態で行われる。入力信号選択スイッチ（５Ａ）入ｔび
（５Ｂ）をオフにする。このときアンプ回路（６）の入
力ｌこは基準＊ ｍ ａｖの電圧がかかり、Ａ／Ｄ変換
器（７）によりデジタル信号に変襲される。When the switch of the reference power input circuit is off, the A/D
The conversion card Q[I is exactly the same circuit as a conventional A/D conversion circuit, and works as a circuit that converts an external analog signal (IA) or (IB) into a digital signal. A circuit related to an external analog signal (IA) will be explained. Circuit abnormality detection is first performed with the reference power input circuit switch turned on. Turn input signal selection switch (5A) on and turn off (5B). At this time, a voltage of reference *m av is applied to the input l of the amplifier circuit (6), which is converted into a digital signal by the A/D converter (7).
演瞭部（８）により、この時のデジタル信８１ｉが理論
値と比較されアンプ回路（６）とＡ／Ｄ変換器（７）が
正常かどうかが判定されろ。次に、入力信号選択スイッ
チ（５Ｂ）をオフ、入力信号選択スイッチ（５Ａ）をオ
ンにしｒこ場合、コンデンサ（４Ａ）轟ζは基準電源Ｑ
υの電圧が充電さｎる。この状態でスイノチムをオフに
してＡ／Ｄ変換を行い、スイッチ色がオフされた匝後の
ディジタル信号値及びスイノチムがオフされて一定時間
後のデジタル信号値の各々が演算部（８）により判定さ
れることにより入力信号選択スイッチ（５Ａ）の異常や
、外部アナログ信号の断線状態が検出される。表１に上
記で述べたチエツク内容及びその結果による正常部分、
異常部分の判定結果の内＠を示す。外部アナログ信号（
ＩＢ） ｓこ関する回路のチエツクについても同様であ
る。The digital signal 81i at this time is compared with the theoretical value by the rendering section (8) to determine whether the amplifier circuit (6) and the A/D converter (7) are normal. Next, turn off the input signal selection switch (5B) and turn on the input signal selection switch (5A).In this case, the capacitor (4A) Todoroki ζ is connected to the reference power supply Q
A voltage of υ is charged. In this state, Suinochim is turned off and A/D conversion is performed, and the digital signal value after the switch color is turned off and the digital signal value after a certain period of time after Suinochim is turned off are determined by the calculation unit (8). As a result, an abnormality in the input signal selection switch (5A) or a disconnection state of the external analog signal is detected. Table 1 shows the above-mentioned check contents and the normal parts according to the results.
Indicates @ in the judgment result of the abnormal part. External analog signal (
The same goes for checking the circuits related to IB).
なお、上記実施例では入力抵抗、抵抗とコンデンサによ
り形成されるフィルタ回路、及び入力信号選択スイッチ
により構成さ創る入力回路は（２Ａ）〜（５Ａ）及び（
２Ｂ）〜（５Ｂ）の２回路の例を示したが１回路でも３
回路以上でも同様の機能を実塩できる。又、基準電源入
力回路Ｑ１１■をアンプ回路（６）の入力部に設けたも
のを示したが、入力抵抗（ＩＡ）（ＩＢ）あるいはコン
デンサ（４Ａ）（４Ｂ）と並列にそれぞれ設けても艮く
、又、Ａ／ Ｄｆ挑器の性能が充分高くてアンプ回路（
６）を必要としない場合は、Ａ／Ｄ変換器（７）の前に
設けても同様の機能を実現させることができる。In the above embodiment, the input circuits (2A) to (5A) and (5A) are composed of an input resistor, a filter circuit formed by a resistor and a capacitor, and an input signal selection switch.
Although we have shown examples of two circuits (2B) to (5B), even one circuit is 3
Similar functions can be realized even in circuits and beyond. Also, although the reference power input circuit Q11■ is shown as being provided at the input section of the amplifier circuit (6), it is also possible to provide it in parallel with the input resistors (IA) (IB) or capacitors (4A) (4B). Also, the performance of the A/Df challenger is sufficiently high that the amplifier circuit (
6) is not required, the same function can be achieved even if it is provided before the A/D converter (7).
また、入力信号選択スイッチ（５Ａ）（５Ｂ）及びスイ
ッチ■はメカニカルスイッチを用いたものを示したが半
導体スイッチでもよく、また基準電源＋２１１は電圧を
設定できるものであればどのようなものでも同様の効果
を実する。なお、演算部（８）により検出された異常部
分を図示しない表示手段で表示することにより異常部品
の交換もしくはＡ／Ｄ変換カードの交換が容易に行える
番
ことは言うまでもない。In addition, although the input signal selection switches (5A) (5B) and switch ■ are shown as using mechanical switches, semiconductor switches may also be used, and the reference power supply +211 may be of any type as long as the voltage can be set. achieve the effect of It goes without saying that by displaying the abnormal parts detected by the calculation section (8) on a display means (not shown), the abnormal parts or the A/D conversion card can be easily replaced.
以上のように、この発明によればＡ／Ｄ変換装島に外部
アナログ信号を終端する入力抵抗とこの入力抵抗ｌこ接
続されｆこＲ−Ｃフィルタと。As described above, according to the present invention, an input resistor for terminating an external analog signal is connected to an A/D converter, and an RC filter is connected to the input resistor.
アナログ信号をディジタル信号に変換するＡ／Ｄｉｄ換
器と、このＡ／Ｄ変換器と上記Ｒ−Ｃフィルタとを接続
するか否かを決定する第１のスイッチと、このＡ／Ｄ変
し器のディジタル信号が入力さハる演算部と、上記入力
抵抗、上記Ｒ−ＣフィルタのコンデンサあるいはＡ／Ｄ
ｉｌｌｉ器の入力端のいずれかに並列接続された基準電
源と第２のスイッチとの直列回路を備えたのでＡ／Ｄ変
換器の異常、入力信号選択スイッチの異常あるいは外部
配線の異常を検出する効果がある。まＴこ、この異常検
出の効果により不良カードの交換も容易に行うことがで
きろ効果が得ら力ろ。An A/D converter that converts an analog signal into a digital signal, a first switch that determines whether or not to connect the A/D converter and the R-C filter, and the A/D converter. a calculation unit into which a digital signal is input, the input resistor, the capacitor of the R-C filter, or the A/D
Equipped with a series circuit of a reference power supply and a second switch connected in parallel to one of the input terminals of the illumination device, it is possible to detect abnormalities in the A/D converter, input signal selection switch, or external wiring. effective. Well, the effect of this abnormality detection makes it easier to replace defective cards.
第１図はこの考案の一実施例によるＡ／Ｄ変換回路の回
路図、第２図は従来のＡ／Ｄ変換回路の回路図である。
（ＩＡ）（ＩＢ） は外部アナログ信号、（２Ａ）（
２Ｂ）は抵抗、（３Ａ）（３Ｂ）は抵抗、（４Ａ）（４
Ｂ）はコンデンサ、（５Ａ）（５Ｂ）は久方選択スイッ
チ、（６］はアンプ回路、（７）はＡ／Ｄ変裂器、Ｑｌ
は基準電源のはスイッチを示す。
なわ、図中、同一符号は向−１または相当部分を示す。FIG. 1 is a circuit diagram of an A/D conversion circuit according to an embodiment of this invention, and FIG. 2 is a circuit diagram of a conventional A/D conversion circuit. (IA) (IB) are external analog signals, (2A) (
2B) is a resistance, (3A) (3B) is a resistance, (4A) (4
B) is a capacitor, (5A) (5B) is a Kugata selection switch, (6] is an amplifier circuit, (7) is an A/D converter, Ql
indicates the reference power supply switch. In the figures, the same reference numerals indicate direction-1 or corresponding parts.
Claims (1)
に接続されたＲ−Ｃフィルタとアナログ信号をディジタ
ル信号に変換するＡ／Ｄ変換器と、このＡ／Ｄ変換器と
上記Ｒ−Ｃフィルタとを接続するか否かを決定する第１
のスイッチと、このＡ／Ｄ変換器のディジタル信号が入
力される演算部と、上記入力抵抗、上記Ｒ−Ｃフィルタ
のコンデンサあるいはＡ／Ｄ変換器の入力端のいずれか
に並列接続された基準電源と第２のスイッチとの直列回
路を備えたＡ／Ｄ変換装置。An input resistor that terminates an external analog signal, an R-C filter connected to this input resistor, an A/D converter that converts the analog signal into a digital signal, and this A/D converter and the above-mentioned R-C filter. The first step is to decide whether or not to connect
a switch, an arithmetic unit into which the digital signal of the A/D converter is input, and a reference connected in parallel to either the input resistor, the capacitor of the R-C filter, or the input terminal of the A/D converter. An A/D converter including a series circuit of a power source and a second switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016952A JP2546005B2 (en) | 1990-01-26 | 1990-01-26 | A / D converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016952A JP2546005B2 (en) | 1990-01-26 | 1990-01-26 | A / D converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03220915A true JPH03220915A (en) | 1991-09-30 |
| JP2546005B2 JP2546005B2 (en) | 1996-10-23 |
Family
ID=11930460
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016952A Expired - Fee Related JP2546005B2 (en) | 1990-01-26 | 1990-01-26 | A / D converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2546005B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07230319A (en) * | 1994-02-18 | 1995-08-29 | Shimaden:Kk | Detecting method for wiring abnormality of servo controller system |
| JP2006345237A (en) * | 2005-06-09 | 2006-12-21 | Matsushita Electric Ind Co Ltd | Sensor signal processing circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57196619A (en) * | 1981-05-29 | 1982-12-02 | Hitachi Ltd | Failure diagnostic system for analog-to-digital converter |
| JPS63301625A (en) * | 1987-06-01 | 1988-12-08 | Nippon Denso Co Ltd | A/d converting device |
-
1990
- 1990-01-26 JP JP2016952A patent/JP2546005B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57196619A (en) * | 1981-05-29 | 1982-12-02 | Hitachi Ltd | Failure diagnostic system for analog-to-digital converter |
| JPS63301625A (en) * | 1987-06-01 | 1988-12-08 | Nippon Denso Co Ltd | A/d converting device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07230319A (en) * | 1994-02-18 | 1995-08-29 | Shimaden:Kk | Detecting method for wiring abnormality of servo controller system |
| JP2006345237A (en) * | 2005-06-09 | 2006-12-21 | Matsushita Electric Ind Co Ltd | Sensor signal processing circuit |
| JP4687256B2 (en) * | 2005-06-09 | 2011-05-25 | パナソニック株式会社 | Sensor signal processing circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2546005B2 (en) | 1996-10-23 |
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