JPH0321719U - - Google Patents
Info
- Publication number
- JPH0321719U JPH0321719U JP8219789U JP8219789U JPH0321719U JP H0321719 U JPH0321719 U JP H0321719U JP 8219789 U JP8219789 U JP 8219789U JP 8219789 U JP8219789 U JP 8219789U JP H0321719 U JPH0321719 U JP H0321719U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- counter
- circuit
- converter
- correction circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
Description
第１図は本案の一実施例の構成図、第２図は第
１図の主要部の信号を示した図である。
１……サンプル信号回路、２……レフアレンス
信号回路、３……対数回路、４……加算器、５…
…平滑回路、６……ゼロ検知回路、７……ＢＧ信
号レベル判断回路、８……基準電圧源、９……計
数上下制御回路、１０……下位計数器、１１……
中位計数器、１２……上位計数器、１３……下位
ＤＡ変換器、１４……中位ＤＡ変換器、１５……
上位ＤＡ変換器、１６……加算器出力信号、１７
……上位計数信号、１８……中位計数信号、１９
……下位計数信号。
FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a diagram showing signals of the main parts of FIG. 1. 1... Sample signal circuit, 2... Reference signal circuit, 3... Logarithm circuit, 4... Adder, 5...
... Smoothing circuit, 6 ... Zero detection circuit, 7 ... BG signal level judgment circuit, 8 ... Reference voltage source, 9 ... Counting up/down control circuit, 10 ... Lower counter, 11 ...
Intermediate counter, 12... Upper counter, 13... Lower DA converter, 14... Intermediate DA converter, 15...
Upper DA converter, 16...Adder output signal, 17
...Upper count signal, 18...Medium count signal, 19
...lower count signal.
Claims (1)
する）と該ＢＧ信号と逆極性をもつ基準信号と該
基準信号のゲインを変化させて該ＢＧ信号に加算
する加算器と該加算器の出力がゼロであるか否か
を判断するゼロ判断回路と該ＢＧ信号レベルを判
断するＢＧ信号レベル判断回路から構成される自
動ゼロ補正回路。 ２ 第１項の自動ゼロ補正回路において、該基準
信号のゲインはＤＡ変換器と該ＤＡ変換器を制御
する計数器より構成し、計数器は複数個に分割さ
れており該ＢＧ信号レベル判断回路により適切な
計数器を動作させるようにしたことを特徴とする
自動ゼロ補正回路。[Claims for Utility Model Registration] 1. A background signal (hereinafter referred to as BG signal), a reference signal having a polarity opposite to that of the BG signal, and an adder that changes the gain of the reference signal and adds it to the BG signal. An automatic zero correction circuit comprising a zero determination circuit that determines whether the output of the adder is zero and a BG signal level determination circuit that determines the BG signal level. 2. In the automatic zero correction circuit of item 1, the gain of the reference signal is composed of a DA converter and a counter that controls the DA converter, the counter is divided into a plurality of pieces, and the BG signal level judgment circuit An automatic zero correction circuit characterized in that a counter is operated more appropriately.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8219789U JPH0321719U (en) | 1989-07-14 | 1989-07-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8219789U JPH0321719U (en) | 1989-07-14 | 1989-07-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0321719U true JPH0321719U (en) | 1991-03-05 |
Family
ID=31628792
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8219789U Pending JPH0321719U (en) | 1989-07-14 | 1989-07-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0321719U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006131280A (en) * | 2004-11-08 | 2006-05-25 | Showa Packs Kk | Multi-layer paper bag |
-
1989
- 1989-07-14 JP JP8219789U patent/JPH0321719U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006131280A (en) * | 2004-11-08 | 2006-05-25 | Showa Packs Kk | Multi-layer paper bag |