JPH03214770A - Semiconductor storage device and manufacture thereof - Google Patents

Abstract

PURPOSE:To cut down the turnaround time by a method wherein an insulating film is formed by ion-implantation process through electrodes and wiring layer connecting to semiconductor regions of a semiconductor element so as to electrically disconnect the semiconductor element from the electrode and wiring. CONSTITUTION:The title semiconductor memory is composed of a semiconductor element 2 formed on a semiconductor substrate 1, an insulating film 7 covering the semiconductor element 2 and having opening parts in the semiconductor regions 6 (source) 6' (drain) of the semiconductor element 2, a wiring layer 8 formed to be connected to the semiconductor regions 6, 6' through the intermediary of an opening on the insulating film 7 and another insulating film 13 formed by ion implantation process through the wiring layer 8 to electrically disconnect the semiconductor element 2 from the wiring layer 8. At this time, the title semiconductor memory is stocked in the state wherein the wiring layer 8 and a passivation film 9 are formed ready for starting the writing-in process. Through these procedures, the turnaround time can be cut down.

Description

[Detailed Description of the Invention] [Summary] The purpose of this invention is to provide a method for manufacturing a semiconductor device, particularly a mask ROM, using a contact hole programming method that can shorten turnaround time. - In a semiconductor memory device that stores information depending on the state of electrical connection or disconnection with wiring, a semiconductor element formed on a semiconductor substrate and a hole that covers the semiconductor element and is formed on one semiconductor region of the semiconductor element. an insulating film having an electrode/wiring layer formed on the insulating film so as to be connected to the semiconductor region via the opening part; and an insulating layer formed by implanting ions through the electrode/wiring layer so as to electrically disconnect the semiconductor element and the electrode/wiring layer. A method for manufacturing a semiconductor memory device that stores information in a connected or non-connected state includes a step of forming the semiconductor element, a step of forming an electrode/wiring layer connected to one semiconductor region of the semiconductor element, and a step of forming the semiconductor element. The method is characterized in that it includes a step of forming an insulating layer by implanting ions through the electrode/wiring layer and electrically disconnecting the semiconductor element from the electrode/wiring.

(Industrial Application Field) The present invention is applicable to semiconductor devices, particularly mask ROMs (Read
The present invention relates to a method of manufacturing a single memory.

Data is written during the wafer process
The OM is called a mask ROM (Mask ROM or MROM). There are three main types of mask ROM programming methods:

(1) Diffusion layer programming method (2) Ion implantation programming method (3) Contact hole programming method Among these, (1) diffusion layer programming method is a method of programming with a mask that defines the diffusion layer, and (2) The ion implantation programming method is a method of programming data by changing the threshold voltage of a memory transistor by channel ion implantation. Finally, the contact 1/hole programming method (3) is a method for programming data depending on the presence or absence of electrical connection between the drain region of the transistor and the bit line.

In the case of ROMs, the production of ROMs generally begins based on pattern codes (program data) provided by customers. The number of days from receiving an order from a customer to delivery is called turnaround time, and (1) and (2) above.
Among methods (3), method (3) contact hole programming is the most effective because it allows ion implantation to write data to ROM at the end of the wafer process compared to methods (1) and (2). Turnaround time is short. For this reason, (3) contact hole programming method 2 is generally adopted, but in order to respond to the sudden demands of customers, it is necessary to further shorten the turnaround time of the contact hole programming method.

[Conventional technology]

FIGS. 4(a) to 4(e) are cross-sectional views of essential parts for explaining an information writing process using a mask ROM using a conventional contact hole programming method.

See Figure 4(a).

In the figure, 1 is a silicon (Si) substrate, and a thin layer of silicon dioxide (SiO2) with a thickness of, for example, about 500 mm is coated on this surface.
A film 2 is formed. And LOGOS (Local
A filled oxide film 3 is formed using an oxidation of silicon method. Subsequently, a gate electrode 4 made of polysilicon and having a thickness of, for example, about 5,000 layers, which is to become a word line, is formed using a conventional method. Thereafter, by implanting arsenic ions (As'') 5 using the gate electrode 4 as a mask, a source region 6 and a drain region 6' are formed in the Si base layer 1, as shown in the figure.

See Figure 4(b).

Next, CVD (Chemicai VaporDep)
For example, the thickness is 500 mm using
A PSG film 7 of 0 to 7000 layers is formed on the surface.

Conventionally, products were manufactured up to this stage, kept in stock in this state, and when the pattern code was handed over from the customer, the writing process began. Data writing using the contact hole programming method distinguishes whether current flows through the transistor depending on the presence or absence of electrical connection between the drain region of the memory transistor and the bint line (B/L), and determines whether the transistor can operate (with contact) or not. (no contact), that is, "continuity" (hereinafter referred to as ○N), or "
It is determined whether there is "non-conduction" (hereinafter referred to as OFF). Now, FIG. 2(c) shows the 6 write steps of ON and OFF.

See Figure 4(C).

A resist film 10 having an opening having a width of, for example, about 2,000 layers and a thickness of, for example, about 8,000 layers is formed by a conventional method on the drain region 6' of the transistor that is turned on by the pattern code.

See Figure 4(d).

Then, using this resist film 10 as a mask, RIE (Reactive) is performed using, for example, a gas containing fluorine or chlorine.
When performing ion etching), the PSG film 7 and the SiO 2 film 2 under the opening are removed and the St
The drain region 6 in the substrate 1 is exposed.

See Figure 4(e).

Next, after removing the resist film 10 by a normal method, an aluminum (AI) film 8 to be a bit line is formed to a thickness of, for example, about 1.0 μm using a sputtering method, and then a PS film is formed.
Bassihesion TI#. 9. An example wafer of 5000 to 7000 A is formed by CVD and completed.

=7 In this way, since the drain region 6' of the transistor to be turned on and the bit line 8 are electrically connected, the transistor can be operated according to the pattern code. In addition, for transistors that are not to be activated, if the wiring is done as is without making a contact hole, the bit line and drain region are not electrically connected, so it can be turned off.
It can be done. In this way, the writing process based on pattern coating is completed.

[Problem to be solved by the invention]

As described above, in the conventional contact 1/hole programming method, products are manufactured up to the level shown in Figure 4(b) and stocked, and after receiving the pattern code from the customer, the drain area and bit line are connected based on the program data. The steps shown in FIGS. 4(C) to 4(e) were performed to determine whether or not to connect. However, the steps shown in FIGS. 4(c) to 4(e) took several days, and there were nine problems with prompt delivery in response to customer demands.

8. It is an object of the present invention to provide a mask ROM manufacturing method using a contact hole programming method that can solve the above problems and shorten the turnaround time.

[Means for Solving the Problems] The present invention provides a semiconductor memory device that stores information by electrically connecting or disconnecting a semiconductor element and an electrode/wiring. an insulating film that covers the semiconductor element and has an opening over one semiconductor region of the semiconductor element; and an electrode/wiring formed on the insulating film so as to be connected to the semiconductor region through the opening. and an insulating layer formed by implanting ions through the electrode/wiring layer so as to electrically disconnect the semiconductor element and the electrode/wiring layer. 9. A method for manufacturing a semiconductor memory device that stores information by forming or electrically connecting or disconnecting a semiconductor element and an electrode/wiring, the step of forming the semiconductor element; A step of forming an electrode/wiring layer connected to the semiconductor region, and forming an insulating layer by implanting ions through the electrode/wiring layer, connecting the semiconductor element and the electrode/wiring layer.
The method is characterized in that it includes a step of electrically disconnecting the wiring.

[Function] By using the present invention, the turnaround time can be reduced compared to the conventional method. This is because conventionally, the program is stored in the state shown in FIG. 4(b) before the bit line 8 is formed, and then the program code is submitted by the customer.
Opening the contact hole as shown in FIGS. 4(C) to (e),
Formed bit lines and panshidion films.

However, in the present invention, the wiring layer 8 and the bashing film 9
You can store it in a state where it has been formed until then, and then perform a write operation. That is, the write process of selectively implanting ions only in areas without contacts can be performed at the end of the wafer process, thereby shortening the turnaround time.

10 [Example] As explained in the section of the prior art, in the past, products up to the state shown in FIG. 4(b) were manufactured and kept in stock.

In comparison, the present invention involves opening a contact window, forming a wiring layer,
The device is manufactured to the state shown in FIG. 1(a) in which all the passivation film formation has been completed, and then it is rolled up. Here, the fabrication is performed so that all the source regions or drain regions are connected to the bit lines. The manufacturing process up to this point is
Basically, the process is exactly the same as each process of the prior art described above.

When the customer presents the program data, the program writing process starts from FIG. 1(a).

Therefore, turnaround time can be shortened. Next, a method for writing information after FIG. 1(a) will be explained using FIGS. 1(b) to 1(c).

See Figure 1(b).

A Sin21 1 film 11 having an opening is formed to a thickness of about 20 μm on the drain region 6′ of the transistor to be turned off by the pattern code by a normal method.

Note that a resist film may be used instead of this Si○2 film 11. However, even if a resist film is formed, Si02
Even if a film is formed, it is necessary that the film 11 be a film that can be used as an ion implantation blocking film during the ion implantation performed later and prevent the injection material from entering other than the openings. Next, ion implantation is performed using this SiCh film 11 as a mask. The injection conditions were 01 so that the peak of the injection material distribution passed through the badge-hesion film and the Vint line and reached the contact area.
Accelerating 6 ions 12 at a voltage of 1.0 MeV and a DOSE amount of I
X I Ocm-". As a result, contact 1.
An oxide of aluminum such as alumina (Al203), that is, an insulating layer 13 is formed in the portion.

As a result, the electrical connection between the drain region 6' and the aluminum bit line 8 is severed, and the transistor is rendered inoperable. In other words, it is possible to form an OFFJ state with no contact. Conversely, if the insulating layer 13 is not formed, that is, without ion implantation, it will be in an ONJ1 2 state with contact present. In the invention, all the connections between the source region or the drain region and the bit line are manufactured to the state of "contact 1, present ONJ", then they are stored, and by looking at the pattern code provided by the customer, "no contact, OFF. The writing operation, that is, ion implantation, is performed only partially.Therefore, the turnaround time is shortened compared to the conventional method.In addition, during ion implantation, it is necessary to form the insulating layer 13 at the position shown in the figure. To,
That is, if the implantation conditions are determined so that the peak of the implantation distribution will be at this point, it can be applied even if the thicknesses of the aluminum film 8 and PSGIII 9 are changed. Further, in this example, oxygen was used as the ion implantation species, but this is not limited to oxygen, and other elements may be selected as the ion implantation species as long as an insulating layer can be formed in the contact area between the bit line and the drain region. . For example, when polysilicon is used for the bin 1 and the line 8, nitrogen can be selected as the ion implantation species in addition to oxygen, and a nitride such as Si3N4 can be used as the insulating layer. In this way, the type of ion implantation can be selected depending on the materials used for the electrodes and wiring layers13. Finally, the SiCh film 11 is removed and the writing process is completed. Note that the SiCh film 1l may be left as is.

Although the figure shows the case where it is removed, silicon nitride (Si3Nx) or the like may be formed as a passivation film after removal. In this embodiment, the insulating layer 13 is formed on the drain region 6', but it may also be formed in the drain-in nodal region 6'. That is, the insulating layer 13 may be formed so that the bit line 8 and the drain region 6' are non-conductive. Further, in the present invention, the passivation film 9
Although the ion implantation is performed after manufacturing up to the aluminum film 8, the ion implantation may be performed after the aluminum film 8 has been formed. However, it is possible to shorten the turnaround time by forming a passivation film in advance and then applying the process.

Note that the present invention is not limited to memory elements using transistors, but can also be applied to a contact hole programming method for memory elements using diodes.

Finally, we will show what changes have occurred in the circuit according to the present invention. FIG. 2 is a sectional view, a plan view, and a circuit diagram in the state 14 of FIG. 1(a).

In the figure, the cross-sectional view shows the state of FIG. 1(a).

In this state, all transistors are turned on. Then, when writing, i.e., ion implantation, is performed, the result is as shown in FIG. FIG. 3 is a cross-sectional view, a plan view, and a circuit diagram in the state shown in FIG. 1(C). The sectional view of FIG. 3 shows the state of FIG. 1(c). Here, the transistors in the portions where the insulating layer 13 is formed and the contacts 14 are not made do not operate. That is, OF' F
become.

On the other hand, transistors without an insulating layer continue to operate as they are. Information can be written using the method described above.

〔Effect of the invention〕

As explained above, according to the present invention, the time from ROM writing to completion of the wafer process can be shortened to one day, so the turnaround time can also be shortened.

Therefore, it is possible to sufficiently respond to sudden requests from customers.

15 FIG. 1 is a cross-sectional view of a main part for explaining the information writing process using a mask ROM using the contact hole programming method of the present invention, and FIG. 2 is a cross-sectional view of the state shown in FIG. 1(a). A plan view and a circuit diagram; FIG. 3 is a cross-sectional view, a plan view, and a circuit diagram in the state shown in FIG. FIG.

In the figure, 6 6“ 7 8 Si substrate Si○2 film field oxide film gate electrode arsenic ion source area drain area diffusion layer psc membrane aluminum membrane 1 6-1 ? :PSG film 10; Resist film 11: SiO■ film 12: Oxygen ion 13: Insulating layer 14; Contact 17 Mouth=ko; 7s 2 cases fixed -3661

Claims (2)

[Claims] (1) In a semiconductor memory device that stores information depending on the electrical connection or disconnection between a semiconductor element and electrodes/wirings, a semiconductor element formed on a semiconductor substrate and a semiconductor element that covers the semiconductor element, an insulating film having an opening over one semiconductor region; an electrode/wiring layer formed on the insulating film so as to be connected to the semiconductor region through the opening;
A semiconductor memory device comprising: an insulating layer formed by implanting ions through the electrode/wiring layer so as to electrically disconnect the semiconductor element and the electrode/wiring layer. (2) In a method for manufacturing a semiconductor memory device that stores information by electrically connecting or disconnecting a semiconductor element and electrodes/wirings, the step of forming the semiconductor element;
A step of forming an electrode/wiring layer connected to one semiconductor region of the semiconductor element, and forming an insulating layer by implanting ions through the electrode/wiring layer to electrically connect the semiconductor element and the electrode/wiring. 1. A method of manufacturing a semiconductor memory device, comprising the steps of: