JPH03209994A - Subcarrier processing circuit - Google Patents

Abstract

PURPOSE:To always control carrier phase fluctuation and amplitude fluctuation by generating a first subcarrier obtained by synthesizing vector signals of a first and a second variable gain amplifiers, and a second subcarrier being 90 deg. out-of-phase therefrom, and supplying them to a first and a second amplifiers, respectively through a detector. CONSTITUTION:The output of a voltage control oscillator 10 is sent to a CR phase shifter 20, and the phase shifter 20 converts an input signal to two vector signals, and supplies them to a first and a second phase shifting amplifiers 21, 22. The amplifier 21 generates a first subcarrier (vector signal + or -(a-b)), and the amplifier 22 generates a second subcarrier (vector signal + or -b). These signals are subjected to vector synthesis so that they are 90 deg. out-of-phase from each other, and also, the amplitude is equalized. In such a state, outputs of the amplifiers 21, 22 are supplied to detectors 25, 26, respectively. The detectors 25, 26 execute an amplitude detection of a first and a second subcarriers, respectively, and detection outputs are sent to gain control ends of the amplifiers 22, 21, respectively. In such a way, levels of a first and a second carriers are controlled so as to be always maintained in prescribed amplitude.

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) This invention is applicable to the field of television signal processing technology.
The present invention relates to a subcarrier processing circuit employed as part of a color signal processing device configured using an integrated circuit.

(Prior Art) With advances in integrated circuit technology, color signal processing devices have come to be constructed from one semiconductor chip.

FIG. 6 shows the configuration of the color signal processing device in blocks. A chroma signal is supplied to an input terminal 1 and amplified by a first chroma amplifier 2. The output of the first chroma amplifier 2 is
The signal is input to a burst amplifier 3 and a second chroma amplifier 5.

The burst signal amplified by the burst amplifier 3 is input to an automatic color control (ACC) detector 4, and is also supplied to an automatic phase (APC') detector 8 and a killer detector 9.

The ACC detector 4 performs amplitude detection on the burst signal, and controls the gain of the first chroma amplifier 2 using the detected output so that the level of the burst signal remains constant. APC
The detector 8 detects a burst signal and a subcarrier processing unit 1 which will be described later.
The phase is compared with the APC carrier (APC-CW) from 1, and the phase error information is sent to the voltage controlled oscillator (VCO).
)10 control terminals. This allows VCOIO
A control loop formed by the subcarrier processing unit 11 and the APC detector 8 can generate a carrier wave whose phase is synchronized with the burst signal.

The killer detector 9 compares the phase of the carrier for killer detection (Killer fist CW) from the subcarrier processing section 11 with the burst signal, and detects the killer signal when the level of the burst signal has decreased significantly or when there is no burst signal. The color signal is generated and controlled so that the color signal is not output to the display circuit section.

The second chroma amplifier 5 is supplied with a color control signal from a terminal 6, and the chroma signal level is adjusted. The chroma signal is input to the color demodulator 7, which demodulates the (II-Y) (B-Y) color difference signal and
The (GY) signal is demodulated by matrix calculation. (RY), (B-Y) demodulation carrier (R-
Y) ・CWl(RY) ・CW is generated by the subcarrier processing section 11.

The subcarrier processing section 11 is a section that generates various carriers using the oscillation output output from the VCO].

The output of VCOII is input to the CR phase shifter 13 and converted into two vector signals having different phases. This vector signal is input to the 90° phase shift amplification and hue control section 14. The 90° phase shift amplification and hue control unit 14 uses the two input vector signals to create two vector signals with a 90° phase difference, and further converts the vector signal in accordance with the externally adjusted hue control signal. Synthesis is performed to generate one hue-controlled vector signal.

This one hue-controlled vector signal is transmitted to the second CR
The signal is input to the phase shifter 15. This CR phase shifter 15 again converts one input vector signal into two vector signals having different phases.

These two PET signals are input to the carrier output section J6. The carrier output unit 16 performs vector synthesis using the two inputted vector signals, and generates a signal by combining a plurality of carrier vectors each having a phase corresponding to each application.

That is, the carrier for APC (APC-CW), the carrier for killer (Killer-CW), the carrier for color difference signal demodulation (RY) ◆CW, (B-Y)CW are generated at the carrier output section]6. .

FIG. 7 shows a specific example of the configuration of the carrier output section 16. Components corresponding to those in FIG. 1 are given the same reference numerals.

The oscillation output from VCOIO is transmitted through transistors Q2 and Q
Supplied on the base of 3. The collectors of transistors Q2 and Q3 are connected to the power supply line together with the collector of transistor Q1. Transistors Ql, Q2
, Q3 are directly connected to the collectors of transistors Q4, Q5, QB, and resistors R3, R4,
Connected to the base via R5. A bias is applied to the bases of transistors Q2 and Q3 through a resistor R1, and a bias is applied to the base of transistor Q1 through a resistor R2. The emitters of transistors Q4, Q5, and Q6 are grounded via resistors R6, R7, and R8, respectively. Here, the base of transistor Q2 is grounded via capacitor C2.

Therefore, the emitter output of transistor Q4 is applied as a bias to the base of transistor Q1.2, the emitter output of transistor Q5 is applied to the common base of transistors QB and Q9, phase-shifting the output of VCOIO, and the emitter output of transistor Q6 is applied to the common base of transistors QB and Q9. The emitter output of VCOl, 0
is supplied to the base of transistor Q7 with the same output phase.

The emitters of transistors Q7 and Q8 are connected to resistors R, respectively.
9, R], O, and are connected in common and grounded via a constant current source, and the collectors are connected to transistors Q13, respectively.
, Q14.

A common bias is supplied to the bases of transistors Q13 and Q],4. The collector of transistor Q1.3, together with the collectors of transistors QIG and Ql8, is connected to the power supply line via resistor R14.

The collector of transistor QI4 is connected to transistor Ql-
5. It is connected to the power supply line through resistors R1 and R3 together with the collector of QI7, and is further connected to the base of transistor QI9.

The common collectors of transistor Q9 and transistor QIO are connected to the common emitters of transistors Q1.5 and 01.6, and! - The common emitters of transistors Qll and Ql2 are connected to the common emitters of transistors Q17 and Qig. The common emitters of transistors Q9 and Ql,0 and the common emitters of transistors Qll and 012 are connected to ground through resistors RLI and R1, 2, respectively, and then through a constant current source. Here transistor Q
1. A burst gate pulse is supplied to the bases of O and Qll.

Now, the emitter output of transistor Q6 is converted into vector signal a
, If the emitter output of the transistor Q5 is a vector signal, a vector signal (a-b) is obtained at the collectors of the I transistors Q8 and Q14. In addition, a vector signal (-b) is applied to the collectors of transistors Q9 and Ql5.
is obtained, and a vector signal (+b) is obtained at the collectors of transistors QI2, Ql, and 8.

Therefore, a vector signal ((a-b)±bl=A is obtained at the emitter of the transistor Q19.

This vector signal A is again input to the CR phase shifter 15 and becomes two vector signals A and B.

That is, the collectors of the transistors Q] and 9 are connected to the power supply line, and the emitters are connected to the common collector of the transistors Q20 and Q21, and to the common base via the capacitor C3.

Bias is supplied to the bases of transistors Q20 and Q2+ via resistors RI5 and RIG, respectively.

Vector signal A will be supplied to the bases of transistors Q20 and Q21 via capacitor C3. The emitter of transistor Q15 is connected to the collector of transistor Q23 and the base via resistor R+7, and the emitter of transistor Q21 is connected to the collector of transistor Q24 and connected to the base via resistor R1-8.
connected to the base via. moreover!・Langister Q
The base of 24 is grounded via a capacitor C4. The emitters of transistors Q23 and Q24 are grounded via resistors R20 and R2. Transistor Q22 constitutes a bias circuit, with its collector connected to the power supply line, its base biased via resistor R1, [i], and its emitter connected to the collector of transistor Q25 and connected to resistor R], 9. is connected to the base of transistor Q25 via. The emitter of transistor Q25 is grounded via resistor R22 and connected to the base of transistor Q29.

The emitter of transistor Q23 is connected to the base of transistor Q2G, and the emitter of transistor Q24 is connected to the bases of transistors Q27 and Q28. l・
Vector signal A is obtained from the emitter of transistor Q23, and vector signal B is obtained from the emitter of transistor Q24.

The emitters of transistors Q2[1 and 027 are connected to ground through a constant current source through resistors R23 and R24, respectively, and the emitters of transistors Q28 and Q29 are also connected to a constant current source through resistors R25 and R2O, respectively. grounded through the source. The collectors of the transistors Q26-Q29 are connected to the emitters of the transistors Q30-Q33, each of which is given a common base bias, and the collectors of these transistors Q30-Q33 are connected to the bias power supply via the resistors R27-Rho, respectively. . APC carrier APC-CW, (RY) demodulation carrier (RY) CW are obtained from the collectors of transistors Q30 and Q31, and transistor Q3
2. From the collector of Q33, carrier for killer detection (KNIer-CW), (B-Y) carrier for demodulation (B
-Y) - CW is obtained.

The APC detection output and the killer detection output are obtained during the burst signal period, and only during this period APC-CW
, K11ler-CW are output and supplied to the respective detectors. During other periods, 0 (RY) .CW and (B-Y) .CW are output and supplied to the demodulator.

(Problems to be Solved by the Invention) According to the conventional subcarrier processing unit described above, the CR phase shifter 1
There is a drawback that the two vector signals a and b created in step 3 have variations in transfer. When this variation occurs, the phase of each carrier naturally shifts, resulting in inaccurate color signal reproduction or color killer malfunction.

Variations in the phase difference of the vector signals in the CR phase shifters 13, ]5 cannot be avoided. In particular, variations in the elements when integrated are unavoidable.

FIG. 8(A) shows how the vector signal S varies with vector No. 13 a of the CR phase shifter 13 as a reference. In the same figure (B), the vector phase shift amount of the CR phase shifter is 12
In the case of 0% variation, the figure (D) shows the vector signal a Sb , (a''-2b) when it is at the center, and the figure (C) shows the vector signal a Sb, (a''-2b) in the case of +20% variation.

1 If such a variation occurs, the carrier amplitude will naturally vary due to hue control.

FIG. 9 shows how the amplitude of each carrier changes when hue adjustment is performed. The vertical line shows the vector of the output of the CR phase shifter affected by the dispersion,
The horizontal line represents changes in output amplitude when hue adjustment is performed. When there is a change in the amplitude of various carriers, AP
C. The bright color demodulation operation is inconsistent, causing malfunctions and color disturbances.

SUMMARY OF THE INVENTION An object of the present invention is to provide a subcarrier processing circuit that does not cause carrier phase difference fluctuations or amplitude fluctuations due to variations in elements.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a phase shifter that is supplied with the output of a voltage controlled oscillator and outputs first and second vector signals having different phases as H1, and first and second variable gain amplifiers that amplify and output the first and second vector signals, respectively, and a third vector signal that combines the two vector signals output from the first and second variable gain amplifiers. a 90-degree phase amplifier that outputs a vector signal and a fourth vector signal whose phase is shifted by 90 degrees; and a 90-degree phase amplifier that detects the amplitude of the third vector signal and transmits the detected output to the first variable a gain control terminal of the gain amplifier, detects the amplitude of the fourth vector signal, supplies the detected output to the gain control terminal of the second variable gain amplifier, and detects the amplitude of the fourth vector signal; A control circuit that always maintains a constant phase difference between signals is provided.

(Operation) By the above means, the third and fourth vector signals are always maintained at a constant phase difference (90°) and are always maintained at the same level.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The same parts as in the conventional circuit shown in FIG. 1 are given the same reference numerals. Since the part improved by this invention is inside the subcarrier processing section 11, this part will be explained in detail.

The output of the voltage controlled oscillator (VCO) 10 is connected to the CR phase shifter 2.
1. The CR phase shifter 20 converts the input signal into two vector signals and supplies them to the first and second 90° phase shift amplifiers 21 and 22.

The first 90° phase shift amplifier 21 creates a first subcarrier (vector signal element (a-b)), and the second 90° phase shift amplifier 21 creates a second subcarrier (vector signal ± b) Create. The vector signals ±b and ±(a-b) are signals that are created by vector synthesis so that their phases differ by 90° from each other, and are controlled so that their amplitudes are constant. The first and second subcarriers thus stabilized are both supplied to a first carrier amplifier 23 and a second carrier amplifier 24. The first carrier amplifier 23 uses two input vector signals to generate an APC carrier (APC-CW) and a killer carrier (Killer
-CW) and supplies it to the APC detector 4 and the killer detector 9. Further, the second carrier amplifier 24 has two carrier amplifiers, one for (RY) demodulation and one for (B-Y) demodulation.
- It is configured to generate CW and supply them to the demodulator 7, and to control the phase of the output carrier using a hue control voltage.

Here, the output of the first 90° phase-shifted amplifier 2 is input to the first detector 25, and the output of the second 90° phase-shifted amplifier 22 is input to the second detector 26. Supplied. The first detector 25 performs amplitude detection of the first subcarrier and supplies the detected output to the gain control terminal of the first 90' phase shift amplifier 22. Further, the second detector 26 performs amplitude detection of the second subcarrier and supplies the detected output to the gain control terminal of the second 90° phase shift amplifier 23.

Thereby, the levels of the first and second subcarriers are controlled to always be maintained at a prescribed constant amplitude.

The fact that the levels of the first and second subcarriers are maintained at a constant prescribed level as described above means that the vector signals obtained when vector synthesis is performed, that is, the phases of the various carriers are stable. This means that the phase is maintained at the desired phase. Since the control loop by the above-mentioned wave detectors 25 and 26 is always operating, even if there are variations in the elements in the integrated circuit, the phase of the output carrier is adaptively corrected and stably maintained at the desired phase. That's true.

FIG. 2 shows the inside of the subcarrier processing section 11 in more detail. This subcarrier processing section 1 is shown in FIG. 2(A) and FIG. 2(B).

The output of VCO10 is provided to the base of transistor Q52.053 via capacitor C51.

Transistors Q52 to Q56, resistors R51 to R5g, and capacitor C52 constitute the CR phase shifter 20.
Its operation is the same as the conventional one described above. Vector signal a is obtained from the emitter of transistor Q55, and vector signal S is obtained from the emitter of transistor Q50. Vector signal a is transmitted through transistor Q
The vector signal S is supplied to the bases of transistors Q68 and Q74. Bias derived from the emitter of transistor Q54 is provided to the base of transistor Q73.

The emitters of transistors Q(i7 and QD8 are grounded via resistors R71 and R72, respectively, and then via a constant current source. The emitters of transistors Q73 and Q74 are grounded via resistors R73 and R74, respectively, and then grounded via a constant current source. The collector of transistor QEi7 is connected to the common emitter of I transistors Q83 and QB4. The collector of transistor Q64 is connected to the power supply line, and the collector of transistor Q6'8 is connected to the resistor. It is connected to the power supply line through R75.The collector of transistor Q65 is connected to the power supply line, and the collector of transistor Q6B is connected to the power supply line through resistor R7B.

Transistors QO3 to Q6g correspond to the first 90° phase shift amplifier 21, and transistors QB9 to Q74 correspond to the second 90° phase shift amplifier 21.
This corresponds to the 0° phase shift amplifier 22. A circuit composed of transistors 057 to QBI and resistors R59 to R70 controls the bias of the 90° phase shift amplifiers 21 and 22, controls the vector synthesis ratio, and adjusts the vector signal obtained from each phase shift amplifier. The amount of phase shift can be finely adjusted.

That is, reference phase shift adjustment signals Rcr1 and Ref'2 are supplied to the bases of the transistors Q57 and Q058, respectively. The collectors of transistors Q57 and Q58 are connected to the power supply line, and the emitters are connected to resistors RB5 and RB.
It is grounded via B. Furthermore, transistor Q57
The emitter of is connected to transistor Q59 via resistor RBI.
The base of Qel is connected to the base of transistor Qel via resistor 114. The emitter of transistor Q58 is connected to the base of transistor Q59 via resistor R59, to the base of transistor Q60 via resistor Rho, to the base of transistor Q[i+ via resistor R62, and to the base of transistor QB2 via resistor 113. connected to the base. Then, the emitter output of the transistor QGJ is supplied as a bias to the bases of the transistors QG3 and QGG]8, and the emitter output of the transistor QB2 is supplied as a bias to the bases of the transistors Q64 and Q65. Also, as the emitter output of transistor Q59 or the base bias of transistors Q69 and Q72, the emitter output of transistor Q60 is applied to transistors Q70 and Q71.
is supplied as a base bias. Therefore, by adjusting the phase shift amount adjustment signals Rcf1 and Rcr2, the combination ratio of vector signals can be controlled, and the phase shift amount of the obtained vector signal is also controlled.

Here, the emitter outputs of transistors Q81 and QB2 can adjust the amount of phase shift of the vector signal amplifier (a-b), which controls the amplification factor of the double-balanced differential amplifier of the transistors. That's true. Using this control, ±(a-b
) information is being returned. In other words, the phase (a-b) information will be described later, but the phase of the output vector signal of the 90° phase shift amplifier 21 can also be controlled using this information. There are similar functions on the 90° phase amplifier 22 side. That is, the emitter outputs of the transistors Q59 and Q[io can adjust the amount of phase shift of the vector signal ±b. Furthermore, ±b information is fed back to the base of the transistor Q59, and the phase of the output vector signal of the 90' phase shift amplifier 22 can also be controlled using this information.

The collector of transistor Q63 is connected to transistor Q75.
The collector of transistor Qili6 is connected to the base of transistor Q7B, the collector of transistor Q69 is connected to the base of transistor Q77, and the collector of transistor Q72 is connected to the base of transistor Q7g.

The collector of transistor Q75 is connected to the power supply line, and the emitter is connected to the collector of transistor Q80 and connected to transistor Q8 via capacitor C53.
0 base. Also transistor Q7B
Its collector is connected to the power supply line, and its emitter is connected to the collector of transistor Q8J and to the base of transistor Q81 via capacitor C54. The collector of transistor Q77 is also connected to the power supply line, and the emitter is connected to the collector of transistor Q82 and to the base of transistor QB2 via capacitor C55. Furthermore, the collector of transistor Q78 is also connected to the power supply line, and the emitter is connected to the collector of transistor Q88, and the capacitor C
58 to the base of transistor Q'83. The transistor Q84 is for bias, and its collector is connected to the power supply line.

A bias is applied to the bases of transistors Q80-Q84 through resistors R79-R83, respectively, and their emitters are grounded through resistors R84-R88.

From the emitter of transistor Q80, a vector signal -
(a-b) is obtained, vector signal +(a-b) is obtained from the emitter of transistor Q81, vector signal +(a-b) is obtained from the emitter of transistor Q82, and vector signal +(a-b) is obtained from the emitter of transistor Q83. A vector signal is obtained.

1 vector signals -(a-b) and +(a-b) are provided to the bases of transistors Q99 and Q100, respectively.

The vector signals −st+b are each connected to the transistor Q1.
Supplied to the base of 04 and Q105.

Transistors Q106-Q114 operate as a current bias circuit. That is, the base and collector of transistor Q110 are connected to a common bias source together with the bases of transistors Q106-Q109 via resistor R91, and the emitters of transistors Q106 and Q107 are commonly connected to the collector of transistor Q112. The emitters of transistors Q108 and Q109 are also commonly connected to the collector of transistor Q114. The emitters of transistors Q110-Q114 are grounded.

The collector of transistor Q111 is connected to transistor Q9.
8 and is connected to the base of transistor Q 10
1 emitter. Also, transistor Q1
] 3 is connected to the base of transistor 2 Ql, 03, and the collector of transistor Q
Connected to the emitter of 9B. The collector of transistor Q9G is connected to the power supply line, and the base is connected to a bias source.

The l-transistors Q99 and Q100 output from their common emitters an output proportional to the amplitude error of the vector signal input to both bases, and supply it to the capacitor C57. The common collectors of transistors Q99 and Q100 are connected to the power supply line, and the common emitters are connected to the collector of transistor Q107. The smoothed output of capacitor C57 is supplied to the base of transistor Q97. Since the base of transistor Q98 is supplied with a reference bias, the base input of transistor Q97 is output to the collector and supplied to the base of transistor Q93. The emitter output of this transistor Q93 is passed through the base and emitter of the transistor Q94, and further through the resistor R89 as the a-b information to the previous transistor Q[il].
will be returned to its base.

The collectors of transistors Q93 and Q94 are connected to the power supply line 3. Also transistor Q97.09g
The collectors of transistors Q87 and Q88 are connected to the emitters of transistors Q85 and Q10, and the collectors of transistors Q85 and Q10 are connected to the power supply line. , the base of Q86 is connected to the collector of transistor Q87, and the bases of transistors Q87 and Q88 are connected to transistor Q9g.
connected to the collector. A capacitor C59 between the base of the transistor Q93 and the power supply line functions to remove ripples.

Transistors Q85-Q8g, Q93, Q94, Q97
~The circuit constituted by Q101 etc. is the first detector 2
5. On the other hand, transistors Q89 to Q92, Q
95, Q96, Q102 to QLO5, Q115, etc., corresponds to the second detector 26.

That is, transistors Q104 and Q105 output from their common emitters an output proportional to the amplitude error of the vector signal input to both bases, and supply the output to capacitor C5g.

The common collectors of transistors Q104 and Q1054 are connected to the power supply line, and the common emitters are connected to the collector of transistor Q109. The smoothed output of capacitor C58 is supplied to the base of transistor Q]02. Since a reference bias is supplied to the base of transistor Q103, the base input of transistor Q102 is output to the collector and supplied to the base of transistor Q95. This transistor Q
The emitter output of transistor 95 is fed back to the base of transistor Q59 as ±b information via the base and emitter of transistor 09B, and further through resistor R90.

As described above, the 90° phase shift amplifier 21 is connected to the detector 25
The gain of the 90° phase shift amplifier 22 is controlled so that a constant output vector signal is always obtained by the detection output of the detector 26.

As a result, the phase difference and amplitude of the first and second subcarriers input to the first carrier amplifier 23 are always automatically controlled to be constant, and the first and second subcarriers input to the second carrier amplifier 245 The phase difference and amplitude of are also automatically controlled to always be constant.

FIG. 3(A) shows the output vector signal a of the CR phase shifter 20.
This shows a state in which the phases of and b have changed due to element variations and temperature fluctuations. Even if there is such a change, as shown in (B), (C), and (D) of the same figure, 90%
° phase amplifier 2], vector signal (a
-b) and b (which have been subjected to vector synthesis processing so as to have a phase relationship of 90 degrees to each other) can be stably obtained without changing their amplitudes and phase difference relationships.

FIG. 4 shows a specific configuration of the first and second carrier amplifiers 23,24.

Line 31 is supplied with the vector signal (a-b) from transistor Q81, line 32 is supplied with a bias from transistor Q84, and line 33 is supplied with the vector signal (a-b) from transistor Q82. is supplied.

Transistors Q216-Q221 have their bases supplied with a common bias, and their emitters grounded via resistors R200-R2O5, respectively. The collector of transistor Q216 is connected to the emitter of transistor Q200 via resistor R221, and
It is connected to the emitter of transistor Q 201 via resistor R222. The collector of transistor Q217 is
It is connected to the emitter of transistor Q202 via resistor R223, and also to the emitter of transistor Q203 via resistor R224. transistor Q
The collector of 218 is connected to the common emitter of transistors Q204 and Q205 through a resistor R225, and to the common emitters of transistors Q20B and Q20B through a resistor R226.
Connected to the common emitter of Q207. transistor Q
The collector of 219 is connected to the common emitter of transistors Q208 and Q209 via a resistor R227, and to the common emitter of transistors Q210 and Q209 via a resistor R228.
Connected to the common emitter of Q 211. The collector of transistor Q220 is connected to the emitter of transistor Q212 via resistor R229, and the collector of transistor Q220 is connected to the emitter of transistor Q212 via resistor R229.
228 to the emitter of transistor Q213. The collector of transistor Q221 is connected to
It is connected to the emitter of transistor Q214 via resistor R231, and to the emitter of transistor Q215 via resistor R232.

Transistors Q200, Q202, Q207, Q
2], the bases of IQ213 and Q215 are connected to the bias line 32. Transistors Q201, Q2
04, the base of Q212 is connected to line 31, which is supplied with the vector signal (a-b). Transistor Q2
03 Q208 The base of Q214 is connected to line 33 where the vector signal is supplied. Therefore, the collector of transistor Q200 has a vector signal (a-b).
is obtained, and a vector signal -(a-b) is applied to the collector of the transistor Q201.

A vector signal is obtained at the collector of transistor Q202, and a vector signal is obtained at the collector of transistor Q203.

The collectors of transistors Q204 and Q205 are commonly connected to the common emitters of transistors Q222 and Q223, and the collectors of transistors Q206 and Q207 are commonly connected to the common emitters of transistors Q224 and Q225. Also, transistor Q 2
The collectors of 08 and Q209 are commonly connected to transistor Q22.
The collectors of transistors Q210 and Q211 are commonly connected to the common emitters of transistors Q228 and Q229.

Here, a vector signal -(a-b) is obtained at the collectors of transistors Q204 and Q205, and a vector signal ((a-b) is obtained at the collectors of transistors Q206 and Q207.
a-b) are obtained. Also transistors Q208 and Q2
A vector signal is obtained at the collector of transistor Q09, and a vector signal is obtained at the collector of transistors Q210 and Q0211.

Transistors Q222, Q225, Q227, Q
The bases of transistors Q223, Q224, Q226, Q229 are connected to line 35. A hue adjustment signal is then supplied between lines 34 and 35.

Furthermore, a vector signal -(a-b) is obtained at the collector of the transistor Q212, and the transistor Q21
A vector signal (a-b) is obtained from the collector of No. 3.

Transistors Q200, Q201, Q202, Q
203, Q222, Q225, Q22B, Q22
9 collector is resistor R210, R211, R212,
R213, R2], 4, R215, R21B, R21
7, respectively, and are connected to the power supply line. The collectors of transistors Q222 and Q224 are commonly connected, the collectors of transistors Q226 and Q228 are commonly connected, and the collectors of transistors Q227 and Q229 are also commonly connected.

Vector signals -(a-b) and (a-b) obtained from transistors Q200 and Q201 are derived on lines 36 and 37 and are used as APC carriers (APCΦCW). Further, the vector signal -st+b obtained from the collectors of transistors Q202 and Q203 is led out to lines 38 and 39 as a carrier for killer detection (Killer -CW). Transistor Q22B, Q
22g, 0 Q2]2 common collector and transistor Q227, Q
229, Q2] 3 common rector is line 40
It is connected to ゜41. From this line 40.4], a carrier (RY) CW for (RY) demodulation is obtained. A common collector of transistors Q222, Q224, Q214 and a common collector of transistors Q223, Q225, Q
2]5 is connected to the line 42.43. A carrier (B-Y) CW for (B-Y) demodulation is obtained from this line 42.43.

FIG. 5 shows vectors of each carrier when hue adjustment is performed in this embodiment.

The vertical system represents the vector of the output of the CR phase shifter affected by variations, and the horizontal system represents the change in output amplitude when hue adjustment is performed. According to the circuit of this embodiment, even if there are variations in the VCO output, the CR phase shift circuit output, and the elements, the phase difference between the carriers (a-b) and b can be adjusted to perform gain control in the subcarrier processing section. The angle is always maintained at 90° and the amplitude is also kept constant.

Therefore, even if hue adjustment is performed, the amplitude of each carrier is not affected and hue control is performed stably. Furthermore, there is no longer a problem that the difference in amplitude of vector signals occurs and is guided to other circuits as in the prior art.

[Effects of the Invention] As explained above, the present invention accurately obtains various carrier phases without causing carrier phase difference fluctuations or amplitude fluctuations due to variations in elements.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a specific example of the circuit shown in FIG. 1, and FIG. 3 is a vector diagram shown to explain the function of the circuit of this invention. , FIG. 4 is a circuit diagram showing a part of FIG. 3 in more detail, FIG. 5 is a vector diagram shown to explain the present invention in detail, and FIG. 6 is a block diagram showing a conventional color signal processing section. , FIG. 7 is a more specific circuit diagram of the circuit of FIG. 6, and FIGS. 8 and 9 are vector illustrations for explaining the functions of the conventional circuit. 0...CR phase shifter, 21, 2...90° amplifier,...carrier amplifier, 5, detector.

Claims (1)

[Claims] A phase shifter to which the output of the voltage controlled oscillator is supplied and outputs first and second vector signals having different phases; and a phase shifter that amplifies and outputs the first and second vector signals, respectively. The first and second variable gain amplifiers combine the two vector signals output from the first and second variable gain amplifiers to generate a third vector signal, which is 90 degrees out of phase with the first and second variable gain amplifiers. a 90-degree phase amplifier that outputs the fourth vector signal; a control circuit that detects the amplitude of the vector signal and supplies the detected output to a gain control terminal of the second variable gain amplifier to always maintain a constant phase difference between the third and fourth vector signals. A color subcarrier processing circuit characterized by: