JPH03205978A - Solid-state image pickup element - Google Patents

Abstract

PURPOSE:To relieve defective picture elements by detecting the output timing of defective picture element signals from the AND of defective bit information to appear at an output by the shift operations of a defect designation horizontal shift register and a defect designation vertical shift register. CONSTITUTION:The defect designation shift registers are provided corresponding to the number of picture elements in horizontal and vertical directions and memory defective bit information are stored in those shift registers. Then, the output timing of the defective picture element signals is detected from the AND of the defective bit information to appear at the output by the shift operations of the respective shift registers synchronized to the read of picture element information and based on the timing, the reset of output capacity to form a read voltage signal is inhibited. Then, the preceding read signal is replaced with the defective picture element signal. Thus, by adding two shift registers, simple logic circuit and signal switching circuit, the defective picture elements can be relieved with high quality.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a solid-state image sensor, and relates to a technique that is effective for use in, for example, a defect relief technique in a solid-state image sensor.

[Conventional technology]

Regarding defect relief technology for solid-state image sensors, there is, for example, Japanese Patent Application Laid-Open No. 60-86980. As described in the above publication, the outline of this defect relief technology is to provide an external memory that stores the position of the defective pixel, and perform defect correction using an address pulse read out from this memory and specifying the defective pixel. It is something to do.

[Problem to be solved by the invention]

In the above defect relief technology, external memory and its writing/
Since a memory control circuit for controlling readout is required and the number of parts increases, this not only prevents the solid-state imaging device from becoming smaller and lighter, but also increases costs. Further, it is necessary to manage the defect information of each solid-state image sensor and to store the defect address in the memory when incorporating the solid-state image sensor into an image sensor.

The inventor of this application focused on the fact that relatively many CCD-type solid-state image sensors are considered defective due to the presence of a limited number of defective pixels, about 2 or 3, and developed a defect relief circuit. We considered a built-in solid-state image sensor.

The purpose of this invention is to suppress the increase in chip size while
An object of the present invention is to provide a solid-state imaging device with a built-in defect relief function.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a defect specifying shift register corresponding to the number of pixels in the horizontal direction and a defect specifying shift register corresponding to the number of pixels in the vertical direction are provided, memory defect information is stored in them, and each of the above-mentioned shifts is performed in synchronization with the reading of pixel information. The output timing of the defective pixel signal is detected from the logical product of the defective bit information that appears at the output due to the shift operation of the register, and based on this, the output capacitance that forms the readout voltage signal is inhibited and the previous readout signal is output. is replaced with the defective pixel signal.

[For production]

According to the above-mentioned means, by adding two shift registers, a simple logic circuit, and a signal switching circuit, high-quality defective pixels can be repaired.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of a solid-state image sensor according to the present invention. Each circuit block and element in the figure is formed on a single semiconductor substrate such as single-crystal silicon using known semiconductor integrated circuit manufacturing techniques.

The solid-state imaging device of this embodiment is directed to an interline CCD type solid-state imaging device, and the imaging array is composed of a photodiode and a vertical CCD (charge phase device). Here, the accumulated and transferred signal charges are serially outputted through a horizontal COD that functions as a horizontal transfer shift register.

The signal charges serially output in this way are output through the following floating diffusion amplifier (output amplifier). The above output amplifier basically consists of MOSFET (insulated gate field effect transistor, the same applies hereinafter) Q8, MOSFET Q9, and MOSFET
It consists of a two-stage source follower amplifier consisting of TQI 1 and Q12. MOSFETs Q9 and Q12 act as constant current loads by supplying constant voltage VG to their gates. Front stage source follower MOSFETQ
The gate capacitor 8 serves as a detection capacitor that converts the transferred signal charge into a voltage signal. A transfer gate MOSFET is connected to the gate of the source follower MOSFETQB in the previous stage.
Signal charges from the horizontal CCD are taken in via ETQ6.

An interline CCD type solid-state image sensor having such an output amplifier has a built-in defect relief circuit as described below.

The defect specifying vertical shift register has bits corresponding to the number of pixels in the vertical direction in the above-mentioned imaging array, and, although not particularly limited, defect information is transferred to the bin corresponding to the defective pixel by selectively disconnecting fuse means as described below. is memorized. The defect specification horizontal shift register has bits corresponding to the number of pixels in the horizontal direction in the imaging array,
By selectively cutting off the fuse means similar to the above, defect information is stored in the bit corresponding to the defective pixel.

Both the defect specified vertical and horizontal shift registers are
Vertical CCD and horizontal CCD in CD type solid-state image sensor
The shift operation is performed in synchronization with the transfer timing. The output signals Y and X of both the vertical and horizontal shift registers read out by such a shift operation are input to a NAND gate circuit G. Note that when the NAND gate circuit G is used in this way, the above defect information is a logic "1".
In this embodiment, the defective pixel output detection signal A output from the NAND gate circuit G as described above and the inverter circuit I
The defective pixel is replaced by the following defective pixel correction circuit using the inverted signal B passed through VI.

The output signal A of the AND gate circuit G is the Swiss MO
Supplied to the gate of SFETQI. This MOSFET
QI transmits a reset gate signal applied to terminal RG to the gate of recent MOSFET Q7. This MOS
FETQ7 is provided between the gate of the source follower MOSFETQB and the reset voltage of terminal RD. Further, the output signal A of the AND gate circuit G is supplied to the gate of the switch MOSFET Q3. This MOSF
ETQ3 transmits the transfer gate signal applied to the terminal OG to the gate of the transfer gate MOSFETQ6.

The output signal B of the inverter circuit IVI is
Supplied to the gate of OSFETQ2.

This MOSFET Q2 is a push-pull power supply side MOSFET that receives the reset gate signal applied to the terminal RG.
Tell the gate of QI 3. Further, the output signal B of the inverter circuit IVI is supplied to the gate of the switch MOSFET Q4. This MOSFETQ4 has terminal OG
The transfer gate signal given to the MOSFET Q14 is transmitted to the gate of the pseudosiple type ground side MOSFETQ14. The reset voltage of terminal RD is MOSFET QI 5 and constant current MO.
The signal is applied to the drain of MOSFETQ17 via a source follower output circuit consisting of SFETQ16. This M
The source of OSFETQI 7 is the source follower of the latter stage.
Connected to the gate of OSFETQI1. MOSFE
The gate of TQI 7 is the above MOSFET Q13 and Q14.
An output signal v1 of a busho pull circuit consisting of is supplied.

The signal Vl is inverted via an inverter circuit IV2, and is transferred to a transfer gate 1-MOSFE provided between the source follower amplifier in the previous stage and the source follower amplifier in the latter stage.
The control voltage of TQI O is set to v3.

The reason why the defective pixel correction circuit is relatively complicated is to accommodate the correlated double sampling operation for reducing the switching noise caused by the signal slope.

The operation of the defective pixel correction circuit of this embodiment is as follows.

FIG. 2 shows a timing diagram for explaining an example of the operation of the defective pixel correction circuit.

In the figure, voltage v2 is the gate voltage of MOSFETQB, and voltage V4 is the gate voltage of MOSFETQI1.

During a normal pixel signal readout operation, the detection signal A is set to a low level because either the output signal X or Y of both shift registers is at a low level logic "O". For example, even when the defect-specifying vertical shift output signal Y is at a high level indicating a defect, if the defect-specifying horizontal shift output signal X is at a low level, the output signal A of the NAND gate circuit G becomes high level, and the output of the inverter circuit IVI Signal B becomes low level. As a result, M
OSF BTQ 1 and Q3 are on.

Due to the ON state of these MOSFETs QI and Q3, the MOSFET is turned on according to the tying signals from terminals RG and OG.
Control signals RG' and OG° are generated to be supplied to the gate of MOSFET Q6 and the transfer gate, and the signal charges are read out through the output amplifier as described above.

That is, the reset MOSFET Q7 is turned on by the high level of the timing signal RG', and after the previous signal charge is swept out, the signal charge transferred from the horizontal COD is taken in by the high level of the timing signal OG'. be exposed.

In the above-mentioned correlated double sampling, the reset level and the readout signal are each sampled externally, and the difference between them is extracted as an output signal. Therefore,
In the solid-state image sensor of this embodiment, it is necessary to always output a reset voltage in pair with a signal voltage.

When the signal from the defective pixel is read out, since the output signals X and Y of both shift registers are both high level logic "1", the defect detection signal A is set to low level. Therefore, the impurity circuit IVI The output signal B of becomes high level, turning off the !OSFETs QI and Q3, and turning on the MOSFETs Q2 and Q4.
MO5FET
Q13 is turned on to set the control signal v1 to the noise level. As a result, MOSFET Q]7 is turned on, and the output signal of the previous source follower amplifier corresponding to the reset voltage RD is output to the source follower amplifier at the subsequent stage. Thereby, a reset voltage corresponding to the defective pixel signal is created in a pseudo manner. This sampling is in contrast to the correlated double sampling operation described above. When a transfer timing signal is supplied from the terminal OG, the large MOSFET is turned on.
MOSFET Q5 is turned off through Q4. As a result, the defective pixel signal is forcibly set to the reset level, and in response to the MOSFET Q3 being turned off, the transfer gate MOSFET Q6 is also kept in the off state. Therefore, the previous pixel signal is held as is at the input of the source follower amplifier at the previous stage. At this transfer timing, -, MOSFETQ
14 is turned on, and the control signal v1 is set to a low level. As a result, the MOSFET Q17 is turned off, and the transmission gate 1-MOSFET QI, which was turned off when the control signal v1 was at a high level, is turned on.
O is turned on, and the previous pixel signal held in the previous source follower is output again as a correction signal to be replaced with the defective pixel signal.

After this, when a normal pixel signal is outputted again due to the defect specifying shift output signal
Note voltage and pixel signal are output as a pair.

FIG. 3 shows a specific circuit diagram of one embodiment of the defect designating horizontal shift register. Note that the defect designation vertical shift register is also constructed from a similar circuit. Each circuit element in the figure, together with circuit elements constituting other circuits of other solid-state image sensors (not shown), is formed on a single semiconductor substrate such as single crystal silicon using known semiconductor integrated circuit manufacturing technology. be intimidated. In addition, in the same figure,
Although some of the circuit symbols given to the MOSFETs are the same as those in FIG. 1, it should be understood that they are different.

MOSFET QI2 performs storage operation and output operation.

That is, MOSFETQ12 uses its gate capacitance as a storage means. When the gate capacitance is held at a high level, MOSFET QI2 is turned on and transmits the high level of the shift clock pulse φ2 supplied to its drain to its source side. This first stage MOSFETQ1
A high level (logic "1") initial value φin is inputted to the gate of No. 2 in synchronization with the start of horizontal scanning of the horizontal COD through a MOSFET QI controlled by a shift clock pulse φ1. The source example signal B1 is taken as an output signal. At this time, in order to prevent the level of the output signal B1 from decreasing due to the threshold voltage of the MOSFET Q12, a bootstrap capacitor C1 is provided between the gate and source of the MOSFET Q12. A diode-shaped MOSFET QI1 is provided at the source of the MOSFET Q12 to perform a signal transmission operation. This MOSFETQI 1 is a MOSFE
It operates as a unidirectional element that transmits a high level signal on the source side of TQ12.

Although not particularly limited, a reset MOSFET Q13 is provided between the source of the MOSFET QI2 and the ground potential point of the circuit for quickly resetting the output signal B1. The gate of this reset MOSFET Q13 is supplied with a shift clock pulse φ1 whose phases are different so that the high levels of the shift clock pulses φ2 do not overlap.

The output signal Bl of the MOSFET QI 2 is transmitted through the diode-type MOSFET QI 1 to the gate of a MOSFET Q22 serving as a similar storage means in the next stage. Stable MOSFETs Q14 and Q15 are provided in parallel between the source (cathode side as a diode) of the diode-type MOSFET QI1 and the ground potential point of the circuit.

An initial value φin is supplied to the gate of MOSFET QI 4, and when the initial value φin is input manually, the previous state is reset once. An output signal passed through a similar diode MOSFET Q31 one bit before is fed back to the gate of MOSFETQI5 as a recent signal. In other words, the circuit consisting of the MOSFETs Q11 to Q15 represents a half-bit unit circuit constituting a shift register, and a pair of similar circuits constitutes an l-bit unit circuit. By providing a plurality of unit circuits, a multi-bit shift register is constructed.

Unit times for half a bin, which is the pair of the above circuits! (Second circuit) is composed of MOSFETs Q21 to Q25. However, MOSFETQ2 that performs storage and output operations
A shift clock pulse φl is supplied to the drain of No. 2. In addition, there is a reset MOSFE provided on the output side.
A shift clock pulse φ2 is supplied to the gate of TQ23.

The human power pulse φin is synchronized with the shift clock pulse φl.
is raised to a high level. This allows MOSFETQ
The high level of the input pulse φin is transmitted to the gate capacitor No. 12 via MOSFETQI. This turns on MOSFET QI2.

After the shift clock pulse φ1 becomes a high level and a low level, the shift clock pulse φ2 is set to a high level. When the shift clock and pulse φ2 are set to high level, the high level is applied to the MO which has already been turned on.
It is output as an output signal B1 through SFETQ12. At this time, since the above-mentioned high level is also written to the bootstrap capacitor CI, the gate voltage of MOSFET QI2 is boosted in accordance with the high level of the output signal. As a result, the high level of the shift cloth pulse φ2 is outputted as the output signal B1 without any level loss. In response to the high level of the output signal B1, the source side node through the diode-type MOSFET QIl is also set to high level. However, this MOSFETQI
The level of the source side node of 1 is MOSFBTQI
It is assumed that the level has decreased by one threshold voltage. The high level of the source side node of MOSFETQI1 is transmitted to the gate electrode of MOSFETQ22 in the next stage circuit, and its gate capacitance and bootstrap capacitance C
2 to high level. This allows MOSFETQ
22 is turned on.

After shift clock pulse φ2 goes from high level to low level, shift clock pulse φ1 goes to high level)L
yl is rubbed. When the shift clock pulse φ1 is brought to a high level, the MOSFET QI 3 is turned on, so that the output signal B1 is pulled from the high level to the low level at high speed. In addition, the high level of shift clock pulse φ1 is MOSFETQ22 which is already turned on.
It is output as the output signal of the next stage. At this time,
Since the high level is also written in the bootstrap capacitor c2, the gate voltage of MOSFET Q22 is boosted in accordance with the high level of the output signal. As a result, the high level of the shift clock pulse φ1 is outputted as the next stage output signal without any level loss. MO in diode form depending on the high level of the above output signal.
The source side node through SFETQ21 is also set to high level. However, the level of the source side node of MOSFETQ2 1 is assumed to be lowered by the threshold voltage of MOSFETQ2 1. This MOSFE
The high level at the source side node of TQ2 1 is transmitted to the gate electrode of a similar MOSFET Q3 2 in the next stage circuit, causing the gate capacitance and bootstrap capacitance C3 to be at high level. This turns MOSFET Q32 on.

Thereafter, a half-bit shift operation is similarly performed in synchronization with shift clock pulses φ1 and φ2.

Therefore, when used as a horizontal shift register as described above, odd-numbered output signals B1, B3, etc. are used.

These odd-numbered output signals Bl, 83, etc. are connected to the output line via diodes (including diode-type MOSFETs) and fuse means Fl, F3, etc. for preventing backflow. The fuse means Fl, F3, etc. are made of thin aluminum wires, although not particularly limited, and are selectively cut by laser beam irradiation in accordance with the horizontal address of the defective pixel. The figure shows an example in which the fourth bit, F9, is cut by a laser beam. Although not shown, the output line is provided with a reset circuit that is reset to a low level by a shift clock pulse φI.

The output line is output as an output signal X via an output inverter circuit IV2. When the logic "1" shift signal is shifted to the disconnected 5 bits, the output signal remains low because the fuse F9 that outputs it is disconnected, and it is transferred to the inverter circuit TV2.
Logic “l” which is inverted by and means the output of the defective pixel.
is output.

By using a shift register like this example,
By increasing the chimp size of the solid-state image sensor by at most 5%, the above-mentioned defects can be repaired.

In the defect relief circuit of this embodiment, in addition to specifying one defective pixel as described above, it is also possible to specify a plurality of pixels using the pair of defect specifying horizontal and vertical shift registers as described above. The most effective case is when a plurality of defective pixels exist on the same horizontal or vertical address. In the above method of specifying a defective pixel using a pair of shift registers, if two defective pixels are specified with different horizontal and vertical addresses, the two defective pixels with defects as described above will be In addition, two normal pixels are also regarded as defects and the signal correction described above is performed.

However, even if this is done, in the case of a solid-state image element consisting of a large number of pixels, it will not be noticeable that the correction voltage is different from the actual one for about four pixels as described above.
There is no practical problem when using the LH delayed signal. Therefore, the defect relief circuit of this embodiment enables relief of a small number of defective pixels, about two or three.

Among COD solid-state image sensors, a relatively large number of COD solid-state image sensors are discarded as defective due to the existence of the above-mentioned two or three defective pixels. Therefore, by incorporating a simple defect relief circuit as in this embodiment, the product yield of COD solid-state imaging devices can be greatly improved. In particular, the number of pixels in solid-state imaging devices is increasing in order to achieve higher resolution, and the probability of defective pixels occurring increases accordingly, making defect relief technology indispensable. Therefore, the defect relief circuit according to the present invention is extremely effective for the solid-state image sensing device with high resolution as described above.

The effects obtained from the above examples are as follows. That is, (11) a defect specifying shift register corresponding to the number of pixels in the horizontal direction and a defect specifying shift register corresponding to the number of pixels in the vertical direction are provided, memory defect bisoto information is stored therein, and the above-mentioned method is synchronized with the readout of the pixel information. Defective signals that appear in the output due to the shift operation of each shift register 7) Detect the output timing of the defective pixel signal from the AND of the information, and adjust the read voltage signal based on it. By adding a relatively simple circuit that replaces the previous readout signal with the defective pixel signal, it is possible to repair the defective pixel.

(2) Since it has a built-in defect relief circuit, it is possible to achieve the effect that an imaging device using a solid-state imaging device can be made smaller and lighter.

(3) Among CCD solid-state image sensors, a relatively large number are discarded as defective due to the presence of about 2 to 3 defective pixels. Therefore, by incorporating a simple defect relief circuit like the one according to the present invention, CO
D. The product yield of solid-state imaging devices can be significantly improved. In particular, the number of pixels in solid-state image sensing devices is increasing in order to achieve higher resolution, and as a result, the probability that defective pixels will occur increases. Therefore, in a high-performance solid-state image sensor that achieves high resolution, the use of the defect repair technique according to the present invention has the effect of making it possible to substantially mass-produce the device.

The invention made by the inventor of the present application has been specifically explained based on Examples above, but the present invention is based on the Examples. It goes without saying that the invention is not limited, and that various changes can be made without departing from the spirit of the invention. For example, the specific structure of the defect designation shift register or various embodiments can be adopted. The method for storing the address of a defective pixel may be one in which fuse means is provided in the output section as in the above embodiment, or one in which the defect information is serially outputted to a shift register. etc. It can be anything. The above-mentioned defect designation shift register may be arranged parallel to the horizontal and vertical directions of the imaging array as in the embodiment shown in FIG.
The layout may be such as arranging two resistors in parallel to each other, or the wiring length between the output section and the output section may be shortened. Further, the readout method may be one that is compatible with the correlated double sampling but outputs only other pixel signals.

In addition to the interline type COD as in the above embodiment, the imaging array may be a CCD type solid-state image sensor that uses other readout methods, or a MOS type solid-state image sensor that reads out the signal charge of a photodiode through a Swiss-chip element. Any device may be used as long as it is configured as a semiconductor integrated circuit, as typified by , and reads out a voltage signal through a capacitor.

This invention can be widely used in solid-state imaging devices.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, a defect specifying shift register corresponding to the number of pixels in the horizontal direction and a defect specifying shift register corresponding to the number of pixels in the vertical direction are provided, memory defect bit information is stored in them, and each of the above shifts is performed in synchronization with the reading of pixel information. The output timing of the defective pixel signal is detected from the logical product of the defective bit information that appears in the output due to the shift operation of the register,
Based on this, the defective pixel can be repaired by adding a relatively simple circuit that prohibits the reset of the output capacitor that generates the read voltage signal and replaces the previous read signal with the defective pixel signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the solid-state image sensor according to the present invention, FIG. 2 is an operation waveform diagram for explaining an example of its operation, and FIG. 3 is a diagram of a defect specifying horizontal shift register. FIG. 2 is a specific circuit diagram showing one embodiment. G... NAND gate circuit, IVI, IV2... Inharter circuit Figure 1

Claims (1)

[Claims] 1. A defect specification shift register corresponding to the number of pixels in the horizontal direction and a defect specification shift register corresponding to the number of pixels in the vertical direction are provided, and each shift register is provided with defect bit information corresponding to the defective pixel. is stored, and the shift operation of each of the shift registers is performed in synchronization with the reading of pixel information,
It is characterized by the addition of a function that detects the output timing from the defective pixel by logical product of defective bit information appearing in the output signal, prohibits resetting of the output capacitance, and outputs the previous read signal as a defect relief signal. A solid-state image sensor. 2. The solid-state image sensor according to claim 1, wherein the solid-state image sensor is a CCD type solid-state image sensor, and a floating diffusion amplifier is provided at the output section.