JPH03205920A - Phase locked circuit, storage device and magnetic disk storage device - Google Patents

Abstract

PURPOSE:To obtain the phase locked circuit which can switch optimally the characteristic in accordance with a data transfer speed and can be operated stably by providing a means for changing a response characteristic, based on an instruction stored in a store means. CONSTITUTION:A CPU 9 decides in which cylinder or in which zone a track having a sector in which target data is written is contained, selects information having the constant of a PLL corresponding to its cylinder or zone from in a ROM or a RAM 11, and writes it in a register 7 through a microcomputer bus 8. The register 7 sends its information to each block of a PLL 43, and each block switches a gain, a mode, etc., based on its information, and constitutes a PLL having a characteristic being optimal to a transfer speed in which target data is written. In such a way, the phase locked circuit which can always supply a stable clock can be formed.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a phase synchronization circuit, and in particular to a magnetic disk device in which the transfer speed of written data changes depending on the inner and outer circumferences, and the magnetic disk device. The present invention relates to an information processing system having the following features.

[Prior Art] Conventionally, a phase synchronized circuit that generates a synchronized clock is usually
P L L (Phase-Locked-Loop)
It consists of The characteristic frequency W m and the attenuation rate ξ are constants indicating the responsiveness of the PLL, and these constants are determined by conditions such as the initial phase difference φ and the phase pull-in time Taq.

Here, the phase pull-in time Taq changes depending on the data transfer speed if the pattern length is constant, since phase pull-in must be performed within the phase synchronization pattern.

The gain of the frequency phase comparator and charge pump is set to Kd. V
When the gain of CO is Kc and the PLL is constructed using the filter shown in FIG. 5, the characteristic frequency W. and damping rate ξ
are respectively expressed as wm = φ (o/(shiξ= (C1+C,) ・R-w./2. In the conventional phase-locked circuit for a system, data transfer for one system is Since the speed is uniquely determined, once the system transfer speed is determined, it is possible to calculate the optimum PLL constant and set the constant as a fixed value.

On the other hand, magnetic disk devices in information processing systems are
Generally, the write data speed was constant, but in this case, the limit of the linear recording density was determined at the innermost periphery, and the linear recording density became smaller toward the outer periphery.

[Problems to be Solved by the Invention] However, in recent years, in order to improve the recording capacity of the entire magnetic disk, techniques for writing data at a constant linear recording density have been devised.

That is, in these techniques, recording is performed at a constant linear density by changing the write clock between the inner and outer circumferences and making the transfer speed variable.

Reading from such a magnetic disk is performed at a constant rotational speed of the disk, so the read data speed differs. Therefore, in this case, it is necessary to generate a variable clock that is synchronized with the read data rate.

However, the PLL according to the prior art does not take into consideration the case where one system has a plurality of data speeds, and the PLL characteristics can only be switched depending on the data speed. Therefore, there was a problem that stable operation could not be obtained for all data speeds.

SUMMARY OF THE INVENTION An object of the present invention is to provide a phase-locked circuit that can optimally switch the characteristics of the phase-locked circuit depending on the data transfer rate and operate stably with respect to the data transfer rate.

In addition, in the embodiments to be described later, each characteristic of the phase synchronized circuit to be switched can be regarded as a response characteristic in a broad sense. Therefore, in this specification, the term "response characteristics" is used in this broad sense. [Means for Solving the Problem] In order to achieve the above object, the present invention provides a storage means for storing an instruction for changing a response characteristic, and a storage means for changing the response characteristic based on the instruction stored in the storage means. The present invention provides a phase-locked circuit characterized by having means for.

In addition, in order to achieve the above-mentioned objective, a phase comparator section, a charge pump section, a filter section, a voltage controlled oscillation section, a storage means for storing an instruction for changing the response characteristic, and a The present invention provides a phase synchronized circuit characterized by comprising means for changing at least one of the gain amount of the charge pump section, the filter constant of the filter section, or the center frequency of the voltage controlled oscillation section.

The present invention also provides means for instructing change of response characteristics in response to changes in the synchronization signal period, storage means for storing the instruction, and changing the response characteristics based on the instructions stored in the storage means. The present invention also provides a clock generation circuit characterized by comprising a phase synchronization circuit having means.

In addition, the present invention provides a storage device equipped with a disk-type storage medium, in which, when a disk-type storage medium is read accessed, a reference clock for handling read data is set according to an access position on the disk-type storage medium. The phase-locked circuit has means for instructing a change in the response characteristic of the phase-locked circuit that generates the signal, a storage means for storing the instruction, and a means for changing the response characteristic based on the instruction stored in the storage means. A first storage device is provided.

In addition, when the first storage device is a magnetic disk device, when a magnetic disk is read accessed, a phase synchronized circuit that generates a reference clock for handling read data according to the access position on the magnetic disk. means for instructing the change of response characteristics so that malfunctions due to intersymbol interference due to peak shifts of stored data positions do not occur, storage means for storing the instruction, and response characteristics based on the instructions stored in the storage means; It is preferable that the phase synchronization circuit has a means for changing the phase synchronization circuit.

The present invention also provides a storage device equipped with a disk-type storage medium, which includes a phase synchronization circuit that generates a read clock synchronized with read data during read access to the disk-type storage medium, and a phase synchronization circuit that generates a read clock that is synchronized with read data. a decoding circuit for decoding the read data; a delay means for delaying the read data to provide a phase difference between the read data to be synchronized by the phase synchronized circuit and the read data to be decoded by the decoding circuit; A second storage device is provided, comprising: control means for controlling operations, wherein the control means changes the amount of delay in the delay means according to a read access position in a disk type storage medium.

Furthermore, the present invention provides a storage device including a disk-type storage medium, which includes an oscillator that generates a reference clock during write access to the disk-type storage medium, and an oscillator that generates a reference clock according to the write access position in the disk-type storage medium. A phase synchronization circuit that generates a write clock synchronized with a reference clock, an encoding circuit that encodes write data using the write clock, a write means that stores the encoded write data in a disk type storage medium, and a phase synchronization circuit that generates a write clock synchronized with a reference clock. It is characterized by having an out-of-synchronization detection means for detecting that the circuit is out of synchronization, and a means for inhibiting writing of write data to a disk-type storage medium when the out-of-synchronization detection circuit detects out-of-synchronization. A third storage device is provided.

Furthermore, the present invention provides an information processing system comprising the storage device and an information processing device connected to the storage device.

Further, the present invention provides a one-chip LSI characterized by having a phase-locked circuit and a register for setting the responsiveness of the phase-locked circuit.

Note that it is desirable that each of the phase synchronization circuits and the clock generation circuits be constructed within an LSI.

The present invention also provides an information processing device comprising the phase synchronization circuit, the clock generation circuit, or the 1-chip LSI.

[Function] According to the phase locked circuit according to the present invention, the response characteristic is changed based on the instruction stored in the storage means for storing the instruction to change the response characteristic.

Further, according to another phase-locked circuit according to the present invention, the gain amount of the charge pump section, the filter constant of the filter section, or the voltage control is controlled based on the instruction stored in the storage means for storing the instruction for changing the response characteristic. At least one of the center frequencies of the oscillation section is changed.

Further, according to the clock generation circuit according to the present invention, an instruction to change the response characteristic is set in the storage means in accordance with a change in the synchronization signal period, and the phase change is performed based on the instruction stored in the storage means. Synchronous circuits change the response characteristics.

Furthermore, according to the first storage device according to the present invention. When a disk-type storage medium is read accessed, an instruction to change the response characteristics of a phase synchronization circuit that generates a reference clock for handling read data is stored in the storage means according to the access position on the disk-type storage medium, and phase synchronization is performed. The circuit changes the response characteristics based on instructions stored in the storage means.

Further, according to the magnetic disk device according to the present invention, when a magnetic disk is read accessed, response characteristics of the phase synchronized circuit that generates a reference clock for handling read data are stored according to the access position on the magnetic disk. A change instruction that prevents malfunctions caused by intersymbol interference due to position peak shift is stored in the storage means.

Further, the phase locked loop changes the response characteristic based on the instruction stored in the storage means.

As described above, according to the present invention, for example, for a single system having multiple transfer speeds, it is possible to set the optimal response characteristics according to all data speeds, so that stable A phase-locked circuit that can supply clocks can be realized.

In particular, in FA disk drives, measures must be taken to prevent false synchronization, deadlock, excessive tracking, etc. caused by inter-symbol interference due to peak shifts of data recorded on the magnetic disk. It is necessary to switch the PLL characteristics with high precision according to the data rate, and the present invention can meet this requirement.

Further, according to the second storage device of the present invention, when a disk-type storage medium is read accessed, read data is delayed according to the read access position, and the phase synchronized circuit decodes the read data to be synchronized. A predetermined phase difference is provided between the read data to be decoded by the circuit, and a stable decoding operation is realized regardless of the transfer speed of the read data.

Further, according to the third storage device according to the present invention, since the transfer speed of write data changes, the phase synchronization circuit may become out of synchronization, but when the phase synchronization circuit loses synchronization, the disk The write data is inhibited from being written to the storage medium, and data stored in the storage medium is prevented from being destroyed.

(The following is a blank space) C Embodiment] Hereinafter, an embodiment of the PLL according to the present invention will be described by taking an application to a magnetic disk device as an example.

First, a first example will be described.

FIG. 1 shows the PLL (
FIG. 2 is a block diagram showing the peripheral configuration of the phase synchronized circuit.

This configuration includes a phase comparator 2 that compares the frequency and phase of Code Data 1, and a charge pump 3 that outputs a constant current for a period according to the phase difference compared by the phase comparator 2.
, a filter 4 that converts the current output of the charge pump 3 into a voltage, and a VCO that generates a Sync C1ock 6, which is a clock whose frequency corresponds to the voltage of the filter 4.
(voltage controlled oscillator) 5, a register 7 that stores switching information such as gains and constants for each of these blocks, a microcomputer pass 8 that writes to the register 7, and a CPU 9 that performs overall arithmetic processing. , HDC (hard disk controller) 10 that performs overall control
, and a ROM or RAM II in which data such as CPU programs and optimum constants are stored.

FIG. 2 shows internal signals of the register 7, and the microcomputer path 8 is a bidirectional data bus D. ~Dfi
l2, address bus A. ~A. 13, and control signal 1
4, and an output signal n.

~n415 is connected to each block.

In order to improve the recording capacity of the disk, the magnetic disk device in this embodiment divides each cylinder or all cylinders into several zones, and changes the writing speed for each zone to reduce changes in linear density. System.

In this case, since the period of read data also changes for each cylinder or each zone, it is necessary to optimize the characteristics of the PLL of the phase synchronized circuit in accordance with the transfer speed indicated by each data period.

Now, to specifically explain the operation when reading data written to a certain track, in response to a read command from a host computer, etc., the CPU 9 determines which track has the sector where the target data is written. It is determined which cylinder or zone it is included in, and information having a PLL constant corresponding to that cylinder or zone is selected from the ROM or RAMI 1 and written into the register 7 through the microcomputer path 8.

The register 7 sends the information to each block of the PLL, and each block switches the gain, mode, etc. based on the information, and constructs a PLL with characteristics optimal for the transfer speed at which the target data is written. do.

In the ROM or RAM II, constants constituting the optimum PLL for the transfer speed in each cylinder or zone are determined theoretically or experimentally, and the information is stored in advance in the register 7. Similar to writing to a general external RAM, the data on the data bus 12 is written to the register designated by the address bus 13 by the τ and WE signals in the control signal 14. The information is sent to each PL as the output signal 15.
It is output to the L block. Furthermore, since the register 7 is rewritten at the same time as or immediately before the head seek operation, it takes a long time (
By the end of 10 days, the rewriting of the register 7 and the switching of the gains, constants, etc. of each block have been completed, and the state is sufficiently stable, so that no problem arises in the read operation.

Next, an example of gain switching of each PLL block will be explained using FIGS. 3 to 6.

FIG. 3 shows a gain switching circuit that switches the value of the constant current output by the charge pump 3, and is composed of a current mirror 16, a level shift transistor A17, an analog switch A18, and resistors R1 to R19.

Note that the gain of the charge pump is expressed as Ia/8π, where Ia21 is the reference current supplied from the gain switching circuit.

From the reference voltage Vrefa20, the transistor A17
is determined by one of the resistors 19 selected by the analog switch A18. is reflected by the current mirror 16 and becomes the reference current Ia21. Therefore, n resistance values are prepared for the resistor 9,
By switching the analog switch A using the control signal A22 sent from the register 7, n types of the reference current Ia can be obtained, and n types of gain switching can be performed.

FIG. 4 shows another example of the gain switching circuit of the charge pump 3, in which transistors T7--T. A current mirror 29, a transistor C30, a resistor R,
131, and an analog switch C32, the third
Similarly to the example shown in the figure, the current determined by the transistor C30, the resistors R, and 31 from the reference voltage Vrefc33 is reflected by the current mirror 29 to generate a reference current Ic3.
4, but n on the receiving side of the current mirror 29.
The reference current Ic34 is changed by connecting two transistors in parallel, switching the number of connected transistors using the analog switch C32 in response to the control signal C35 from the register 7, and changing the ratio of the folded current.

? It is also possible to switch the output current Ia of the gain switching circuit by switching Vrefa20, but this method has the disadvantage that the influence of disturbances is large and the operation becomes unstable.

Figure 5 shows the switching circuit of the filter, including capacitor C123, capacitor C224, and resistors R■1 to
Consisting of R1.25 and analog switch B26.
In the case of the filter having the configuration shown in FIG. 4, the attenuation rate ξ is calculated using the characteristic frequency W1 as
It is expressed as 2. Here, R represents one of the resistors R2, .about.R25. Therefore, by preparing n resistance values for the resistor 25 and switching the analog switch B28 using the control signal B28 sent from the register 7, it is possible to set n different attenuation rates ξ.

FIG. 6 shows the gain switching circuit of the VCO 5, which includes 2n input transistors T1, 1 to T p r m
* T r l L~T,,. 36, reference current source 37
, a differential amplifier circuit including a load transistor 38, and an analog switch D39.

As shown in FIG. 6, the gain of the VCO 5 is determined by the gain of the input stage differential amplifier circuit, and is known to be proportional to the size of the input transistor 36 to the 172nd power. Therefore, two pairs of n transistors are connected in parallel to the input transistor 36, and the number of connected transistors is changed by the analog switch D39 in response to the control signal D40 from the register 7, and the size is changed in n ways in equalization, and the gain Switch.

In order to shorten the pull-in time and expand the capture range, the VCO 5 needs to be fixed at the center frequency determined by the transfer rate immediately before starting the pull-in operation. Said VCO
The center frequency f0 of 5 is the timing capacitor C and the transistor pace emitter voltage VB! ．． and the reference voltage Ic.

In a system with variable transfer speeds, it is necessary to change the reference voltage Ic and set the center frequency for each transfer speed. To change the reference current Ic, if a circuit similar to the gain conversion circuit of the charge pump shown in FIG. 4 is used, the reference current Ic can be arbitrarily set and the center frequency can be changed.

Next, an example of a magnetic disk data control circuit 70 equipped with a PLL according to this embodiment will be explained using FIG.

The example shown in FIG. 7 is one in which peripheral function blocks are integrated into the phase synchronized circuit of this embodiment, and in addition to the PLL 43 and the register 7, there is also a function block for converting to a recording code. Encoder 47 that performs inverse conversion, decoder 45, Code Read Data
Window adjustment 44 performs phase adjustment of 5.0, clock adjustment 46 performs conversion between system clock and data transfer clock, and write clock generation 49 generates a clock of any frequency for writing based on reference clock 51.
, a write compensation 48 for compensating for effects such as peak shift during writing, and the microcomputer pass 8.

In this control circuit 70, the register 7 is connected to the PL
In addition to the optimum value of L43, information such as adjustment switching signals of other blocks is also stored to keep the entire system in an optimum state at all times.

Note that this control circuit JII 70 is preferably provided in a magnetic disk as an LSI. In this case, the resistor R and capacitor C used in the PLL for switching characteristics are LSI
It may also be used as an external element.

This is because it is considered difficult to provide highly accurate resistors and capacitors in an LSI.

FIG. 8 shows an example in which RAM II is provided independently and exclusively for storing information for setting the PLL 43. In this case, there is no need to transfer data to the control circuit 70 using the microcomputer path 8, and the switching This will reduce the time required.

FIG. 9 shows the configuration of an information processing system according to this embodiment.

This system consists of a host computer 91 and a magnetic disk device 192. The magnetic disk device 92 includes a magnetic disk 93, a controller 98 that controls the magnetic disk,
A magnetic head 94, a head amplifier 95 that amplifies the electrical signal of the data sensed by the magnetic head, a waveform shaping section 96 that shapes the electrical waveform of the amplified data, the data control circuit 7o, the code conversion section 97, and the entire device. It is equipped with a CPU 9 that controls the.

A second embodiment of the present invention will be described below.

FIG. 10 shows the structure of the PLL according to this embodiment.

PLL includes phase comparator 110, filter 120, and VCO
1 3 0 and it is set up. In the PLL according to this embodiment, the charge pump 3 of the PLL according to the first embodiment is
will be described assuming that it is provided within the phase comparator 110. FIG. 2 shows the operation timing of the PLL according to this embodiment.

The phase comparator 110 has an input pulse signal 1000 and a VCO
Compare the phases of the output clocks 1040 of 1 3 0,
The phase of the input pulse signal 1000 is the output clock 1040
If the phase is ahead of that of the current phase, the current is adjusted for a time corresponding to that phase difference. On the other hand, if the phase of the input pulse signal 1000 lags the phase of the output clock 1040, the current ■ flows for a time corresponding to the phase difference. is extracted from the filter 120.

Also, the phase of the input pulse signal 1000 and the output clock 1
If the phases of 040 match, the filter 120
has no effect on

A phase comparator 110, a filter 120 .
A control bus 1050 is connected to each of the VCOs 130, and constants for each block are thereby set.

FIG. 12 shows the internal configuration of the VCO 130 according to the second embodiment.

As shown in the figure, the VCO 1 3 0 includes a voltage-current converter 210, a current-controlled oscillator 220, and a digital-to-analog converter 230.

In the figure, a control voltage 1030 is input to a voltage-current converter 210 and converted into a control current 2000.

This control current 2000 is input to the current controlled oscillator 220 and controls the frequency of the output clock 1040.

On the other hand, the digital-to-analog converter 230 has a reference resistance R
Instructions by the control bus based on the current generated by 2x10
A reference current 2010 is generated and input to the current controlled oscillation I220 for setting the free-running frequency according to 50.

Figure ↓4 shows this VCO 1 3 according to the second embodiment.
The specific circuit configuration of 0 is shown below.

In the figure, 210 is a voltage-current converter, 220 is a current controlled oscillator, and 230 is a digital-to-analog converter.

As shown in the figure, the current controlled oscillator 220 is a known emitter-coupled astable multivibrator, and transistors Q1, Q2, Q3, Q4, and Q5 in the figure control current 2.
A current mirror is used to fold back the sum current IC of 000 and the reference current 2010.

As described in the first embodiment, at this time, the frequency f of the output clock 1040 is 4G.・v! l! however. VBR is given by the voltage between the base and emitter of the transistor.

Next, voltage-current converter 210 connects transistor Q6. Q
7, a differential amplifier composed of resistors R1 and R2, and a current source Ia, and Q8 and Q9 that take out the difference current of the differential amplifier.

Further, the digital-to-analog converter 230 is of a current output type, and includes differential switches whose number corresponds to the number of bits of the control bus, and current sources weighted according to the number of bits. Then, the total sum of currents corresponding to each bit of the control bus 1050 is output as a reference current 2010.

Here, FIG. 13 shows the relationship between the reference current 2010 and the free-running frequency with respect to the n-bit digital control value input from the control bus 1050.

As shown, the reference current 2010 and the free-running frequency vary linearly depending on the control value of the control bus 1050.

Further, FIG. 15 shows another structure of the digital-to-analog converter 230.

In the figure, transistor Mb applies a bias voltage, transistor Ml. M2, . . . Mn correspond to n bits of the control bus, respectively, and are configured so that the gate width W is doubled.

In other words, the gate IIIW of the transistor Mn is twice the gate width of the transistor M1.

The remaining (2 x n) transistors other than those indicated by M are used as switches, and the control bus 1050 controls whether or not the bias voltage generated by transistor Mb is applied to the gates of the transistors M1 to Mn. Determine according to each corresponding bit.

Note that the digital-to-analog converter can be used with other circuit systems as long as it is a current output type.

Next, FIG. 16 shows the configuration of the phase comparator 110. vinegar.

As shown, phase comparator 110 includes flip-flops FFI. FF2, NAND gate NAI, transistor QIO, Qll, Q12, Q13, Q14, Mac
, k − M@3, M■, and a digital-to-analog converter 230.

Flip-flops FFI, FF2 and NAND gate NAI detect the phase difference between input pulse signal 1000 and output clock 1040. When the phase of the input pulse signal 1000 is ahead of the phase of the output clock 1040, the Q output of the FFI becomes "H" for a time corresponding to the phase difference, and conversely, the phase of the input pulse signal 100 is output When it is behind the phase of the clock 1040, the Q output of FF2 becomes "H" for a time corresponding to the phase difference.
"become.

Transistors M1 and M. 2, and M. , and M. 4 is
Each constitutes a differential switch, and current flows only when the Q output of FFI is "H".On the contrary, the Q output of FF2
The output draws current for the duration of It H 71.

Transistor Q10. Q11, Q12 and Q13, Q
14 constitute folded current mirrors, and supply the reference current generated by the digital-to-analog converter 230 to the differential switch.

The internal configuration of the digital-to-analog converter 230 is the same as that used in the voltage control oscillator 130 described above (Figs. 14 and 15).
(see figure).

However, in order to be able to set constants independently of VCO 1 3 0, the control bus 105 used for VCO 1 3 0
For a 0 bit, use another m bits and a reference resistance R. X is provided independently.

Of course, it is also possible to share the control bus and switch using the same control signal.

Note that, as shown in the first embodiment, each part of the PLL may be controlled via registers as shown in FIG. 17.

In FIG. 17, the PLL includes a phase comparator 110, a filter 120 . The microprocessor 160 writes information into the register 150, and the output of the register 150 becomes a control bus 1050, which is then used as the phase comparator 110, filter 120, etc. Set the circuit constants of the VCO 130.

As described above, in addition to the effects of the PLL according to the first embodiment, the PLL according to the second embodiment is mainly composed of semiconductor elements, so that the PLL according to the second embodiment
It has the advantage of being easier to integrate.

Note that the PLL may be configured by combining the components such as the VCO and phase comparator shown in the first embodiment with some of the components shown in the second embodiment.

Furthermore, in the magnetic disk data control circuit 7o (see FIG. 7) or the information processing system (see FIG. 9),
Instead of the PLL according to the first embodiment, a PLL according to the second embodiment may be provided.

Next, as a third embodiment of the present invention, it is suitable for a magnetic disk device in which each cylinder or all cylinders are divided into several zones, and the writing speed is changed for each zone to reduce changes in linear density. In addition, the magnetic disk system circuit will be explained. The magnetic disk system circuit includes a magnetic disk 93, a controller 98, a magnetic head 94, a head amplifier 95, a waveform shaping section 96, a data control circuit 70 . The code converter 97 corresponds to a reading and writing part of the CPU 9 that controls the entire device.

FIG. 18 shows the structure of the read side of the magnetic disk system circuit according to this embodiment.

As shown, the magnetic disk system circuit includes a microprocessor 160, a non-volatile storage element 170, a disk controller 190, a decoder 200, a selector 31
0, delay line 320, P according to the first or second embodiment
It is composed of LL330.

In the figure, an encoded signal 4000 read from a magnetic medium 180 is input to a tapped delay line 320.

Each tap of tapped delay line 320 is input to selector 310 .

On the other hand, the encoded signal 4010 extracted from the center tap having a delay amount approximately half of the maximum delay of the delay line 320 is
Input to LL330.

Then, the output clock 104 generated by the PLL 330
0 is input to the decoder 200 as a timing clock for data acquisition by the decoder 200.

Selector control information for selecting a tap that has an optimal phase relationship with respect to the output clock 1040 is written in the nonvolatile memory element 170, and the microprocessor 160 reads this information and inputs it to the selector 310.

As a result, even if the transfer speed of the encoded signal 4000 changes, the circuit constants of the PLL 33 are switched by the control bus, and the microprocessor 16 switches the control information of the selector 31, so that the encoded signal 4020 is always output. The clock 1040 can maintain an optimal phase relationship.

As a result, the decoder 200 performs stable decoding processing and sends the decoding signal 403 to the disk controller 190.
Next, in the magnetic disk system RAM circuit according to the third embodiment, the PLL according to the first or second embodiment can be supplied with a clock for writing to the magnetic medium. The case where it is used for the moon will be explained.

FIG. 19 shows the configuration of the σ write side of this magnetic disk system circuit.

The magnetic disk system circuit includes disk controller 1
90, read/write amplifier 410, AND gate 4
20, an encoder 430, a D-type flip-flop 440, an inverter 470, an out-of-synchronization detection circuit 450, and a PLL 460.

PLL 460 generates write clock 5020 of the required frequency based on reference clock signal 5000. In this embodiment, the reference clock signal 5000 is
To simplify the device, it is set to a fixed value, and the frequency is changed by the PLL 460 to generate a clock according to the write transfer speed.

The encoder 430 uses this write clock 5020 to encode the write signal 5010 input from the disk controller 190 to generate an encoded signal 5030. Write clock 5020 is reference clock signal 5000
When the encoded signal 5030 is synchronized with the
and the signal is recorded on the magnetic medium. but,
Write clock 5020 and reference clock signal 5000
out of synchronization, the out-of-sync detection circuit 450 detects out-of-sync, outputs an out-of-sync signal 5040 to notify the disk controller, and at the same time immediately switches the AND gate 42 using the inverter 470 and the D-type flip-flop 440. The output of is fixed to "L jl". This suppresses recording on the magnetic medium.

Thereafter, after confirming that the out-of-synchronization signal 5040 is no longer output, the disk controller 190 clears the flip 7 flop 440 and restarts the write operation under the control of the host device.

Here, FIG. 20 shows an internal configuration diagram of the writing PLL 460 and the out-of-sync detection circuit 450. The PLL 460 includes an M frequency divider 500 that divides the reference clock signal by M.
Output clock 10 of VCO 130 and VCO 1 3 0
N frequency divider 140 that divides 40 by N, and phase comparison 8I11
0 and a filter 120. This PLL46
0, as in the first and second embodiments, vCO
In addition to changing the settings of each part such as the M frequency divider. By changing the division ratio of the N frequency divider, an output of a predetermined frequency is obtained.

Further, the out-of-sync detection circuit 450 is composed of a determination window generation circuit 510 and a determination circuit 520.

The determination window generation circuit 510 uses the reference clock signal 5
It receives a signal from an M frequency divider 500 that divides 000 by M, and generates a window having a certain width before and after the edges compared by the phase comparator 110.

The determination circuit 520 determines whether the edge of the branched clock 1010, which is the output of the N frequency divider 140, is within the window, and if it is within the window, synchronization is established. If it is not within the window, it is determined that the synchronization is out.

FIG. 21 shows the configurations of the above M frequency divider 500, determination window generation circuit 510, and determination circuit 520. A specific example will be shown.

The operation will be described below for the case where the reference clock signal 5000 is frequency-divided by two.

Since the frequency is divided by 2, the 2
Connect k frequency divider circuits. This corresponds to the M frequency divider 500.

The judgment window generation circuit 510 has k input NAND 70
00, inperter 7010, flip-flop 702
Constructed with 0.

The determination circuit is comprised of a flip-flop 7030.

FIG. 22 shows the operation timing chart.

The judgment window control circuit 510 generates a window signal 6010 having a time width corresponding to a half period of the reference clock signal 5000 before and after the rising edge of the M-divided signal 6000 that is the output of the M-frequency divider 500. generate.

Of course, if you reduce the number of signals input to the k-input NAND7000, the window width will become wider, and the synchronization criteria will be
It becomes loose.

This window signal 6010 is connected to the D input of the flip-flop 7030 of the determination circuit 520, and the N frequency divider 140
The output of the divided clock 1010 is connected to the clock input of the flip-flop 7030.

As shown in the timing chart, the frequency division clock 10-
If a rising edge of 1 0 exists within the window, then
The out-of-synchronization signal 5040 outputs "H", and conversely, when it exists outside the window, it outputs "It L".

As described above, according to the magnetic disk device equipped with the magnetic disk system circuit according to the third embodiment, the phase relationship between the data read from the magnetic medium and the timing clock can be optimally set, so that highly reliable decoding can be achieved. becomes possible.

Further, when writing data to a magnetic medium, the write operation can be immediately inhibited if the write clock is out of synchronization, thereby preventing data from being destroyed on the medium.

The embodiments of the PLL according to the present invention have been described above, taking as an example the application to a magnetic disk device.

Note that the PLL according to the above embodiments can be similarly applied to storage devices such as optical disk storage devices and magneto-optical disk storage devices that use other disk-type storage media.

Further, even in an information processing device with a variable data rate, the PLL according to each embodiment can be implemented in the same way and works effectively. (The following is a blank space) [Effects of the Invention] As described above, according to the present invention, a phase-locked circuit whose characteristics can be optimally switched according to the data transfer rate and which can operate stably with respect to the transfer rate is provided. can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the PLL and its peripheral parts according to this embodiment, FIG. 2 is a symbol diagram showing the configuration of the register circuit, FIG. 3 is a circuit diagram showing the charge pump gain switching circuit, and FIG. Figure 4 is a circuit diagram showing another charge pump gain switching circuit, Figure 5 is a circuit diagram showing a filter constant switching circuit, Figure 6 is a circuit diagram showing a VCO gain switching circuit, and Figure 7 is a data control circuit. A block diagram showing the configuration of the circuit,
Figure 8 is a block diagram showing the configuration of another data control circuit.
FIG. 9 is a block diagram showing the configuration of the information processing system, FIG. 10 is a block diagram showing the configuration of the PLL according to the second embodiment of the present invention, FIG. 11 is a timing chart showing the operation of the PLL, and FIG. 12 is a block diagram showing the configuration of vCO,
Fig. 13 is a characteristic diagram showing the characteristics of VCO, Fig. 14 is vC
15 is a circuit diagram showing the configuration of the digital-to-analog converter, FIG. 16 is a circuit diagram showing the configuration of the phase comparator, and FIG. 17 is a circuit diagram showing the configuration of the PLL. Block diagram, FIG. 18 is a block diagram showing the structure of the read side of the magnetic disk system circuit according to the third embodiment, FIG.
20 is a block diagram showing the structure of the write side of the magnetic disk system circuit, FIG. 20 is a block diagram showing the structure of the out-of-sync detection circuit, FIG. 21 is a circuit diagram showing the structure of the out-of-sync detection circuit, FIG. 22 is a timing chart showing the operation of the out-of-synchronization detection circuit. E...Codo Data signal, 2...Frequency phase comparison, 3...Charge pump, 4...Filter, 5
...■C○, 6...Sync Clock signal, 7
...Register, 8...Microcomputer pass, 9...CP
U, 10...HDC (hard disk controller) 11...RAM, 43...PLL, 110...
・Phase comparator, 120...filter, 130...V
CO, Engineering 60...Microprocessor, 170...
Non-volatile memory element, 190... Disk controller, 200... Decoder, 310... Selector, 32
0...Delay line, 330...PLL, 410...Read/write amplifier, 420...AND, 430...
・Encoder, 450... Out-of-synchronization detection circuit, 460
...PLL.

Claims (1)

Claims: 1. A phase synchronized circuit comprising: storage means for storing an instruction to change the response characteristic; and means for changing the response characteristic based on the instruction stored in the storage means. 2. A phase comparison section, a charge pump section, a filter section, a voltage controlled oscillation section, a storage means for storing an instruction for changing the response characteristic, and a gain amount of the charge pump section based on the instruction stored in the storage means. or means for changing at least one of the filter constant of the filter section or the center frequency of the voltage controlled oscillation section. 3. A phase shifter having means for instructing a change in response characteristics in response to changes in the synchronization signal period, storage means for storing the instruction, and means for changing the response characteristics based on the instructions stored in the storage means. A clock generation circuit comprising a synchronous circuit. 4. A storage device equipped with a disk-type storage medium, which includes a phase synchronization circuit that generates a reference clock for handling read data according to the access position on the disk-type storage medium when the disk-type storage medium is read accessed. A memory characterized by comprising: means for instructing change of response characteristics; storage means for storing the instruction; and the phase synchronized circuit having means for changing the response characteristic based on the instruction stored in the storage means. Device. 5. During read access to a magnetic disk, the response characteristics of the phase synchronization circuit that generates the reference clock for handling read data are changed according to the access position on the magnetic disk to prevent intersymbol interference due to peak shifts in the stored data position. The phase synchronized circuit has a means for instructing to prevent the occurrence of a malfunction due to the above, a storage means for storing the instruction, and a means for changing the response characteristic based on the instruction stored in the storage means. magnetic disk storage device. 6. A storage device equipped with a disk-type storage medium, the phase-locked circuit generating a read clock synchronized with read data during read access of the disk-type storage medium;
A decoding circuit decodes read data using a read clock, and a phase difference between the read data to be synchronized by the phase synchronization circuit and the read data to be decoded by the decoding circuit by delaying the read data. a delay means that gives
A storage device comprising: control means for controlling a read operation, wherein the control means changes the amount of delay in the delay means according to a read access position in a disk type storage medium. 7. A storage device equipped with a disk-type storage medium, comprising: an oscillator that generates a reference clock during write access to the disk-type storage medium; and an oscillator that generates a reference clock when the disk-type storage medium is accessed; The phase synchronization circuit that generates the clock, the encoding circuit that encodes the write data using the write clock, the writing means that stores the encoded write data in the disk type storage medium, and the phase synchronization circuit are out of synchronization. 1. A storage device comprising: out-of-synchronization detection means for detecting out-of-synchronization; and means for inhibiting writing of write data to a disk-type storage medium when the out-of-synchronization detection circuit detects out-of-synchronization. 8. An information processing system comprising the storage device according to claim 4, 5, 6 or 7, and an information processing device connected to the storage device. 9. A one-chip LSI characterized by having a phase-locked circuit and a register for setting the responsiveness of the phase-locked circuit. 10. A phase comparison section, a charge pump section, a filter section, a storage means for storing an instruction for changing the response characteristic, and a gain amount of the charge pump section or a filter of the filter section based on the instruction stored in the storage means. 1. A semiconductor integrated circuit comprising: a phase synchronization circuit comprising means for changing at least one of a constant or a center frequency of a voltage controlled oscillator. 11. The phase locked circuit according to claim 1 or 2, or
An information processing device comprising the clock generation circuit according to claim 3 or the semiconductor integrated circuit LSI according to claim 7 or 8. 12. A storage device according to claim 6 or 7, characterized in that the storage device comprises a magnetic disk as the disk type storage medium, particularly a magnetic disk device.