JPH03204218A - High frequency phase shifter - Google Patents

Abstract

PURPOSE:To always obtain a highly accurate phase shift by providing a phase shift circuit setting the phase shift with a control signal in (n+1)-bit, and a code converter converting an n-bit input control signal into a control signal of (n+1)-bit. CONSTITUTION:Phase shifters 11-16 by bit with phase shifts of 9 deg., 16.87 deg., 31.61 deg., 59.25 deg., 111.06 deg., 208.15 deg. are provided corresponding to each bit of a control signal (bits B1-B6) in (n+1) bits (e.g. n=5). Moreover, a phase shift circuit 1 giving a phase shift in response to the control signal (bits B1-B6) in (n+1)-bit to an input signal IN and a code conversion section 2 converting an input control signal (bits A1-A5) in n-bit into the control signal (bits B1-B6) in (n+1)-bit according to the predetermined rule are provided. Thus, even when an error of each bit shift quantity is large, the phase shift with high accuracy is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high frequency phase shifter, and particularly to a high frequency phase shifter that is used in a phased array antenna and requires highly accurate phase control.

[Conventional technology]

Conventionally, in this type of high-frequency phase shifter, when using a control signal for controlling the phase shift amount, for example, 5 bits, the minimum phase shift amount is set to 1.
1.25°, weighted by L2.4.8.16, and the phase shift amount of each bit is 11.25°, 22.2°.
By setting angles of 11°, 45°, 90°, and 180°,
．． The configuration was such that a phase shift amount of 0° to 348.75° was obtained in 25° steps.

[Problem to be solved by the invention]

The conventional high-frequency phase shifter described above can provide the minimum number of bits for the required minimum and maximum phase shift amounts, but in order to ensure a highly accurate phase shift amount, each A highly accurate phase shift amount is required for all bits.

For example, in a high-frequency phase shifter that requires high precision, a general requirement is ±6°, 3° rms or less over the entire phase shift amount, and there are also many demands for even higher precision.

In order to meet this requirement with the conventional high frequency phase shifter mentioned above, for example, in the case of a 5-bit phase shifter, the weight of each bit is 11.25±0.16°22.5±
0.32°, 45±0.65°, 90±1.29°, 1
The angle is 80±2.58°, which allows for an error of only ±1.43%.

Furthermore, since errors due to connection of each bit cannot be ignored, the tolerance value becomes even smaller.

To achieve this, for example, in a hybrid integrated circuit, phase shift elements such as a switch element that changes the amount of phase shift, an inductor that determines the amount of phase shift, a capacitor, a distributed constant line, etc. are separately constructed and assembled. This can be achieved by adjusting the amount of phase shift at each time, but for ICs where adjustment is impossible, if the error in phase shift amount is large, the design must be restarted from the beginning, which takes a lot of time. The disadvantage was that it was expensive.

[Means to solve the problem]

The high frequency phase shifter of the present invention includes a bit-specific phase shifter that is provided corresponding to each bit of an (n+1) bit control signal and has a predetermined phase shift amount that is set according to each of these bits. , a phase shift circuit that supports a transfer amount of the input signal according to the control signal, and a code converter that converts the n-bit input control signal into the (n+1)-bit control signal according to a predetermined regulation. have.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

This example uses (n+1) bits (n=
5) are provided corresponding to each bit of the control signal (bits Bl to B6), and are set respectively according to these bits.
It is equipped with bit-by-bit phase shifters 11 to 16 having a phase shift amount of 111.06°, 208.15', and supports a phase shift amount corresponding to the control signal (Bl to B6) with respect to the input signal IN. Phase circuit 1 and n-bit human control signal (beep) Al~A5)
The code converter 2 converts the code into an (n+1) bit control signal (Bl to B6) according to a predetermined regulation.

The amount of phase shift of each bit/Z phase shifter 11 to 16 is determined as follows.

The minimum phase shift amount of the (n+1) bit phase shift circuit 1 is θ1, the total phase shift amount is θ, and the binding XK (0<X<2, K-〇, 1.2
. . . n) is weighted and expressed by the relational expression (1).

θd = θ, (1+x+x"+-・-・+x')・・
(1) Also, assuming that the error in the phase shift amount of each bit is ±E%, the minimum phase shift amount as n-bit phase shift circuit 1 is φ1, and the maximum phase shift amount is φ7, θ1=φ , (1-E/100) ...
... (2) θ d = = φT/ (1-E/100)
・・・・・・ Relating to [3], formula (1) ~ (3
), and the phase shift amount θ of each bit phase shifter 11 to 16 of the (n+1) bit phase shift circuit l is determined as θ,=
Determine x K-1·θ1.

Further, the code converter 2 is configured of, for example, a ROM.

Next, the operation of this embodiment will be explained.

The 5-bit, 7-bit input control signal (Al to A5) is converted into a 6-bit phase shift that is the closest phase shift amount to the phase shift amount corresponding to the added input control signal (Al to A5) in the code converter 2. The signals are converted into 6-bit control signals (B1 to B6) as the optimal combination signals stored in advance for the respective bit-specific phase shifters 11 to 16 constituting the circuit 1.

The converted control signal (Bl-86) is input to the 6-bit phase shift circuit 1, and the selected bit (logic level “1”)
) only set the phase shift amount. In this way, the input signal IH is given the phase shift amount closest to the phase shift amount set by the input control signal (Al to A5) and is output as the output signal OUT.

In the above operation, the total error when the set phase shift amount of each bit phase shifter 11 to 16 constituting the phase shift circuit 1 has an error is shown in Table 1.

From Table 1, ±20 for the center value set for each bit.
% error, the total error can be set to 3°rms or more.

〔Effect of the invention〕

As explained above, the present invention includes a phase shift circuit that sets the amount of phase shift using an (n+1)-bit control signal, and a code converter that transforms an n-bit manual control signal into an (n+1)-bit control signal. With this configuration, even if the error in the phase shift amount of each bit is large, it is possible to obtain a predetermined highly accurate phase shift amount as a whole, and therefore it is possible to reduce costs. . Further, there is an effect that a wide range of design freedom can be given to ICs that cannot be adjusted.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1... Phase shift circuit, 2... Code converter, 11 to 16... Bit-specific phase shifter.

Claims (1)

[Claims] A bit-by-bit phase shifter is provided corresponding to each bit of the (n+1) bit control signal and has a predetermined phase shift amount set according to each bit, and the control signal is adjusted to the input signal. A phase shift circuit that supports the transfer amount according to n
A high-frequency phase shifter comprising: a code conversion unit that converts a bit input control signal into the (n+1) bit control signal according to a predetermined regulation.