JPH03204068A - Neuron coupling circuit - Google Patents

Abstract

PURPOSE:To easily make a circuit into an LSI by providing a multiplier to multiply input data inputted to a first input terminal by weighing data inputted to a second input terminal, and a capacitance means to store the weighing data as a voltage. CONSTITUTION:When the input data is inputted to an input terminal 22, it is stored in a capacitor 10 as the voltage. Simultaneously, the input data is inputted to the first input terminal 28 of the multiplier 14. Meanwhile, the weighing data changed to a value designated from a computer is stored in a capacitor 12 in advance as the voltage with a learning function, and the weighing data is inputted to the second input terminal 30 of the multiplier 14. The multiplier 14 performs the multiplication of both data, and outputs a result. The learning function is executed by inputting data desired to learn to the input terminal 22 and storing it in the capacitor 10. The charge/discharge of the capacitor 12 is performed by energizing a switching means 18c by inputting a learning signal from the computer(not shown in figure) to the start-up terminal of the switching means 18c and so as to approach the input data amplified with a positive-phase amplifier 18d.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a neuron coupling circuit that is a neuron component of a neuron type computer. - Layer In detail, it relates to a neuron connection circuit with a learning function that can be implemented in an LSI.

(Prior Art) In a neuron type computer, one neuron is an information processing element with a large power and one output, and a network is formed by connecting a large number of neurons. The neuron has multiple connection circuits (100a to 100
z) and the outputs of these combination circuits.
2 and an amplifier 104 that amplifies the output of the adder 102.

In FIG. 16, N coupling circuits (100a to 1°O
z), weighting data optimized by a digital computer (not shown) is sent and stored in a register 136 as shown in the system diagram of the coupling circuit in FIG. This weighted data is converted into an analog signal by a digital-to-analog converter (hereinafter referred to as "rD/A converter") 138, and then multiplied by input data in a multiplier 140. The data weighted in the coupling circuit in this way is added in addition H102, amplified in amplifier 104, and then output as a neuron.

(Problem to be Solved by the Invention) The conventional coupling circuit described above uses a register 136 to store weighted data, and also uses a D/A converter to convert digital data to analog data. Therefore, there are problems that the coupling circuit becomes complicated and it is difficult to implement it into an LSI, and a learning means for optimizing the weighting data is provided by an external digital computer and not within the coupling circuit.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a neuron coupling circuit which has a learning means, which can be realized with a simple circuit, and which can be implemented in an LSI.

(Means for Solving the Problems) In order to solve the above problems, the present invention includes the following configuration. That is, in a neuron coupling circuit that changes weighting data to a specified value based on input data inputted by a computer and a learning signal, the neuron coupling circuit multiplies the input data by the weighting data and outputs the result.
a multiplier that multiplies input data input to a first input terminal connected to the input terminal of the coupling circuit by weighting data input to a second input terminal; and a multiplier between the second input terminal of the multiplier and ground. a capacitive means connected to the circuit and configured to store weighted data as a voltage; Particularly, a neuron coupling circuit that changes weighting data to a specified value based on input data inputted by the computer and a learning signal, characterized by comprising a learning means for charging and discharging to a value specified by the computer. In the neuron coupling circuit that multiplies the input data by weighting data and outputs the result, the gate is connected to the input terminal (328) of the coupling circuit, and the drain is connected to the positive power supply line (334). A first FET (310) which is a channel FET, and a P-channel FE whose gate is connected to the input terminal (328) and whose drain is connected to the positive power supply line (334).
a second FET (318) which is T, and the input terminal (32
8) and the gate is connected to the negative power supply line (
336), which is a P-channel FET connected to
ET (316) and a fourth FE'j (324), which is an N-channel FET whose gate is connected to the input terminal (328) and whose drain is connected to the negative power supply line (336).
), and a capacitor (304) whose one end is connected to ground (332) and which stores the weighted data as a voltage.
A charge/discharge terminal (330) is connected to the other side of the capacitor (304) for charging and discharging the voltage accumulated in the capacitor (304), and a gate is connected to the other side of the capacitor (304), and a drain terminal is connected to the other side of the capacitor (304). is the first FET
N-channel FET connected to the source of (310)
a fifth FET (312), and the capacitor (
304), a drain connected to the source of the second FET (318), and a sixth FET (320), which is a P-channel FET, whose source is connected to the source of the fifth FET (312); , a seventh FET (314) which is a P-channel FET whose gate is connected to the other of the capacitors (304,) and whose drain is connected to the source of the third FET (316); an eighth FET (322) whose drain is connected to the source of the fourth FET (324) and whose source is connected to the seventh FET (314), and the sixth FET (320).
a first resistor (326a), one of which is connected to the source of the eighth FET (322) and the other of which is connected to the output terminal (33B) of the coupling circuit; a second resistor (326b) connected to the output terminal (338) of the first learning symbol input terminal (338);
40), a ninth FET (40) whose gate is connected to the first learning symbol input terminal (340), whose drain is connected to the source of the first FET (310), and whose source is connected to the other of the capacitors (304). 306a) and the first
A tenth FET (306b) whose gate is connected to the learning signal input terminal (340), whose drain is connected to the source of the third FET (316), and whose source is connected to the other of the capacitors (304), and a second learning signal. Input terminal (3
42), and an eleventh FET (308a) whose gate is connected to the second learning signal input terminal (342), whose drain is connected to the source of the second FET (31B), and whose source is connected to the other of the capacitors 304. , a 12th FE whose gate is connected to the second learning signal input terminal (342), whose drain is connected to the source of the fourth FET (324), and whose source is connected to the other of the capacitors (304).
T (308b).

Further, in a refresh circuit for refreshing weighting data of a neuron coupling circuit having a capacitive means for accumulating weighting data, a voltage of the capacitive means is compared with a plurality of predetermined reference voltages to select a voltage for recharging the capacitive means. It is characterized by comprising a selection section for selecting.

(Operation) Input data input from the input terminal of the coupling circuit is input to the first input terminal of the multiplier.

On the other hand, the learning means is controlled by the learning signal and charges and discharges the weighted data stored as a voltage in the capacitive means.

The multiplier combines the input data input to the first input terminal and the second
The weighting data input to the input terminal is multiplied and output.

The weighting data stored in the capacitive means is read out, refreshed by a refresh circuit external to the neuron coupling circuit, and then charged via the refresh circuit.

In the refresh circuit, the read weighted data is compared with a plurality of predetermined reference voltages in a selection section, and a voltage for recharging the capacitor means is selected. This selection voltage is again charged into the capacitive means of the neuron coupling circuit.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a system diagram showing an embodiment of a neuron coupling circuit according to the present invention.

In the figure, a capacitor IO for storing input data is connected between an input terminal 22 of the coupling circuit and a ground (hereinafter referred to as rGND) 26. The input terminal 22 and the first input terminal 28 of the multiplier 14 are directly connected. The learning means 18 includes a positive phase amplifier 18d and a negative phase amplifier 18.
It is composed of switching means 18b and 18c that conduct between the input terminal and the output terminal when a signal is received at the start terminal and the input terminal a. The input terminal of the reverse amplifier 18a is connected to the input terminal 22 of the coupling circuit, and its output terminal is connected to the switching means 18.
The output terminal of the switching means 18b is connected to the second input terminal 30 of the multiplier 14. The input terminal of the positive phase amplifier 18d is connected to the input terminal 22 of the coupling circuit, and the output terminal of the positive phase amplifier 18d is connected to the input terminal of the switching means 18c. The output terminal of the switching means 18c is connected to the second input terminal of the multiplier 14. A capacitor 12, which is a capacitive means, is connected between the second input terminal 30 of the multiplier 14 and GND 26.

Since this embodiment has a weighting function and a learning function, the circuit operation will be explained based on both functions.

First, the weighting function will be explained. When input data is input to the input terminal 22, it is stored in the capacitor 10 as a voltage. At the same time, this input data is input to the first
It is input to the input terminal on the 2nd day. On the other hand, weighting data changed to a value specified by a computer (not shown) by a learning function described later is stored in the capacitor 12 as a voltage in advance, and this weighting data is applied to the second input terminal 30 of the multiplier 14. is input. Multiplier 14 multiplies both data and outputs the result.

Next, the learning function will be explained. First, data to be learned (either positive or negative data may be used, but let's assume positive data) is input to the input terminal 22 and stored in the capacitor 10. When it is desired that the weighting data accumulated in the capacitor 12 be positive data, a learning signal is inputted from a digital computer (not shown) to the starting terminal of the switching means 18c to make the switching means 18c conductive, and the signal is amplified by the positive phase amplifier 18d. The capacitor 12 is charged and discharged so that the input data approaches the input data. If you want to accumulate negative weighted data in the capacitor 12, input a learning signal to the starting terminal of the switching means 18b to make it conductive, and charge/discharge the capacitor 12 so that it approaches the negative input data that has been inverted and amplified by the anti-phase amplifier 18a. I do. As described above, the weighting data stored as a voltage in the capacitor 12 is charged and discharged by a learning signal from the digital computer, and is set to specified positive or negative data.

In the embodiment shown in FIG. 1, a capacitor 10 is connected, but this is not necessarily necessary since the function can also be provided by providing a circuit for latching input data outside the coupling circuit.

Here, since the weighting data stored in the capacitor 12 gradually discharges naturally, the weighting data is read out via the charge/discharge terminal 20 (hereinafter referred to as "rR/W terminal") of the capacitor 12, refreshed, and then charged again. There is a need.

FIG. 3 is a systematic diagram of neurons having a refresh function.

This neuron has a timing circuit 2 with a counter.
06, a decoder 204 that decodes the counter value from the timing circuit 206, an input selection circuit 202 that selects to which coupling circuit (216a to 216z) the input data is input based on the data from the decoder 204, and N.
coupling circuits (216a to 216z) and decoder 2
Which coupling circuit (216a to 216
a refresh selection circuit 208 that reads the weighted data of z) and selects whether to refresh it; and a refresh circuit 2 that reads the weighted data and refreshes the weighted data by comparing it with the stepped input/output characteristics.
10 (details will be described later), and N coupling circuits 216a~
216z ) and an adder 212 that adds the outputs of the S-type (
an amplifier 214 having a sigmoidal function.

The refresh operation will be explained below using FIG. 3.

The value of the counter of the timing circuit 206 is sent to the decoder 204.
is decoded to send a signal indicating which coupling circuits 216a to 216z should be refreshed to the refresh selection circuit 2.
Send to 08. The refresh selection circuit 208 selects one of the coupling circuits (temporarily referred to as the first coupling circuit 216a). The refresh circuit 210 connects the selected first coupling circuit 2
The weighting data of the capacitor 12 is read from the R/W terminal of the capacitor 16a. Weighting data is determined by comparing this weighting data with the refresh input/output characteristics shown in FIG. For example, in FIG. 4, the weighting data Vin is Vl
, < Vin < V, the value + 2 obtained from the input/output characteristics is used as weighting data to charge the first coupling circuit. The capacitor 12 is charged with this data, and the N coupling circuits are refreshed and the next first coupling circuit 21 is charged.
Since the capacitor 12 is naturally discharged by the time of refresh 6a, the weighting data Vin is reduced due to the natural discharge.

If this value is V'in, then the staircase width of this input/output characteristic is determined so that V,<V'in<V, so the weighting data can be held within the range of the staircase width, and it is natural. Refreshing can solve the discharge problem.

When the refresh of the first coupling circuit 216a is completed, the counter value of the timing circuit 206 advances by one, which is decoded by the decoder 204 and refreshed by the refresh selection circuit 208.
selects the second coupling circuit 216b. Refreshing is performed in the same manner as described above, and then the third coupling circuit 216c is selected. This is also refreshed, and finally the Nth coupling circuit 216z is also refreshed. Once the refresh is completed, the circuit returns to the first coupling circuit and repeats this cycle from then on.

Details of the refresh circuit 210 that refreshes weighted data will be explained below using the system diagram of FIG. 5.

The refresh circuit 210 includes an input amplifier 250 that amplifies the weighted data read out from the capacitor 12 , and selects a voltage for recharging the capacitor 12 by checking which range of the stepped input/output characteristic the weighted data belongs to. It consists of a selection section 252 and an output buffer 256.

The operation of refresh circuit 210 is as follows. Capacitor 12 read from R/W terminal 20 of coupling circuit
The voltage (weighting data) is amplified by the input amplifier 250. In the selection section 252, this voltage is compared with a plurality of reference voltages determined by the stepped input/output characteristics shown in FIG. 4, and a voltage for recharging the capacitive means of the neuron coupling circuit is selected.

The second selected voltage is passed through the output buffer 7256.
The signal is sent to the neuron coupling circuit and charged to the capacitor 12.

FIG. 6 shows an embodiment in which the refresh circuit of FIG. 5 is implemented using FETs. The selection section 252 in FIG. 5 is a resistor 260a.
2S260h and comparators 262a to 262f, weighted data (voltage) input via an input amplifier 258 is input, and an input larger than the reference voltage determined by the resistors 260a to 260h is applied to each of the comparisons 262a to 262f. When input, the outputs of comparators 262a to 262f are TTL.
It becomes the value of the level "old gh". The selection unit 252 also includes inverters 264a to 264f and AND gates 266a to 266f.
266e and resistors 268a to 268f and FET270
a to 270g, whose operation is performed by comparators 262a to 262a to 270g.
The signal from 62f causes inverters 264a to 264 to
A logic circuit composed of FET r and AND gates 266a to 266e selects one of the FETs 270a to 270g, makes it conductive, and outputs an output voltage determined by being divided by resistors 268a to 268f to the cover sofa 272. do. The output buffer 272 is connected to the refresh circuit 2
10 and performs impedance matching with the external circuit and outputs an output voltage.

FIG. 2 shows an embodiment in which the circuit of FIG. 1 is implemented using FETs. Positive phase amplifier 18d has FET 116a and resistor 1
16b, and the negative phase amplifier 18a is FET118.
b and a resistor 118a, the switching means 18
b is FET 118c, switching means 18c is FET 118d, and multiplier is FET 114a, 11
4b and a resistor 114C1114d.

Here, capacitors 10 and 12 also function as stray capacitances at the gate of the FET, so if they are used, L
It has the advantage of reducing the number of parts when converting to SI.

In FIG. 2, when an input signal of TTL level "old gh" is input, the capacitor 10 is charged and the FET 1
This input signal is applied to the gate of FET 16a and
The drain and source of 6a become electrically conductive. Then resistance 1
A voltage obtained by subtracting the voltage drop across the FET 116a from the power supply voltage +■ is applied to the FET 16b. The voltage charged in this capacitor lO is applied to the gate of FET 114a,
The drain and source of the ET 114a also become conductive, and a voltage obtained by subtracting the voltage drop across the FET 114a from the power supply voltage +V is applied to the resistor 114d. On the other hand, weighted data is stored in the capacitor 12 by a learning function.
If this value is the TTL level "thigh", then F
The drain and source of ET114b become conductive, and the resistance 1
FET114a and FET are connected to 14c from the power supply voltage terminal ■.
A voltage excluding the voltage drop of 114b is applied. This voltage becomes the output obtained by multiplying the input signal of the coupling circuit by the weighting data.

The learning function of the circuit shown in FIG. 2 is as follows. First, learning input data is input from a digital computer (not shown) and stored in the capacitor IO.

The voltage drop across the FET 116a is determined according to this input voltage, and a constant voltage (rVin hereinafter) is applied to the resistor 116a.
b.

The weighting data stored in the capacitor 12 is set to this voltage V
In order to get close to in, a second
Input the learning signal and switch the capacitor 12.
to charge or discharge the charge of.

Conversely, if you want to discharge the voltage accumulated in the capacitor 12,
After setting the voltage of the capacitor 10 to the TTL level "old gh" and making the FET 118b conductive, the first learning signal is transferred to the FET.
118c and conducts the capacitor I2,
A loop consisting of FETs 118b and 118C is configured to discharge charges. In this way, the weighting data can be changed by charging or discharging the capacitor 12 using the first learning signal or the second learning signal.

The weighted data stored as a voltage in the capacitor 12 is read out to an external refresh circuit via the R/W terminal, refreshed, and then recharged.

7 to 9 are application examples of the neuron coupling circuit according to the present invention. In FIG. 7, an amplifying means 16 consisting of a positive phase amplifier or a negative phase amplifier, a switching means 18c which is a learning means and whose input terminal and output terminal are electrically connected when a signal is received at the starting terminal, a capacitor 10.12, and a multiplier. 14
and an R/W terminal 20.

When the amplification means 16 is a positive phase amplifier, when the weighting data is desired to be positive data, the input data is stored as positive data in the capacitor 10, and when the switching means 18c is made conductive by the learning signal, the capacitor 12 is charged and discharged.
The weighting data can be accumulated as arbitrary positive data up to the value amplified by the positive phase amplifier 16. If negative weighting data is to be stored, negative input data may be stored in the capacitor 10 in the same manner as described above.

When the amplification means is an anti-phase amplifier, positive input data is accumulated in the capacitor 10 when negative weighting data is desired, and negative input data is accumulated in the capacitor 10 when positive weighting data is desired, and the switching means is used as described above. 18c may be made conductive.

FIG. 8 shows a configuration in which the amplifying means 16 of FIG. 7 is removed.

In FIG. 9, the multiplier 14 in FIG. 8 is replaced with a differential amplifier 15, the positive terminal of which is connected to the capacitor lO, and the negative terminal connected to the capacitor 12. As a result, if the weighting data stored in the capacitor 12 is larger than the input data stored in the capacitor IO, the output of the differential amplifier 15 becomes negative, if it is smaller, it becomes a positive output, and if they are equal, the output becomes 0. can be realized.

FIG. 10 shows another embodiment of the neuron coupling circuit according to the present invention. A capacitor 302 for storing input data, a capacitor 304 for storing weighted data, and a first capacitor 302 for storing input data.
FETs 306a and 306b conduct when receiving a learning signal from a digital computer (not shown), and FETs 306b conduct when receiving a second learning signal from the digital computer.
308a, 308b, FET 314.324 which is an N-channel enhancement type FET, and FET 310.312 which is an N-channel depletion type FET.
FET318, which is a P-channel enhancement type.
320 and F, which is a P-channel depletion type FET.
It consists of ET316.322 and resistors 326a and 326b.

The operation of the embodiment shown in FIG. 10 will be explained using FIG. 11.

In Figure 11, the voltage of the positive TTL level "old ghl" is set to "1", and the voltage of the negative TTL level "old gh+1" is set to "-".
The voltage of 1" and 0 is expressed as "0".

In the figure, when the input data of "1" is stored in the capacitor 302, FET 310 and FET 324 become conductive, and when the weighting data stored in the capacitor 304 is "1", FET 312 and FET 314 become conductive, and FET 310 and FET 324 become conductive. Power supply voltage +■ is output via FET312. If the weighting data is "0", the FETs 312, 314, 320, and 322 are non-conductive, so the output becomes "0". If the weighting data is "-IJ," FET320 and FET322 become conductive, and FE
Power supply voltage -V is output via T324 and FET322.

If the input data is "0", FET310.316.
Since 318 and 324 are non-conductive, the output is "0" regardless of the weighting data.

If the input data is "-1", FET316 and FET
318 becomes conductive, and when the weighting data is "1", FET312 and FET314 become conductive, and FET31
4 and FET316, "ζ power supply voltage -■ is output. If the weighting data is r□, FET312.3
Since 14.320.322 is non-conductive, the output becomes "0". If the weighting data is 1-1, FET320
and FET322 become conductive, and FET318 and FET32
Power supply voltage +■ is output via 0.

The learning function of the embodiment shown in FIG. 10 will be explained using FIG. 12. In FIG. 12, when the first learning signal is a signal that makes the FET conductive, it is expressed as "ON", and when it is a signal that makes the FET non-conductive, it is expressed as rOFF.

It is expressed as When the input data is "1", "0", or "-1", the operation of FET 310.316.318.324 is the same as described above. If the input data is "1" and the first learning signal is "ON", FETs 306a and 306b become conductive, and the voltage of capacitor 304 is charged and discharged via FET 310 and FET 306a, and the first learning signal is "ON". By controlling the "ON" time, intermediate values up to the power supply voltage +■ can be stored in the capacitor 304 as weighted data. If the input data is "1" and the second learning signal is rON, the voltage of the capacitor 304 is charged and discharged via FET 308b and FET 324, and this second learning signal is
By controlling the rONJ time of the learning signal, intermediate values up to the power supply voltage -■ can be stored in the capacitor 304 as weighted data.

If the input data is "-1", FET318.316
becomes conductive, and the first learning signal and the second learning signal are ON10.
FET306b or FET308 by F F control
a becomes conductive and the same learning function as described above is exhibited.

As described above, the learning function first inputs input data ("l" or '-IJ) to the capacitor 302, and charges and discharges the weighting data of the capacitor 304 by controlling the first learning signal and the second learning signal with 0N10FF. It has the effect of being able to be set to a constant value.

The weighting data of this embodiment is refreshed via the R/W terminal 330, and the refresh function is as described above.

FIG. 13 is a system diagram showing another embodiment of the neuron coupling circuit according to the present invention, and FIG. 14 is a circuit diagram showing its details. In FIG. 13, a capacitor 402 is connected between the input terminal 400 of the neuron coupling circuit and GND 410, and has the function of accumulating input data. The input terminal 400 is one input terminal 408a of the multiplier 408.
A capacitor 404 for storing weighted data is connected between the other input terminal 408b and GND 410. An R/W terminal 412 is connected to the other input terminal 408b of the multiplier 408, and weighting data is refreshed via the R/W terminal 412. Multiplier 4
A switching means 406 is connected between the intermediate terminal 408C of 08 and the input terminal 408b.

When input data is input to the input terminal 400 of the neuron coupling circuit, it is stored in the capacitor 402. Multiplier 40
8 multiplies the input data stored in the capacitor 402 by the weighted data stored in the capacitor 404, and outputs the product.

The weighting data stored in the capacitor 404 is set to a constant value by receiving the learning signal, turning on the switching means 406, and charging or discharging the charge in the capacitor 404.

The weighted data stored in capacitor 404 is R/
It is read out via the W terminal 412, refreshed by an external refresh circuit, and then charged.

FIG. 14 shows an example in which the embodiment of FIG. 13 is implemented using FETs. Multiplier 408 includes FETs 408a, 408
The switching means 406 is an FET 406a.

When the capacitor 402 has an input of "1" and the weighting data is "l", both the FETs 408a and 408b become conductive, and the output becomes "1".

In this case, if the input data or weighting data is "0", the FET 408a or 408b becomes non-conductive and the output becomes "0".

In order to bring the weighting data closer to the power supply voltage +■, the input data should be set to 71. As a result, the FET 408a may be made conductive, and a learning signal may be input to the FET 406a to make it conductive, thereby charging the FET 406a to the power supply voltage (■). The weighting data is
In order to get close to 0, set the input data to 0 and
The ET 408a is kept non-conductive, and a learning signal is input to the FET 406a to make it conductive, thereby causing the resistor 408d to consume the charge of the capacitor 404.

The weighting data is read out via the R/W terminal 410, and the capacitor 404 is recharged and refreshed.

As mentioned above, various aspects of the preferred embodiment of the present invention have been examined. For example, the multiplier has used the circuit shown in FIG. 15(a), but it can be inverted and used as shown in FIG. 15(b). It's okay,
It goes without saying that the present invention is not limited to the embodiments described above, and that many modifications can be made without departing from the spirit of the invention.

(Effects of the Invention) Since the neuron coupling circuit according to the present invention stores weighted data in the capacitive means, registers and D/A converters are not required, and the number of components is reduced, making it easy to implement into an LSI.

Further, the learning means is controlled by a learning signal and can charge and discharge the voltage stored in the capacitive means to a constant value.

Furthermore, by refreshing the weighting data, the problem of spontaneous discharge of the capacitive means can be solved.

[Brief explanation of drawings]

Fig. 1 is a system diagram showing an embodiment of a neuron coupling circuit according to the present invention, Fig. 2 is a circuit diagram showing details of the embodiment of Fig. 1, Fig. 3 is a neuron system diagram, and Fig. 4 is a refresh diagram. Figure 5 shows the input/output characteristics of the circuit; Figure 5 is a systematic diagram of the refresh circuit; Figure 6 is a circuit diagram showing details of the refresh circuit in Figure 5; Figures 7 to 9 are diagrams of the neuron coupling circuit according to the present invention. FIG. 10 is a circuit diagram showing details of the neuron coupling circuit according to the present invention, FIG. 11 is a logic value table showing the multiplication function of the embodiment of FIG. 10, and FIG. 12 is a system diagram showing another embodiment. Logical value table showing the learning function of the embodiment of FIG. 10, No. 13
14 is a circuit diagram showing details of the embodiment of FIG. 13, FIG. 15 is a circuit diagram showing an embodiment of a multiplier, and FIG. 16 is a circuit diagram showing another embodiment of the refresh coupling circuit according to the present invention. is a system diagram showing a conventional neuron, and FIG. 17 is a system diagram showing a conventional neuron coupling circuit. 12... Capacitor as capacitance means, 14... Multiplier, 18... Learning means, 20... Charge/discharge terminal, 22... Input terminal of coupling circuit, 26... Ground, 28...・First input terminal 30・
...Second input terminal, 304...Capacitor, 306a...9th FE
T, 306b...10th FET, 308a...11th FET, 308b...12th FET, 310
...1st FET, 312...5th FET, 31
4... 7th FET, 3 318... ET, 3 324... resistor, 328... child, 33 334... power line 340... 342... 252... 16... 3rd FET.・2nd FET, 320...6th FET 22...8th FET.・4th FET, 326a-1st 326b...2nd resistor, ・Input terminal, 330...Charge/discharge terminal 2...Ground, ・Positive power supply line, 336...Negative negative, 338・
...output terminal, -first learning signal input terminal, -second learning signal input terminal, -selection section.

Claims (1)

[Scope of Claims] 1. A neuron coupling circuit that changes weighting data to a specified value based on input data input to a computer and a learning signal, the neuron coupling circuit that multiplies the input data by the weighting data and outputs the result. a multiplier that multiplies input data input to a first input terminal connected to the input terminal of the combination circuit by weighting data input to a second input terminal; a second input terminal of the multiplier; capacitive means connected between grounds and for storing the weighted data as a voltage; A neuron coupling circuit comprising learning means for charging and discharging a voltage to a value specified by the computer. 2. A neuron coupling circuit that changes weighting data to a specified value based on input data input to a computer and a learning signal, the neuron coupling circuit that multiplies the input data by weighting data and outputs the result, the coupling circuit comprising: The input terminal (328) and the gate are connected,
a first FET (310), which is an N-channel FET, whose drain is connected to the positive power supply line (334), whose gate is connected to the input terminal (328), and whose drain is connected to the positive power supply line (334); a second FET (318) which is a P-channel FET; a third FET (316) which is a P-channel FET whose gate is connected to the input terminal (328) and whose drain is connected to the negative power supply line (336); A fourth FET (324) is an N-channel FET whose gate is connected to the input terminal (328) and whose drain is connected to the negative power supply line (336), and one side is connected to the ground (332) and the weighted data is transferred to the voltage. a charging/discharging terminal (330) connected to the other of the capacitors (304) for charging and discharging the voltage stored in the capacitor (304); and the capacitor (304). The other side of the gate is connected,
a fifth FET (312), which is an N-channel FET, whose drain is connected to the source of the first FET (310), and whose gate is connected to the other of the capacitor (304);
a sixth FET (320) that is a P-channel FET whose drain is connected to the source of the second FET (318) and whose source is connected to the source of the fifth FET (312);
and the gate is connected to the other of the capacitor (304),
a seventh FET (314), which is a P-channel FET, whose drain is connected to the source of the third FET (316), and whose gate is connected to the other of the capacitors (304);
an eighth FET (322) whose drain is connected to the source of the fourth FET (324) and whose source is connected to the seventh FET (314); one side is connected to the source of the sixth FET (320);
a first resistor (326a) whose other end is connected to the output terminal (338) of the coupling circuit; one side is connected to the source of the eighth FET (322) and the other is connected to the output terminal (338) of the coupling circuit; a second resistor (326b), a first learning symbol input terminal (340), and a gate connected to the first learning symbol input terminal (340),
The drain is connected to the source of the first FET (310),
A ninth FET (306a) whose source is connected to the other of the capacitors (304), whose gate is connected to the first learning signal input terminal (340), whose drain is connected to the source of the third FET (316), and whose source is connected to the other of the capacitors (304). is connected to the other of the capacitors (304), a second learning signal input terminal (342), a gate is connected to the second learning signal input terminal (342), and a drain is connected to the second FET (306b). (318), whose source is connected to the other of the capacitors 304, and a fourth FET (324) whose gate is connected to the second learning signal input terminal (342), and whose drain is connected to the second learning signal input terminal (342). a twelfth FET (308b), the source of which is connected to the other of the capacitors (304). 3. In a refresh circuit for refreshing the weighting data of a neuron coupling circuit having a capacitive means for accumulating weighted data, the voltage of the capacitive means is compared with a plurality of predetermined reference voltages to select a voltage for recharging the capacitive means. A refresh circuit characterized by comprising a selection section that selects.