JPH03201199A - Radio type alarm system - Google Patents

Abstract

PURPOSE:To save temporary malfunction due to noise or the like and to surely select an idle channel by setting up the frequency dividing ratio data of the succeeding channel if a PLL circuit can not be locked at the time of carrier sensing and then executing retrial operation. CONSTITUTION:Frequency channels 1 to 6 are allocated to respective slaves 12 connected to respective sensors 10 for detecting abnormality such as a fire, and at the time of detecting abnormality, the slave 12 is turned to a receiving state and frequency dividing ratio data are set up in the PLL circuit to execute carrier sensing. The slave 12 selects an idle channel not used by other slaves, turns its state to a transmitting state, sets up the frequency dividing ratio data of the selected channel in the PLL circuit 16, and then transmits an abnormality detecting signal to the master. If the circuit 16 can not be locked, a PLL control circuit 18 sets up the frequency dividing ratio data of the succeeding channel, and when the circuit 16 can not be set up yet, the setting of the same frequency dividing ratio data is repeated plural times until the circuit 16 is locked. Consequently, the generation of temporary malfunction due to noise or the like can be saved and the abnormality detecting signal can surely be transmitted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wireless alarm system for monitoring abnormalities such as fire.

[Conventional technology] Conventionally, in order to monitor fires at construction sites such as buildings, a slave unit with a fire detector directly attached externally was installed on the ceiling side of a warning area, and when a fire signal was received from the fire detector, A wireless alarm system has been proposed in which an abnormality detection signal is transmitted wirelessly to a parent device to notify the user of an abnormality. The slave unit has a built-in battery power supply, and can be freely installed in any desired location.

In such a wireless alarm system, for example, six frequency channels are assigned to the slave unit, and when transmitting, the slave unit first performs carrier sensing with the slave unit in the receiving state, and then selects an empty channel that is not used by other slave units. Then, the slave device is switched to the transmitting state, and the abnormality detection signal is transmitted to the goodwill using the empty channel selected by carrier sense. On the other hand, in the case of goodwill, the same six frequency channels as the slave unit are assigned, and carrier sensing of the six channels is always performed in sequence. When a carrier is detected, the reception state of the detection channel is fixed and the reception state from the slave unit is Receive an abnormality detection signal.

Here, the oscillation of the local oscillation frequency used in the carrier sense reception operation in the child device and the oscillation of the carrier frequency used during transmission using an empty channel are performed by setting frequency division ratio data for the PLL circuit.

That is, the PLL circuit consists of a frequency divider and a phase comparator,
A phase comparator compares the branch output of the reference oscillator and the branch output of a VCO (voltage controlled oscillator), and feedback controls the oscillation frequency of the vCO so that the output of the phase comparator is zero. And vc.

Any oscillation frequency can be obtained from vcO by externally changing the division ratio of the side frequency divider.

For example, if the carrier frequency of channel CHI is f t 1
= 429.175 MHz, the local oscillation frequency for carrier sense is frl = 407.475 MHz (however, the intermediate frequency f 1 = 21.7 MHz), and the PLL is configured to obtain this local oscillation frequency frl.
By setting the division ratio data in the circuit, the channel CHI
If channel CHI is an empty channel, by setting frequency division ratio data of carrier frequency ftl of channel CHI in the PLL circuit, it is possible to transmit an abnormality detection signal using channel CHI.

[Problem II to be Solved by the Invention] However, in such a conventional wireless alarm system, P of a slave device is not used for carrier sensing or transmission.
Even if frequency division ratio data is set in the LL circuit, so-called PLL lock may not be achieved in which the PLL loop operates effectively and the oscillation frequency is controlled according to the frequency division ratio, resulting in temporary malfunction due to noise etc. However, there is a problem in that PLL locking fails and transmission becomes impossible.

The present invention has been made in view of these conventional problems, and it is an object of the present invention to provide a highly reliable wireless alarm system that can reliably transmit signals even if the PLL circuit malfunctions temporarily.

[Means for Solving the Problems] To achieve this object, the present invention is configured as follows. In addition, the reference numerals of the drawings of the embodiments are also shown.

First, the present invention allocates a predetermined number (for example, 6) of frequency channels CH1 to CH6 to the slave unit 12 connected to the sensor 10 for detecting an abnormality such as a fire, and when an abnormality is detected, first the slave unit 1
2 is in the receiving state, carrier sensing is performed using the received signal obtained by oscillation based on the set of division ratio data of the local oscillation frequency fr for the PLL circuit 16 of the slave unit 12, and empty channels not used by other slave units are detected. , and then switches the child device 12 to the transmitting state and transmits the frequency division ratio data of the carrier frequency ft of the selected empty channel to the PLL circuit 16.
is set to oscillate and transmits an abnormality detection signal to the goodwill 14, and the goodwill 14- sequentially performs carrier sense on the same predetermined number of channels CHI to CH6 assigned to the child device 12, and when a carrier is detected, the signal is sent to the detection channel. The target is a wireless alarm system that is fixed and receives abnormality detection signals. 'In the present invention for such a wireless alarm system, when frequency division ratio data for carrier sensing is set in the PLL circuit 16 of the ascus 12, if the PLL circuit 16 cannot be locked, the following procedure is performed. When setting the frequency division ratio data of the channel and further setting the frequency division ratio data to the PLL circuit 16 to oscillate the carrier frequency of the empty channel, if the PLL circuit 16 cannot be locked, it will remain the same until it locks. A PLL control means 18 is provided which repeats setting of frequency division ratio data a plurality of times.

[Function] According to the wireless alarm system of the present invention having such a configuration, if the PLL circuit cannot be locked during carrier sensing, a retry operation is performed by setting the frequency division ratio data of the next channel, and the noise is reduced. It is possible to reliably select an empty channel by relieving temporary malfunctions caused by such problems. In addition, if the PLL circuit cannot lock when transmitting using an empty channel based on carrier sense, the same frequency division ratio data is set repeatedly or a trial operation is performed multiple times until the same frequency division ratio data can be locked. Therefore, malfunctions of the PLL circuit can be reliably relieved.

[Embodiment] FIG. 1 is a system configuration diagram showing the system configuration of the present invention.

In FIG. 1, 12-1.12-2. ...12
-n is an asci, each of which is connected to a fire detector 10. The asci 12-1 to 12-n have a built-in battery power source,
Power is supplied to the fire detector 10, and when the fire detector 10 generates an alarm, the radio circuit of the ascus receives the frequency to be transmitted once, and there are no radio waves from other asci. Conduct career sense to confirm that. Once carrier sense confirms that it is not being used by any other asci, it begins transmitting operations. If it is confirmed that it is being used in another ascus, it moves to the next frequency and performs the same operation.

Here, the asci 12-1 to 12-n have frequency channels of 429 MH2 band, for example, 6 channels (CH2-CH2).
Assigned.

Note that 20 is an operation indicator light that lights up during transmission operation, and 22 is an antenna.

Reference numeral 14 indicates a friendship, which receives transmitted radio waves from the asci 12-1 to 12-n. Since transmission is performed from the asci 12-1 to 12-n using any of the six frequency channels CHI to CH6, carrier sensing of the six frequency channels is performed sequentially, and if any of the channels is When a carrier is detected, it is fixed to the detection channel and receives an abnormality detection signal. When the abnormality detection signal is received, the received address of the ascus is compared with the address preset in the friendship 14, and if the two match, data processing is performed and an alarm operation is performed according to the abnormal state.

FIG. 2 is a structural diagram showing an embodiment of the asci of the present invention.

In FIG. 2, the asci 12 is provided with a CPU 24,
The functions of the transmission control section 26 and the PLL control section 18 are realized under program control of the CPU 24.

A fire reception circuit 28 is provided for the CPU 24, and a power signal line 100 drawn out from the fire reception circuit 28
A fire detector 10 is connected to. Fire receiving circuit 28
When receiving a fire detection signal from the fire detector 10, it generates a reception output to the CPU 24 and the starting circuit 30.

When the starting circuit 30 receives the fire reception output, it starts the power supply control circuit 3.
2, the battery power source 25 supplies power to the CPU 24, and the CPU 24 is powered on. That is, the CPU 24 is in a stopped state in the steady monitoring state, and when a fire detection signal is received, the CPU 24 receives power supply and performs a transmitting operation. Further, the starting circuit 30 is connected to the CPU 24
Through this control, it is possible to perform a power-off operation in which the operating state of the power supply control circuit 32 is stopped and the power supply from the battery power supply 25 is stopped.

Reference numeral 36 denotes a periodic notification circuit, which outputs a periodic notification output to the CPUs 2 and 4 and the starting circuit 30, for example, every 9 hours using a built-in timer. The starting circuit 30 receiving this periodic notification output controls the power supply control circuit 32 to supply power to the CPU 24 to start the power-on, as in the case of the fire reception output, and the CPU 24 transmits the periodic notification based on the periodic notification output. Perform the action.

Further, for the CPU 24, an address setting circuit 34, E
A nonvolatile memory 35 using EFROM and an operation indicator light 20 are connected. The address setting circuit 34 sets a group address for one group of one master device and a plurality of slave devices, and an individual address unique to the sensor. A call identification code (ID code) approved by the Minister of Posts and Telecommunications is stored in the nonvolatile memory 35, and this call identification code is transmitted first. For specified low power radio stations under the Radio Law,
It is mandatory to send a call identification signal at the beginning of transmission, and in addition, an extended group address (upper) is stored in the nonvolatile memory 35 in order to provide expandability to the group address. The operation indicator light 20 lights up when the CPU 24 starts powering on, and goes out when the power is off.

A transmitting/receiving circuit section is provided on the left side of the CPU 24.

In this transmitting/receiving circuit section, 40 is a synthesizer circuit, which includes a PLL circuit 16, a VCO 44, and an amplifier 46. The PLL circuit 16 includes a reference oscillator, a frequency divider, and a phase comparator, and forms a PLL loop together with the vCO 44. As is well known, this PLL loop compares the divided output of the reference oscillator and the divided output of the VCO 44 using a phase comparator, and performs feedback control so that the phase difference is zero by giving the output of the phase comparator to the VCO 44. It forms a phase-locked loop. The oscillation frequency of the VCO 44 is controlled by changing the frequency division ratio of a frequency divider provided in the PLL circuit 16 that divides the output of the VCO 44.

To explain a specific example, the oscillation frequency of the reference oscillator is set to 12.
If it is 8MHz, the fixed frequency division ratio is 1/10.
The standard frequency of 12.5 KHz is created by dividing the station by 24. On the other hand, if the oscillation frequency of the VCO 44 is taken as an example of the carrier frequency of channel CHI, 429.175 MHz, the oscillation frequency of the VCO 44 can be divided into 1/34334 to 12.5K.
Get Hz. And the divided output of the reference oscillator and the VCO44
The oscillation frequency of the VCO 44 is controlled so that the phase difference is zero.

Therefore, the oscillation frequency can be freely set by changing the frequency division ratio of the frequency divider that produces the frequency-divided output of the VCO 44 under the control of the CPU 24.

The output of the synthesizer circuit 40 is outputted via the signal switch 48 to the transmitting circuit 50 or the high frequency amplification/mixing circuit 54 on the receiving side. During transmission when the signal switch 48 is switched to the transmission circuit 50 side, the synthesizer circuit 4
0 oscillates one of the carrier frequencies of channels CHI to CH6.

On the other hand, during carrier sensing when the signal switch 48 is switched to the high frequency amplification/mixing circuit 54 side, channels CHI to
It oscillates a local oscillation frequency for frequency converting any carrier frequency of CH6. Here channel CHI
For example, if the carrier frequency of channel CHI is f t = 429.175 MHz, and the intermediate frequency f 1 output from the high frequency amplification/mixing circuit 54 is 21.7 MHz, then the high frequency amplification/mixing circuit 54
The local oscillation frequency frl of channel CHI for mixing circuit 54 is 407.475 MHz.

The output of the transmitting circuit 50 is applied to the antenna 22 via an antenna switch 52, and the other switching side of the antenna switch 52 is connected as an input to a high frequency amplification/mixing circuit 54.

The high frequency amplification/mixing circuit 54 receives the local oscillation frequency from the synthesizer circuit 40, converts the received channel frequency into a 21.7 MH2 intermediate frequency signal, and outputs it to the next stage intermediate frequency amplification/mixing circuit 56. The intermediate frequency amplification/mixing circuit 56 is provided with a local oscillator that oscillates a fixed frequency, and further converts the frequency of the 21.7 MHz intermediate frequency signal into a 455 KHz intermediate frequency signal. The system in which frequency conversion is performed twice by the high frequency amplification/mixing circuit 54 and the intermediate frequency amplification/mixing circuit 56 in this manner is known as a double superhetero gain system.

The output of intermediate frequency amplification/mixing circuit 56 is provided to carrier detection circuit 58 and MSK modem 60.

The carrier detection circuit 58 has a threshold value based on the white noise level when the carrier frequency is not detected, and provides the CPU 24 with a detection output indicating the presence or absence of carrier detection.

MSK modem 60 converts the received signal from intermediate frequency amplification/mixing circuit 56 into data bits 1.0 and
Converts data bit 0.1 from 24 into a predetermined frequency signal. For example, data bit 1 corresponds to 1200 Hz, and data bit 0 corresponds to 1800 Hz. M.S.
The modulation of the transmitted data by the K modem 60 is 1200 Hz or 18 Hz depending on the data bit 1.0 from the CPU 24.
00Hz frequency signal to the VC of the synthesizer circuit 40
MSK modulation is performed by supplying O441.

The operation of the transmitter circuit section and the receiver circuit section in this embodiment is as follows.
This is performed by switching the power supply by the power supply switching circuit 62. That is, when the CPU 24 starts powering on, first, power is supplied to the receiving circuit section under the control of the power supply switching circuit 62, and the carrier sensing operation of the channel to be transmitted is performed. When an empty channel is selected by the carrier sense operation, the power supply to the reception circuit section is turned off, and the power supply to the transmission circuit section is turned on, thereby performing a transmission operation. For switching the power supply to the receiving side and the transmitting side, a signal switch 48 is used.
The antenna switch 52 is switched to enable the circuit to which power is being supplied.

During the carrier sense operation performed prior to transmission, the transmission control unit 26 of the CPU 24 first sets frequency division ratio data for oscillating the local oscillation frequency fr1 of the channel CHI in the PLL circuit 16, and sets the frequency division ratio data for the carrier detection circuit 58. Check for presence of detection output. If the detection output of the carrier detection circuit 58 is not obtained, it is determined that the channel is empty, and for transmission, frequency division ratio data of the carrier frequency ftl of channel CHI is set in the PLL circuit 16 to perform an oscillation operation. On the other hand, when the detection output of the carrier detection circuit 58 is obtained, the local oscillation frequency fr2 of the next channel CH2
The frequency division ratio data is set in the PLL circuit 16, and channel switching is repeated until an empty channel is found.

The PLL control section 18 is a PLL circuit 1 controlled by the transmission control section 26.
The presence or absence of a lock accompanying the setting of frequency division ratio data for 6 is monitored. If the PLL circuit 16 is unable to lock onto the frequency division ratio data set during carrier sensing, it instructs the transmission control unit 26 to set frequency division ratio data for receiving the next channel. On the other hand, if it is detected that the PLL circuit 16 does not lock even if the frequency division ratio data is set during transmission using the selected empty channel, the same frequency division ratio data is set to the transmission control unit 26 a predetermined number of times. Command the action to repeat.

FIG. 3 is a time chart of the transmission operation in the child device of FIG.

In FIG. 3, if continuous transmission of abnormality detection signals based on sensor alarms is started by the power-on start of the CPU 24, carrier sense is first performed to select an empty channel, and then the selected empty channel is used. T
1 = Send an abnormality detection signal for 8 seconds, then T2 = 22
Repeat the transmission operation that stops. For a transmission period of T1=8 seconds, first the call identification code approved by the Minister of Posts and Telecommunications is transmitted. This call identification code has a format shown in FIG.

Following the call identification code, a mark and a transmission code are repeatedly transmitted. The mark is a series of 1's, and the transmission code includes a slave device address and data. The transmission code is composed of four frames, frame 1 to frame 4, as shown in FIG. Each frame has a start bit of 0 at the beginning and a stop bit of 1 at the end, thereby achieving frame synchronization. The 8 bits following the start bit are the data area, and frame l is the extended group address (upper)
, frame 2 is an individual address and group address (lower), frame 3 is an alarm signal, and frame 4 is a horizontal parity bit. The horizontal parity bit of frame 4 is set so that the sum of the same bit positions of frames 1 to 3 becomes, for example, an odd number of bits. Following the 8-bit data area, a parity bit is provided for each frame.

Next, the transmission operation of the child device shown in FIG. 2 will be explained with reference to the operation flow diagram of FIG. 6.

Now, if the fire detector 10 is activated, the starting circuit 30 that receives the received output from the fire receiving circuit 28 is activated by the power supply control circuit 3.
2 is turned on, power is supplied to the CPU 24 from the battery power supply 25, and the CPU 24 starts powering on and starts the sixth cycle.
The flow shown in the figure is executed.

In FIG. 6, initialization processing is first performed in step Sl (hereinafter "step" is omitted), and then in step 32, the call identification code, extended group address (upper), and address setting circuit 34 are read from the non-volatile memory 35. Settings are made to read the individual addresses and group addresses (lower), as well as the delay time randomly determined for each child device. Next, in S3, the PLL circuit 16
Set frequency division ratio data to obtain the local oscillation frequency of the receiving channel corresponding to the transmitting channel.

In this example, the first transmit channel upon power-on start is channel CHI, so PLL
Frequency division ratio data of the local oscillation frequency for receiving channel CHI is set for the circuit 16.

Next, the process proceeds to step 34, where it is determined whether or not the PLL circuit 16 is locked to the set of frequency division ratio data. If the PLL circuit 16 is successfully locked, the process proceeds to S5, where the power supply to the receiving circuit section is turned on to bring it into an operating state.

On the other hand, if the setting of the frequency division ratio data cannot be locked due to an abnormality in the PLL circuit 16 in S4, the process proceeds to S24 where the counter A is incremented, and it is determined in S23 whether the counter A has reached 5 times or not. After that, proceed to S22,
The frequency division ratio data of the next receiving channel CH2 is transferred to the PLL circuit 1.
6, and the presence or absence of locking is determined again in S4.

If the PLL circuit 16 cannot be locked, the operation of switching and setting the division ratio data for the next channel is repeated five times, and if the PLL circuit 16 cannot be locked even after switching the division ratio data five times, the process goes from S23 to 827. Next, power off is performed to stop the power supply to the CPU 24.

If the PLL circuit 16 is normally locked in S4 and the power supply to the receiver circuit section is turned on in S5, the power supply to the receiver circuit section has already been turned on in S6.

Check whether there is a carrier sense or not, that is, whether it is the first carrier sense of power-on start, and if it is the first, proceed to S7 and 3
It is in a waiting state for 00m5, and the operation of the receiving circuit section is stabilized during this time.

Next, proceed to S8 and check whether or not carrier is detected.
If there is no carrier detection, the elapsed delay time is checked at 811, and the processing at 88 and 811 is repeated until the delay time has elapsed. On the other hand, if carrier detection has been performed in S8, the process advances to S91 to check whether or not carrier detection continues for a predetermined time, and if carrier detection has been performed for more than the predetermined time, the process advances to SIO to select the next reception channel. The frequency division ratio data of is set in the PLL circuit 16, the process returns to S4, and the same process is repeated until an empty channel is obtained.

812 when the delay time elapses without carrier detection
Go to step 8, turn off the power supply to the receiving circuit, and then go to step 8.
At step 13, frequency division ratio data for obtaining the carrier frequency of the selected transmission channel (vacant channel) is set in the PLL circuit 16.

Next, in S14, it is determined whether or not the PLL circuit 16 is locked,
If the lock is successfully completed, the process advances to S15. - On the other hand, if the PLL circuit 16 cannot be locked normally, the process proceeds to 826 and increments the counter B, and after determining in S25 whether 8=5 times has been reached, the process returns to S13 and the PLL circuit 16 is reactivated.
Frequency division ratio data for obtaining the carrier frequency of the same transmission channel is set in the circuit 16. If the PLL circuit 16 cannot be locked even after setting the same frequency division ratio data five times, the process proceeds from S25 to 827 and the CP
Power off U24 and end the transmission process.

If the PLL circuit 16 is normally locked in S14,
In S15, the power supply to the transmitting circuit section is turned on to bring it into operation, and in S16, as shown in FIG. 3, the call identification code is first transmitted, then the mark and data are transmitted in 817, and the mark is and increments a counter C indicating the number of data transmissions. Next, in 819, it is determined whether the transmission number counter C has reached a predetermined value n1, for example, n=75 times, and the processes of 817 and 818 are repeated until C=75 is reached. 817 like this. When the transmitting operation for 8 seconds is completed through the process of S18, the process proceeds to S20, where the timer pauses for 2 seconds, and then the process proceeds to S21, where it is checked whether or not a fire signal is being received. If the fire signal is being received, the process returns to S2 and the transmitting operation is performed again; on the other hand, if the fire signal has stopped, the process proceeds to 827 and the CPU 24 is powered off, after which the series of processes ends.

As is clear from the above transmission operation, P
If the LL circuit 16 cannot be locked, the next channel or the same channel's frequency division ratio data is repeatedly reset or a trial operation is performed. The beam try operation reliably locks the PLL circuit and allows effective transmission operation.

In addition, although the above embodiment takes as an example the case where a fire detector is connected to the slave unit, it is also possible to connect an appropriate abnormality detector such as a gas leak detector or an intruder detector. You can also do this.

[Effects of the Invention] As explained above, according to the present invention, if the PLL circuit cannot be locked during carrier sensing, a retry operation is performed by setting the frequency division ratio data of the next channel, and the division ratio data at the time of transmission is If the PLL circuit cannot lock the frequency ratio data set, the same frequency division ratio data is set repeatedly or a trial operation is performed several times until it can lock the frequency ratio data, so temporary malfunctions due to noise etc. can be relieved. Therefore, the abnormality detection signal can be reliably transmitted.

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram of the present invention; FIG. 2 is a configuration diagram of an embodiment of the slave unit of the present invention; Figure 3 is a transmission timing chart of the slave unit of the present invention; Figure 4 is from the slave unit of the present invention. FIG. 5 is a format diagram of the transmission code transmitted from the slave device of the present invention; FIG. 6 is an operational flow diagram showing the transmission operation of the slave device of the present invention. In the figure, 10: Fire detector 12.12-1 to 12-n: Child device 14: Main device 16: PLL circuit 18: PLL control unit 20: Operation indicator 22: Antenna 24: CPU 25: Battery power source 26: Transmission control section 28: Fire reception circuit circuit 30: Starting circuit 32: Power supply control circuit 34 Near address setting circuit 35: Non-volatile memory (EEPIIOM) 36: Periodic notification circuit 40: Synthesizer circuit 44: VCO 46: Amplifier 48: Signal switch 50: Transmission circuit 52: Antenna switching circuit 54: High frequency amplification/mixing circuit 56: Intermediate frequency amplification/mixing circuit 58: Carrier detection circuit 60: MSK modem 62: Power supply switching circuit

Claims (1)

[Claims] 1. A predetermined number of frequency channels are assigned to a slave device connected to a sensor for detecting an abnormality such as a fire, and when an abnormality is detected, the local oscillation frequency division ratio data for the PLL circuit is first transmitted as a receiving state. Carrier sensing is performed using the received signal obtained by oscillation by the set to select an empty channel that is not used by other slave units, and then the slave unit is switched to the transmitting state and the carrier frequency of the selected empty channel is Frequency ratio data is set in the PLL circuit and oscillated to transmit an abnormality detection signal to the parent device, and the parent device sequentially performs carrier sense of the same predetermined number of channels assigned to the slave device, and when a carrier is detected. In a wireless alarm system that is fixed to a detection channel and receives abnormality detection signals, when frequency division ratio data is set for carrier sensing in the PLL circuit of the slave device, the PLL circuit cannot be locked. When this happens, set the division ratio data for the next channel,
Further, when frequency division ratio data is set in the PLL circuit to generate the carrier frequency of the selected channel during transmission, if the PLL circuit cannot be locked, the same frequency division ratio data is set multiple times. A wireless alarm system characterized by having a PLL control means.