JPH03198575A - Picture processing unit - Google Patents

Abstract

PURPOSE:To improve the cost performance and to attain high speed operation by generating a threshold level corresponding to each dot of a matrix to obtain a dither processing picture signal from a picture signal having an intermediate tone not from a ROM but from a simple logic circuit. CONSTITUTION:An inputted analog picture signal 1 is inputted sequentially in a form of decomposing an original picture into picture elements. The analog picture signal 1 is inputted to a 6-bit A/D converter 3 via an amplifier 2 and inputted to a comparator circuit 4 as a 6-bit digital signal. Threshold levels D0-D5 obtained in the progress of main and sub scanning addresses are changing as a random number and all of 0-63 are generated corresponding to the address. The comparator circuit 4 receiving the obtained threshold levels D0-D5 compares the digital signal from the 6-bit A/D converter 3 with the threshold level. As a result, a dither processing signal 5 obtained from the comparator circuit 4 is outputted as a dot pattern having a proper spread in a dither matrix of picture elements.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an image processing device, and particularly to an image processing device suitable for use in converting image information into a dither matrix pattern.

(Prior Art) Conventionally, images of facsimile machines, copying machines, image scanner machines, printer machines, etc. are processed after image information is converted into electrical signals by an image scanner using a COD (chargeable device) or the like. There is a device that handles signals. In these devices, in order to express the halftones of an image using binary codes of white and black, pseudo halftones are expressed by the ratio of white or black dots in a block consisting of multiple dot images. A so-called dither matrix method is often used to reproduce the This dither matrixing method has a relatively simple circuit configuration,
It is possible to express halftone images to a certain extent. For this reason, it is often used as a halftone expression method for copying machines, facsimile machines, etc.

In this dither matrix, in order to express one pixel with multiple dots, a main scan and a sub-scan in a direction perpendicular to the main scan are assigned, and between the main scan and the sub-scan, a white or black dithered image is created. A signal is output corresponding to each dot of the matrix pattern, so that the intermediate tone of each pixel of the image signal can be visually obtained.

FIG. 5 shows a block diagram of such a conventional image processing device. In FIG. 5, an analog image signal 1 obtained by an image sensor or the like is amplified by an amplifier 2 and input to a 6-bit A/D converter 3. Here, the analog image signal 1 is converted into a 6-bit digital signal and provided to the comparison circuit 4. Now, one pixel of analog image signal 1 is assigned main scanning and sub-scanning. A main scanning clock 6 is applied corresponding to each tod of the main scanning, and a sub-scanning clock 10 is input corresponding to each dot of the sub-scanning. This main scanning clock 6 is applied to an octal counter 7, and the octal counter 7 outputs AO to A2 as addresses corresponding to dots in the main scanning direction. Similarly, the sub-scanning clock 10 is applied to the octal counter 8, and the sub-scanning clock 10 outputs A3 to A5 as addresses corresponding to sub-scanning dots. As a result, AO to A5 are obtained from the octal counter 7.8 as addresses representing one coordinate of each dot when the analog image signal 1 is converted into a dither matrix. This address AO~A5 is RO
M (read-only memory) is given to 9. ROM9
A quantization signal representing a threshold value for white/black binarization at each coordinate of the matrix is stored, and threshold values DO to D5 corresponding to inputs of addresses AO to A5 are output. These threshold values DO~D5 are given to the comparator circuit 4, and 6
It is matched with the digitized signal of the analog image signal 1 from the bit A/D converter 3. As a result of this comparison, the comparator circuit 4 outputs a dithered signal 5.

In the configuration described above, the digitized signal of the analog image signal 1 by the 6-bit A/D converter 3 is
Threshold value Do- given from ROM 9 for each dot of the matrix expressed by address AO-A5 through sub-scanning.
A dithered signal 5 can be obtained as a binary signal indicating whether the corresponding dot should be expressed as white or black.

(Problems to be Solved by the Invention) Since the conventional image processing device is configured as described above, a ROM is required to store in advance the threshold values corresponding to the halftone levels of the dither matrix. However,
The address indicating the dot of the dither matrix is 4.
X4 (16th floor: 211) to 8X3 (64th floor: A), which does not require much, and the number of output threshold bits is 6 to 8.
It is about a bit.

Therefore, the required ROM capacity may be as small as 16 bytes to 64 bytes, and high speed is often required for high-speed image processing rather than capacity. However, many of the ROMs currently on the market have a capacity of 2 to 4 or more, far exceeding the required capacity, and are extremely wasteful from a cost standpoint. Furthermore, since ROM has restrictions on access time, it is disadvantageous in terms of high-speed image processing.

The present invention has been made in view of the above, and its purpose is to:
To obtain a dithered image signal from an image signal with halftones, the threshold value corresponding to each dot of the matrix is expressed as R.
The object of the present invention is to provide an image processing device which has excellent cost performance and is capable of high-speed if1 generation by generating the image from a simple logic circuit instead of from the OM.

[Structure of the invention]

(Means for Solving the Problems) An image processing device of the present invention includes a first counter that counts clocks in the main scanning direction that are generated corresponding to a matrix pattern of one pixel of an image signal, and a first counter that is perpendicular to the main scanning direction. a second counter that counts clocks generated corresponding to the sub-scanning direction; and a counter that counts clocks generated corresponding to the sub-scanning direction; logic means for generating a predetermined threshold value; and comparing one pixel of the image signal with the threshold value from the logic means to generate a binary dithered signal corresponding to each dot of the matrix pattern of pixels. and comparison means for

(Function) The first counter counts clocks in the main scanning direction that are generated corresponding to the matrix pattern of one pixel of the image signal. A second counter counts clocks generated in a sub-scanning direction perpendicular to the main scanning direction. By the above two counts, a signal generated corresponding to each dot in the matrix pattern is obtained, and by inputting this signal to the logic means, a predetermined threshold value corresponding to each dot in the matrix pattern of pixels is generated. The comparison means compares one pixel of the image signal with the threshold value from the logic means to obtain a binary dithered signal corresponding to each dot of the pixel matrix pattern.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an image processing apparatus according to an embodiment of the present invention. As shown in FIG. 1, among the main scanning addresses AO to A3 obtained from the octal counter 7, A
O is input to the exclusive OR circuit 17.19, and A
1 is input to the exclusive OR circuit 18.19, and A
2 is input to the comparator circuit 4 as DO. On the other hand, among the sub-scanning addresses 83 to A5 obtained from the octal counter 8, 83 is given to the exclusive OR circuits 17 and 18, and also inputted to the comparator circuit 4 as D3, and A4 is the exclusive OR circuit 17 and 18. A5 is applied to the OR circuit 20, and A5 is input to the comparison circuit 4 as Dl. On the other hand, the output of the exclusive OR circuit 19 is input to the exclusive OR circuit 20. In addition, the output of the exclusive OR circuit 17 is D5
The output of the exclusive OR circuit 18 is input as D4, and the output of the exclusive OR circuit 20 is input as D2 to the comparison circuit 4. The comparison circuit 4 converts the signal obtained by digitizing the analog image signal 1 by the 6-bit A/D converter 3 using the input signal of the DO-D 5 as a threshold value.
It is binarized and output as a dithered signal 5.

The operation of the above-described configuration will now be described with reference to FIGS. 2, 3, and 4. By the way, Figure 2 is 1
An explanatory diagram of a threshold pattern for converting one pixel into a dither matrix, Figure 3 is an explanatory diagram of the address coordinates Yoo-Y77 of the dither matrix, and Figure 4 is an explanatory diagram of the address coordinates AO-A5.
3 is a timing chart showing the temporal correspondence of threshold values pO to D5 inputted to the comparator circuit 4 in accordance with FIG. In addition, in FIG. 4, (A) to (F) are addresses AO, respectively.
˜A5, and (G)˜(L) indicate threshold values DO˜D5, respectively.

The input analog image signal 1 is sequentially input in the form of an original image decomposed into pixels. Here, the explanation will focus on one pixel. This analog image signal 1 is inputted to a 6-bit A/D converter 3 through an amplifier 2, and then inputted to a comparator circuit 4 as a 6-bit digital signal.

Now, as shown in Figure 3, 64 dots of Yoo-Y77 are assigned to this one pixel in order to create a dither matrix, and the white/black combination of each dot is used to form a dot in the middle of this pixel. You can express the key easily. In order to determine whether each of these dots should be expressed as black or white, it is necessary to binarize each dot. For this purpose, a distribution threshold as shown in FIG. 2 is set. Here, the main scanning direction is Yo-+ in FIG.
Y07, "10-"17・Y20″''Y27・
"30-YB2・Y2O-Y47ゝY50="
57ゝYGo'Y67ゝY70-Y77''
) to (Ylo-+Y17), (" 20-00 0
7 Y), (Y - Y), ("40-" 47
), 73037 (y −y ), (” [io-YIli7), (
Y7O-Y7□)50 57 is repeated in the same direction. Therefore, the main scanning clock 6 is output corresponding to each dot of the dither matrix, and the address AO-A3, which is the output of the octal counter, changes in the same way for each scan. On the other hand, the sub-scanning clock 10 is output corresponding to each row in the main scanning direction of the dither matrix, and addresses A3 to A5 which are the output of the octal counter 8
counts up one by one for each main scan.

Now, in FIG. 1, the relationship between the addresses AO to A5 and the threshold value DO-D5 given to the comparator circuit 4 will be explained. Now, if DO~D5 is expressed as AO~A5, it will be as follows.

DO-A2 (1) DI-A
5 (2) D2-A40(A
(Al of O) (3) D3-A3
(4) D4=-A3■A 1
(5) D5mu AOΦA 3
(6) As shown by the above formula, the threshold DO obtained according to the progress of the main scanning and sub-scanning addresses
~D5 changes randomly, and all values from 0 to 63 are generated corresponding to the address.

The comparison circuit 4, which receives the threshold values DO to D5 obtained in the above manner, compares the digital signal from the 6-bit A/D converter 3 with this threshold value. As a result, the dithered signal 5 obtained by the comparator circuit 4 is output as a dot pattern with an appropriate spread in the dither matrix of pixels.

Note that the addresses AO to A5 shown in the above embodiment are set to the threshold value D.
The combination of exclusive OR circuits for converting to O to D5 is an example, and other combinations may be used to obtain threshold values DO to D5 that make one cycle for the 0 to 63 counts of addresses AO to A5. You can also use it as

〔Effect of the invention〕

As described above, according to the present invention, the threshold value in the dither matrix can be configured using a general logic circuit without using ROM, which is excellent in cost performance and low power consumption, and the access time is short. An image processing device suitable for high-speed image processing can be realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an image processing device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of a threshold pattern for converting one pixel into a dither matrix obtained with the configuration of FIG. 1,
FIG. 3 is an explanatory diagram of address coordinates of a dither matrix, FIG. 4 is a block diagram of a conventional image processing device, and FIG. 5 is a block diagram of a conventional device. 1...Analog image signal, 2...Amplifier, 3...
6-bit A/D converter, 4... Comparison circuit, 5... Dither signal, 6... Main scanning clock, 7, 8... 8
digit counter, 9...ROM, 10...sub-scanning clock, 17-20...exclusive OR circuit.

Claims (1)

[Claims] a first counter that counts clocks in the main scanning direction generated corresponding to a matrix pattern of one pixel of the image signal; and a second counter that counts clocks generated in the subscanning direction perpendicular to the main scanning direction. a counter, logic means for generating a predetermined threshold corresponding to each dot of a matrix pattern of pixels based on the output of the first counter and the output of the second counter, and one pixel of the image signal. an image processing apparatus, comprising comparing means for comparing the output signal with a threshold value from the logic means and generating a binary dithered signal corresponding to each dot of a matrix pattern of pixels.