JPH03196331A - Data pattern detecting circuit - Google Patents

Abstract

PURPOSE:To suppress the increase of power consumption of a shift register by setting a use clock of the shift register to a lower frequency than a transfer data synchronizing clock. CONSTITUTION:The circuit is provided with a flip-flop (FF) 1 being a frequency dividing circuit, FFs 2, 3 being shift registers, an FF 4 for outputting a detecting signal, inverters 5, 6 for specifying a detection pattern from a parallel output of the shift register, and an OR gate 7 for taking OR of the parallel output of the shift register and discriminating whether it is a specific pattern or not. In such a state, at the time of detecting the specific pattern contained in transfer data, a frequency dividing clock of a synchronizing clock is generated, and by using this frequency dividing clock, the data transfer is executed, and the specific pattern of its transfer data is detected. Accordingly, a use clock frequency of the shift register can be made lower than a synchronizing clock frequency of the transfer data. In such a way, an increase of power consumption of the shift register is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data pattern detection circuit that is installed in a device that transfers data using a synchronous clock and detects a specific pattern included in the transferred data. .

[Conventional technology] Conventionally, data transfer is performed using a synchronous clock,
As a method for detecting a specific pattern contained in the data, a shift register is configured using the synchronization clock as a clock, and the specific pattern is detected from the parallel output of this shift register.

[Problems to be Solved by the Invention] However, in the above conventional example, as the data transfer speed increases, the frequency of the synchronization clock used increases, so the power consumption of the shift register used for detecting the data pattern increases. increases.

For this reason, in LSI, etc., the circuit scale can be reduced,
For example, there was a drawback that it forced a change from a plastic package to a ceramic package.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data pattern detection circuit that can suppress a shift register for data pattern detection to a low frequency and avoid an increase in power consumption.

[Means for Solving the Problems] The present invention provides a data pattern detection circuit for a device that transfers data using a synchronous clock, in which a frequency-divided clock of the synchronous clock is used to detect a specific pattern included in transferred data. The frequency-divided clock is used to transfer data, and a specific pattern of the transferred data is detected.

[Function] In the present invention, a frequency-divided clock is generated from a synchronous clock of transfer data, and a shift register is configured using the rising edge and falling edge of the frequency-divided clock as clocks, thereby making it possible to use the shift register. The clock frequency can be lower than the synchronous clock frequency of the transfer data, and an increase in power consumption of the shift register can be limited.

[Embodiment] FIG. 1 is a circuit diagram showing a data pattern detection circuit according to an embodiment of the present invention.

This data pattern detection circuit detects a specific pattern
It has a configuration that detects "otoooi", and includes flip-flop 1 (FF1) as a frequency divider circuit and flip-flops 2.3 (FF2, FF
3) and a flip-flop 4 (FF
4), an inverter 5.6 for specifying a detected pattern from the parallel output of the shift register, and an OR gate 7 for determining whether the parallel output of the shift register is a specific pattern or not.

The clock input terminal CLK of the FFI has a synchronous clock C.
LOCKI is input. This synchronous clock CLO
CKI is a synchronization clock for transfer data.

The data terminal of the FFI is connected to its inverted output terminal Q. As a result, FFI becomes CLOCKI's 2
It operates as a frequency divider circuit, and from output terminal Q, CLOCK
CLOCK2 with a frequency of 1/2 of CLOCK1 is output, and CLOCK3 with a polarity inverted at a frequency of 1/2 of CLOCK1 is output from the inverted output terminal Q.

FF2 and FF3 each have four data terminals D1
~D4, D5~D8 and output terminal Ql-Q4, Q5~
A 4-bit shift register is constructed by cascading Q8, and the first data terminals DI and D
5 is sequentially shifted based on the clock input. In addition, the output terminal Q of each FF2 and FF3
l-Q4. Q5 to Q8 are directly or inverter 5.6
The signal is input to the OR gate 7 via.

Furthermore, FF2 receives the frequency-divided CLOCK2 of the FFI as a clock signal, and operates at the rising edge of CLOCR2.

On the other hand, FF2 receives the inverted frequency-divided CLOCK3 of FFI as a clock signal, and operates at the rising edge of CLOCK3. Therefore, each FF2 and FF3 has a transfer lock operating speed of 172.

Furthermore, inverters 5 and 6 are connected to output terminals Q5 and Q of FF3.
7, and the OR gate 7 has all inputs “
0”, a specific pattern “ooootoooi”
The detection signal of is output to FF4. In FF4, the above CL
It operates using OCK2 as a clock input, and sends the output of OR gate 7 to the pattern detector.

FIG. 2 is a time chart showing the circuit operation of such a configuration.

Here, when the data "00010001" is input, this data is alternately shifted in each FF2.3, and it appears that the data is transferred to CLOCKI at the transfer rate, and Ql is transferred to each output terminal.
The data is transferred in the order of +Q5 → Q2 → Q6 → Q3 → Q7 → Q4 → Q8. And exactly “
oo.

When the data of "10001" arrives, the output "1" of Ql and Q3 becomes "O" by the inverter 5.6, all the inputs of the OR gate 7 become "0", and a detection signal is output. and a specific pattern “oooiooo
ot'' is detected.

7...or gate.

It is of course possible to detect other patterns by changing the connection position of the inverter.

[Effects of the Invention] According to the present invention, by setting the clock used by the shift register to a lower frequency than the synchronization clock for transfer data,
This has the effect of suppressing the increase in power consumption of the shift register, increasing the efficiency of gate usage in LSI, and avoiding package bottlenecks.

Claims (1)

[Claims] In a data pattern detection circuit of a device that transfers data using a synchronous clock, when detecting a specific pattern included in transferred data,
A data pattern detection circuit characterized in that it generates a frequency-divided clock of the synchronization clock, performs data transfer using the frequency-divided clock, and detects a specific pattern of the transferred data.