JPH03191407A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To contract chip size and to reduce power consumption by preparing a timing adjusting circuit, a clock output terminal and a clock switching circuit and controlling an output latch circuit by a clock signal outputted from the clock switching circuit. CONSTITUTION:The clock switching signal 3 selects a clock pulse CK2 outputted from a timing adjusting circuit 2. Although the delay time of an internal logical circuit 1 is not outputted, output data DTO2 can be normally obtained because a clock signal CK1 is a repeating signal. When frequency to be used is previous ly designed so as to satisfy conditions that the phase relation between the input signal DTO1 of an output latch circuit 4 and an input clock CK is included within the phase allowance of the circuit 4, a proper phase allowable range of input data DTI and the clock signal CK1 is specified and delay relation between the data DTI and the output data DTO2 of the circuit 4 is specified, the device can be normally driven and the number of delay elements can be reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and particularly to an ultrahigh-speed digital circuit device in which an internal logic circuit and an output latch circuit are formed on a GaAs substrate using a plurality of Schottky junction field transistors. The present invention relates to a semiconductor integrated circuit device suitable for circuits.

[Conventional technology]

With the advancement of high-speed digital signal processing technology including optical communication and measurement, the importance of ultra-high-speed Gaps digital ICs that operate at several Gb/s (3 to 5 Gb/S) is increasing. In such a high-speed ICE, an output sub-circuit is required to shape the output waveform and determine the output timing.

However, as the speed of ultrahigh-speed GaAs digital ICs increases, it is becoming difficult to adjust the phase (timing) between the output of the child circuit and the output of the internal logic circuit.

The application fields of ultrahigh-speed GaAs digital ICs can be roughly divided into the following two areas.

(1) Communication field such as optical communication In this applied field, the clock signal is a repetitive signal, often a sine wave, and has a frequency of 2 to 5 GHz. However, one frequency per system is required, and wideband performance is not essential.

(2) Field of signal processing such as measurement The feature of this application field is that it requires ultra-high bandwidth from DC to 5 GHz or more. The clock signal may also be an aperiodic signal rather than a repeating pattern such as a sine wave.

From the standpoint of versatility, the Ga3 digital IC must be applicable to both of the above fields. However, some conventional methods have had problems in terms of suitability for both fields. A conventional semiconductor integrated circuit device of this type will be described below with reference to the drawings.

FIG. 4 is a schematic diagram showing an example of a conventional semiconductor integrated circuit device of this type. Figure 5 shows that.

The timing diagram is shown below.

In FIG. 4, input data OTI is input to an internal logic circuit 1, and after performing predetermined signal processing according to a clock signal CKI, its output data DT01 is supplied to an output latch circuit 4.

The delay circuit 5 delays and adjusts the timing of the clock signal CKI, and then supplies the output α-clock signal CKO as a timing clock to the output latch circuit 4.

The output latch circuit 4 receives output data DT of the internal logic circuit l.
O1 is output according to output clock signal CKO2, and is output as waveform-shaped and timed high-speed output data DTO2.

FIG. 6 shows the second diagram of a conventional semiconductor integrated circuit 1vct of this type.
This is a professional diagram showing an example.

In FIG. 6, there is no internal delay circuit, and the timing clock for the output latch circuit 4 is supplied from the outside (CN3).

In this example, the delay time is adjusted externally, thereby achieving ultra-wideband performance from DC to 5 GHz or more.

[Problem to be solved by the invention]

In the first example, the conventional semiconductor integrated circuit device described above is configured to supply the tying clock for the output child circuit 4 from the internal delay circuit 5. Although it has the advantage of being applicable to both the field of measurement and the field of measurement, there are problems with the delay circuit 5 for timing adjustment as described below.

As shown in FIG. 5, in order for this semiconductor integrated circuit device to operate over a wide band, it is necessary to provide a delay time to the clock signal CKI in order to correct the delay time t of the internal logic circuit l. The amount of delay caused by the circuit 5 is expected to be approximately several hundred 98 ec-1 nsec.

Therefore, delay circuit 5! ! The required performance is as follows.

(1) It must have a delay amount of several hundred psec-1n5ec, and at the same time as (z) l), it must have an ultra-high bandwidth from DC to 5 GHz or more. It is constructed using a circuit similar to a logic gate or a modified circuit thereof.

In this case, the problems summarized below arise in this first example.

(1) In order to achieve ultra-high speed of the entire IC, the amount of delay of the basic logic gate when no load is applied must be reduced to the minimum of 20 to 5 Q p8eC.

(2) To obtain a delay amount of several hundred psec-1n5ec by cascading basic logic gates, approximately 50 stages are required, which increases the area occupied by the delay circuit and the power consumption.

This drawback becomes extremely serious as the number of output dual circuits increases, and becomes a major hindrance to lower power consumption and chip size reduction.

(3) When adding a circuit element to a basic logic gate to increase the amount of delay per gate, this circuit element becomes capacitive, which inevitably impairs the broadband performance of the basic logic gate and significantly lowers the maximum operating frequency.

Therefore, in this case, the user needs additional parts such as a driver circuit and a delay circuit for distributing and driving a clock signal of 5 GHz or more outside the IC, and also requires a mounting technique for these.

All of the additional components require ultra-high frequency characteristics, which has the drawback of increasing system cost and power consumption.

[Means to solve kneecap problem]

The semiconductor integrated circuit device of the present invention is a first embodiment of the semiconductor integrated circuit device.

an internal logic circuit that performs predetermined processing on input data according to a signal; a timing adjustment circuit that performs predetermined timing adjustment on the [a] and [a] signal and outputs the result; and an output clock signal of the timing adjustment circuit. A clock output terminal outputs to the outside, and a switching control signal outputs the output clock signal of the timing adjustment circuit and a second clock signal from the outside.
Kuro.

A clock switching circuit that selects and outputs one of the two signals, and an output clock of this clock switching circuit.

and an output latch circuit that checks and outputs the output data of the internal logic circuit according to the signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of tl/c1 of the present invention.

This embodiment includes an internal logic circuit 1 that performs predetermined logic processing on input data DTI according to a first clock signal CKl, and an inverter I21, and outputs the first clock signal CKIK after performing predetermined timing adjustment. a clock output terminal TCKO that outputs the output clock signal CK2 of the timing adjustment circuit 2 to the outside, and a clock output terminal TCKO that outputs the output clock signal CK2 of the timing adjustment circuit 2 and a second clock from the outside according to the switching control signal SCK. A clock switching circuit 3 selects and outputs either one of the signals CK3, and output data D of the internal logic circuit 1 according to the output clock signal CK of the clock switching circuit 3.
The configuration includes an output latch circuit 4 that latches and outputs TO1.

Next, the operation of this embodiment will be explained.

FIG. 2 is a timing chart of signals of various parts for explaining the operation of this embodiment.

First, the application to the communication field described above will be explained.

The characteristics of this field are that the frequency used is specified and determined in advance, and the clock signal is a repetitive signal.

When applied to this field, the clock switching circuit 3 selects the output clock pulse CK2 of the timing adjustment circuit 2, and the timing at this time is shown in FIG. In this case, the delay time of internal logic circuit 1 is 1. However, since the clock signal CKI is a repetitive signal, normal output data DTO2 can be obtained.

This embodiment will operate normally if it is designed in advance so that the following conditions are satisfied at the frequency used.

(1) The phase relationship between the input signal (DTOI) of the output slave circuit 4 and the input clock signal (CK) of the output slave circuit 4 must be within the output latch circuit 40 phase margin.

(2) Input data DTI and first clock signal CK
The appropriate phase tolerance range with l is clear.

(3) The delay relationship between the input data DTI and the output data DTO2 of the output latch circuit 4 is clear.

In the communication field, the frequencies used are predetermined, so the above conditions can be easily found and set at the time of design. Therefore, this embodiment can be easily operated at specified frequencies. In this case, the timing adjustment circuit 2 has the inverter I21 set to 1.
Since only one stage is required, the number of delay elements can be significantly reduced compared to the conventional example.Also, timing clocks can be applied externally.

No further input is required.

Next, operations in fields such as measurement that require broadband performance will be explained.

For this field, the clock switching circuit 3 selects the second clock signal CK3 for external timing.

In this case, the DC to several Gb /s ultra-wideband characteristics can be obtained.

In this embodiment, the clock output terminal T'cx.

Therefore, there is no need for an external additional circuit such as a clocked dual driver, which is conventionally required, and increases in system cost and power consumption can be suppressed.

FIG. 3 is a circuit diagram of a timing adjustment circuit according to a second embodiment of the present invention. Note that the connections between blocks other than the timing adjustment circuit and between the processors and the processors are the same as in the first embodiment.

The timing adjustment circuit 2 of this embodiment includes four inverter stages 4 of cascade-connected even stages that delay the first clock signal CKI by a predetermined time, and a circuit 4 that delays the first clock signal CKI by a predetermined time. Stage inverter I
The configuration includes an inverter 5 and NOR gates G1 to G3 forming a selection circuit that selects and outputs one of the four output signals.

This second embodiment has the following advantages.

In the first embodiment, stable high-speed operation is shown for a single predetermined frequency, but stable operation is not necessarily guaranteed when the frequency changes. That is, unlike the conventional example, the timing adjustment circuit 2 has a delay time 1 of the internal logic circuit 1.
This is because o is not accurately corrected, so if the repetition frequency is changed, there may be a frequency at which the rising edges of the data input (DTOI) of the output latch circuit 4 and the clock signal CK overlap. Note that in high-speed GaAs digital ICs, output 2. The switching time for rising and falling data in the child circuit 4 is about 1100p.

On the other hand, in the second embodiment, the output 2. Child circuit 4
The rise time of the clock input can be delayed or not delayed by four stages of inverters.

The delay time of the inverter in the ultra-high speed GaAs IC is 30~
50 p8, the timing adjustment circuit 2 of this embodiment can provide a delay time of 120 to 200 ps.

That is, it can be seen that this second embodiment has versatility in that it can easily support various communication systems using different frequencies.

〔Effect of the invention〕

As explained above, the present invention provides a timing adjustment circuit that performs timing adjustment on a first clock signal, a clock output terminal that outputs an output clock signal of the timing adjustment circuit to the outside, and a clock output terminal that outputs an output clock signal of the timing adjustment circuit. By providing a clock switching circuit that switches between the clock signal and the second clock signal from the outside, and controlling the output latch circuit using the output clock signal of this clock switching circuit, the number of tens of gates that were conventionally required for the delay circuit can be reduced. Since it can be reduced to a few gates, the chip size and power consumption can be reduced, and external additional circuits can be simplified, reducing system cost and power consumption. , and has the effect of improving versatility for various application fields without impairing the original ultra-high speed.

[Brief explanation of drawings]

1 and 2 are a diagram of a first embodiment of the present invention and a timing diagram of signals of each part to explain the operation of this embodiment, and FIG. 3 is a diagram of a second embodiment of the present invention. FIGS. 4 and 5 are a circuit diagram of an example timing adjustment circuit, respectively, and a diagram of a first example of a conventional semiconductor integrated circuit device, and a timing diagram of signals of each part for explaining the operation of this example. FIG. 6 is a block diagram of a second example of a conventional semiconductor integrated circuit device. 1... Internal logic circuit, 2*2k... Timing adjustment circuit, 3... Clock switching circuit,
4...Output, child circuit, 5...Delay circuit, G1-G3...NOR gate, II to I5
．． I21... Inverter, T CKO...
...Clock output terminal.

Claims (2)

[Claims] (1) an internal logic circuit that performs predetermined processing on input data according to a first clock signal; a timing adjustment circuit that performs predetermined timing adjustment on the first clock signal and outputs the result; a clock output terminal that outputs an output clock signal to the outside; a clock switching circuit that selects and outputs either the output clock signal of the timing adjustment circuit or a second clock signal from the outside according to a switching control signal; 1. A semiconductor integrated circuit device comprising: an output latch circuit that latches and outputs output data of the internal logic circuit according to an output clock signal of a clock switching circuit. (2) A timing adjustment circuit includes cascade-connected even-numbered inverters that delay a first clock signal by a predetermined time, and a final stage of the first clock signal and the even-numbered inverters according to a selection control signal. 2. The semiconductor integrated circuit device according to claim 1, further comprising a selection circuit that selects and outputs one of the output signals.